INA821 35 - V Offset, 7-nV/ HZ Noise, Low-Power, Precision Instrumentation Amplifier

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INA821
SBOS893D – AUGUST 2018 – REVISED JUNE 2020
INA821 35-µV Offset, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier

1 Features 3 Description
•
1 Low offset voltage: 10 µV (typ), 35 µV (max) The INA821 is a high-precision instrumentation
amplifier that offers low power consumption and
• Gain drift: 5 ppm/°C (G = 1), operates over a wide single-supply or dual-supply
35 ppm/°C (G > 1) (max) range. A single external resistor sets any gain from 1
• Noise: 7 nV/√Hz to 10,000. The device has high precision as a result
• Bandwidth: 4.7 MHz (G = 1), 290 kHz (G = 100) of super-beta input transistors, which provide low
input offset voltage, offset voltage drift, input bias
• Stable with 1-nF capacitive loads
current, and input voltage and current noise.
• Inputs protected up to ±40 V Additional circuitry protects the inputs against
• Common-mode rejection: 112 dB, G = 10 (min) overvoltage up to ±40 V.
• Power supply rejection: 110 dB, G = 1 (min) The INA821 is optimized to provide a high common-
• Supply current: 650 µA (max) mode rejection ratio. At G = 1, the common-mode
• Supply range: rejection ratio exceeds 92 dB across the full input
common-mode range. The device is designed for low-
– Single-supply: 4.5 V to 36 V voltage operation from a 4.5-V single supply, and
– Dual-supply: ±2.25 V to ±18 V dual supplies up to ±18 V.
• Specified temperature range: –40°C to +125°C The INA821 is available in 8-pin SOIC, VSSOP, and
• Packages: 8-pin SOIC, VSSOP, and WSON WSON packages, and is specified over the –40°C to
+125°C temperature range.
2 Applications
Device Information(1)
• Analog input module PART NUMBER PACKAGE BODY SIZE (NOM)
• Flow transmitter SOIC (8) 4.90 mm × 3.91 mm
• Battery test INA821 VSSOP (8) 3.00 mm × 3.00 mm
• LCD test WSON (8) 3.00 mm x 3.00 mm
• Electrocardiogram (ECG) (1) For all available packages, see the package option addendum
• Surgical equipment at the end of the data sheet.
• Process analytics (pH, gas, concentration, force

and humidity)
INA821 Simplified Internal Schematic Typical Distribution of Input Stage Offset Voltage
+VS
Drift
Over-
30
-IN Voltage + 10 k 10 k
Protection 25
±
RG
24.7 k ± 20
Amplifiers (%)
RG OUT
24.7 k +
15
RG
±
Over- REF 10
+IN Voltage + 10 k 10 k
Protection
5
-VS
49.4 k: 0
G 1 VO G V IN V IN VREF
RG -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Input Stage Offset Voltage Drift (PV/qC) D002
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA821
SBOS893D – AUGUST 2018 – REVISED JUNE 2020 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 26
2 Applications ........................................................... 1 9 Application and Implementation ........................ 26
3 Description ............................................................. 1 9.1 Application Information............................................ 26
4 Revision History..................................................... 2 9.2 Typical Application .................................................. 29
9.3 Other Application Examples.................................... 31
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 32
7 Specifications......................................................... 5 11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Layout Example .................................................... 33
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 34
7.4 Thermal Information .................................................. 5 12.1 Device Support .................................................... 34
7.5 Electrical Characteristics........................................... 6 12.2 Documentation Support ........................................ 34
7.6 Typical Characteristics: Table of Graphs .................. 8 12.3 Receiving Notification of Documentation Updates 34
7.7 Typical Characteristics ............................................ 10 12.4 Support Resources ............................................... 34
12.5 Trademarks ........................................................... 34
8 Detailed Description ............................................ 19
12.6 Electrostatic Discharge Caution ............................ 34
8.1 Overview ................................................................. 19
12.7 Glossary ................................................................ 34
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20 13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2019) to Revision D Page
• Added DRG (WSON) package and associated content to data sheet .................................................................................. 1
Changes from Revision B (May 2019) to Revision C Page
• Changed DGK (VSSOP) package from advanced information (preview) to production data (active) ................................... 1
• Changed Figure 9, Typical Distribution of Input Offset Current, to show correct image ...................................................... 11
• Changed Figure 27, Typical Distribution of Gain Error, G = 1, to show improved data....................................................... 14
Changes from Revision A (December 2018) to Revision B Page
• Added 8-pin DGK (VSSOP) advanced information package and associated content to data sheet ..................................... 1
• Changed Applications bullets ................................................................................................................................................. 1
Changes from Original (August 2018) to Revision A Page
• First release of production-data data sheet ........................................................................................................................... 1
2 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated
Product Folder Links: INA821

INA821
www.ti.com SBOS893D – AUGUST 2018 – REVISED JUNE 2020
5 Device Comparison Table
DEVICE DESCRIPTION GAIN EQUATION RG PINS AT PIN

35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, High-
INA821 G = 1 + 49.4 kΩ / RG 2, 3
Bandwidth, Precision Instrumentation Amplifier
35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,
INA819 G = 1 + 50 kΩ / RG 2, 3
Precision Instrumentation Amplifier
INA818 G = 1 + 50 kΩ / RG 1, 8
INA828 G = 1 + 50 kΩ / RG 1, 8
25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ,
INA333 G = 1 + 100 kΩ / RG 1, 8
Chopper-Stabilized INA
20-mV to ±10-V Programmable Gain IA With 3-V or 5-V
PGA280 Digital programmable N/A
Differential Output; Analog Supply up to ±18 V
G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V
INA159 G = 0.2 V/V N/A
Conversion
PGA112 Precision Programmable Gain Op Amp With SPI Digital programmable N/A
Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

INA821
6 Pin Configuration and Functions
D and DGK Packages DRG Package

8-Pin SOIC and 8-Pin VSSOP 8-Pin WSON
Top View Top View
±IN 1 8 +VS
±IN 1 8 +VS
RG 2 7 OUT
RG 2 7 OUT
RG 3 6 REF Thermal
Pad
RG 3 6 REF
+IN 4 5 ±VS
+IN 4 5 ±VS
Not to scale
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
–IN 1 I Negative (inverting) input
+IN 4 O Positive (noninverting) input
OUT 7 — Output
RG 2, 3 I Gain setting pin. Place a gain resistor between pin 2 and pin 3.
REF 6 — Reference input. This pin must be driven by a low impedance source.
–VS 5 — Negative supply
+VS 8 — Positive supply
Thermal pad — — Thermal pad internally connected to –VS. Connect externally to –VS or leave floating.

INA821
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage –20 20 V
Voltage –40 40
Signal input pins V
REF pin –20 20
Signal output pins (–Vs) – 0.5 (+Vs) + 0.5 V
Output short-circuit (2) Continuous
Operating Temperature, TA –50 150
Junction Temperature, TJ 175 °C
Storage Temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Single-supply 4.5 36
Supply voltage, VS V
Dual-supply ±2.25 ±18
Specified temperature, TA Specified temperature –40 125 °C
7.4 Thermal Information

INA821
THERMAL METRIC (1) D (SOIC) DGK (VSSOP) DRG (WSON) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 119.6 215.4 55.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.3 66.3 57.9 °C/W
RθJB Junction-to-board thermal resistance 61.9 97.8 28.6 °C/W
ψJT Junction-to-top characterization parameter 20.5 10.5 1.8 °C/W
ψJB Junction-to-board characterization parameter 61.4 96.1 28.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 12.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

INA821
7.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
INA821ID,
10 35
INA821DRG
INA821IDGK 10 40
Input stage offset µV
VOSI INA821ID,
voltage (1) (2) 75
TA = –40°C to +125°C (3) INA821DRG
INA821IDGK 80
vs temperature, TA = –40°C to +125°C 0.1 0.4 µV/°C
INA821ID,
50 350
INA821DGK
Output stage offset µV
VOSO INA821DRG 50 400
voltage (1) (2)
TA = –40°C to +125°C (3) 850
vs temperature, TA = –40°C to +125°C 5 µV/°C
G = 1, RTI 110 120
Power-supply rejection G = 10, RTI 114 130

PSRR dB
ratio G = 100, RTI 130 135
G = 1000, RTI 136 140
zid Differential impedance 100 || 1 GΩ || pF
Common-mode
zic 100 || 7 GΩ || pF
impedance
RFI filter, –3-dB
45 MHz
frequency
(V–) + 2 (V+) – 2
VCM Operating input range (4) V
VS = ±2.25 V to ±18 V, TA = –40°C to +125°C See Figure 51 to Figure 54
Input overvoltage range TA = –40°C to +125°C (3) ±40 V
At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
92 105
G=1
112 125
Common-mode rejection G = 10
CMRR dB
ratio At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,
132 145
G = 100
140 150
G = 1000
BIAS CURRENT
VCM = VS / 2 0.15 0.5
IB Input bias current nA
TA = –40°C to +125°C 2
VCM = VS / 2 0.15 0.5
IOS Input offset current nA
TA = –40°C to +125°C 2
NOISE VOLTAGE
Input stage voltage f = 1 kHz, G = 100, RS = 0 Ω 7 nV/√Hz

eNI
noise (5) fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.14 µVPP
Output stage voltage f = 1 kHz, RS = 0 Ω 65 nV/√Hz

eNO
noise (5) fB = 0.1 Hz to 10 Hz, RS = 0 Ω 2.5 µVPP
f = 1 kHz 130 fA/√Hz
In Noise current
fB = 0.1 Hz to 10 Hz, G = 100 4.7 pAPP
GAIN
G Gain equation 1 + (49.4 kΩ / RG) V/V
Range of gain 1 10000 V/V
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI2 + (ΔVOSO / G)2].
(3) Specified by characterization.
(4) Input voltage range of the Instrumentation Amplifier input stage. The input range depends on the common-mode voltage, differential
voltage, gain, and reference voltage. See Typical Characteristic curves Figure 51 through Figure 54 for more information.
(5) Total RTI voltage noise is equal to: eN(RTI) = √[eNI2 + (eNO / G)2].

INA821
Electrical Characteristics (continued)

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
G = 1, VO = ±10 V ±0.005% ±0.025%
G = 10, VO = ±10 V ±0.025% ±0.15%
GE Gain error
G = 100, VO = ±10 V ±0.025% ±0.15%
G = 1000, VO = ±10 V ±0.05%
G = 1, TA = –40°C to +125°C ±5
Gain vs temperature (6) ppm/°C
G > 1, TA = –40°C to +125°C ±35
G = 1 to 10, VO = –10 V to 10 V, RL = 10 kΩ 1 10
G = 100, VO = –10 V to 10 V, RL = 10 kΩ 15
Gain nonlinearity ppm
G = 1000, VO = –10 V to 10 V, RL = 10 kΩ 10
G = 1 to 100, VO = –10 V to 10 V, RL = 2 kΩ 30
OUTPUT
(V–) +
Voltage swing (V+) – 0.15 V
0.15
Load capacitance
1000 pF
stability
Closed-loop output
ZO f = 10 kHz 1.3 Ω
impedance
ISC Short-circuit current Continuous to VS / 2 ±20 mA
FREQUENCY RESPONSE
G=1 4.7 MHz
G = 10 970
BW Bandwidth, –3 dB
G = 100 290 kHz
G = 1000 30
SR Slew rate G = 1, VO = ±10 V 2.0 V/µs
0.01%, G = 1 to 100, VSTEP = 10 V 6
0.01%, G = 1000, VSTEP = 10 V 40
tS Settling time µs
0.001%, G = 1 to 100, VSTEP = 10 V 10
0.001%, G = 1000, VSTEP = 10 V 50
REFERENCE INPUT
RIN Input impedance 10 kΩ
Voltage range (V–) (V+) V
Gain to output 1 V/V
Reference gain error 0.01%
POWER SUPPLY
Single-supply 4.5 36
VS Power-supply voltage V
Dual-supply ±2.25 ±18
VIN = 0 V 600 650
IQ Quiescent current µA
vs temperature, TA = –40°C to +125°C 870
(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

INA821
7.6 Typical Characteristics: Table of Graphs

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
Table 1. Table of Graphs
DESCRIPTION FIGURE
Typical Distribution of Input Stage Offset Voltage Figure 1
Typical Distribution of Input Stage Offset Voltage Drift Figure 2
Typical Distribution of Output Stage Offset Voltage Figure 3
Typical Distribution of Output Stage Offset Voltage Drift Figure 4
Input Stage Offset Voltage vs Temperature Figure 5
Output Stage Offset Voltage vs Temperature Figure 6
Typical Distribution of Input Bias Current, TA = 25°C Figure 7
Typical Distribution of Input Bias Current, TA = 90°C Figure 8
Typical Distribution of Input Offset Current Figure 9
Input Bias Current vs Temperature Figure 10
Input Offset Current vs Temperature Figure 11
Typical CMRR Distribution, G = 1 Figure 12
Typical CMRR Distribution, G = 10 Figure 13
CMRR vs Temperature, G = 1 Figure 14
CMRR vs Temperature, G = 10 Figure 15
Input Current vs Input Overvoltage Figure 16
CMRR vs Frequency (RTI) Figure 17
CMRR vs Frequency (RTI, 1-kΩ source imbalance) Figure 18
Positive PSRR vs Frequency (RTI) Figure 19
Negative PSRR vs Frequency (RTI) Figure 20
Gain vs Frequency Figure 21
Voltage Noise Spectral Density vs Frequency (RTI) Figure 22
Current Noise Spectral Density vs Frequency (RTI) Figure 23
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1 Figure 24
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000 Figure 25
0.1-Hz to 10-Hz RTI Current Noise Figure 26
Typical Distribution of Gain Error, G = 1 Figure 27
Typical Distribution of Gain Error, G = 10 Figure 28
Input Bias Current vs Common-Mode Voltage Figure 29
Gain Error vs Temperature, G = 1 Figure 30
Gain Error vs Temperature, G = 10 Figure 31
Supply Current vs Temperature Figure 32
Gain Nonlinearity, G = 1 Figure 33
Gain Nonlinearity, G = 10 Figure 34
Offset Voltage vs Negative Common-Mode Voltage Figure 35
Offset Voltage vs Positive Common-Mode Voltage Figure 36
Positive Output Voltage Swing vs Output Current Figure 37
Negative Output Voltage Swing vs Output Current Figure 38
Short-Circuit Current vs Temperature Figure 39
Large-Signal Frequency Response Figure 40
THD+N vs Frequency Figure 41
Overshoot vs Capacitive Loads Figure 42
Small-Signal Response, G = 1 Figure 43

INA821
Typical Characteristics: Table of Graphs (continued)

Table 1. Table of Graphs (continued)
DESCRIPTION FIGURE
Large-Signal Step Response Figure 47
Closed-Loop Output Impedance Figure 48
Differential-Mode EMI Rejection Ratio Figure 49
Common-Mode EMI Rejection Ratio Figure 50
Input Common-Mode Voltage vs Output Voltage, G = 1, VS = 5 V Figure 51
Input Common-Mode Voltage vs Output Voltage, G = 100, VS = 5 V Figure 52
Input Common-Mode Voltage vs Output Voltage, VS = ±5 V Figure 53
Input Common-Mode Voltage vs Output Voltage, VS = ±15 V Figure 54

INA821
7.7 Typical Characteristics

15 30
25
10 20
Amplifiers (%)
Amplifiers (%)
15
5 10
0 0
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Input Stage Offset Voltage (PV) D001
Input Stage Offset Voltage Drift (PV/qC) D002
N = 2667 Mean = 3.1 µV Std. Dev. = 8.1 µV N = 81 Mean = -0.03 µV/°C Std. Dev. = 0.09 µV/°C
Figure 1. Typical Distribution of Figure 2. Typical Distribution of

Input Stage Offset Voltage Input Stage Offset Voltage Drift
15 16
14
12
10
Amplifiers (%)
Amplifiers (%)
10
6
5
4
0 0
-200 -100 0 100 200 -5 -4 -3 -2 -1 0 1 2 3 4 5
Output Offset Voltage Drift (PV/qC) D004
N = 2667 Mean = 7.7 µV Std. Dev. = 50.7 µV N = 81 Mean = –1.09 µV/°C Std. Dev. = 0.94 µV/°C
Figure 3. Typical Distribution of Figure 4. Typical Distribution of

Output Stage Offset Voltage Output Stage Offset Voltage Drift
100 500
75 400
Input-Referred Offset Voltage (PV)
Input-Referred Offset Voltage (PV)
300
50
200
25 100
0 0
-25 -100
-200
-50
Mean -300 Mean
-75 +3V -400 +3V
-3V -3V
-100 -500
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (qC) D005
81 units 81 units
Figure 5. Input Stage Offset Voltage vs Temperature Figure 6. Output Stage Offset Voltage vs Temperature

INA821
Typical Characteristics (continued)

20 20
15 15
Amplifiers (%)
Amplifiers (%)
10 10
5 5
0 0
-300 -200 -100 0 100 200 300 -200 -150 -100 -50 0 50 100 150 200
Input Bias Current (pA) D007
Input Bias Current (pA) D008
N = 292 Mean = 45 pA Std. Dev. = 62 pA N = 292 Mean = 34 pA Std. Dev. = 52 pA
TA = 25°C TA = 90°C
Figure 7. Typical Distribution of Input Bias Current, Figure 8. Typical Distribution of Input Bias Current,
TA = 25°C TA = 90°C
25 1
Avg
0.8 3V
20 0.6 3V
Input Bias Current (nA)
0.4
Amplifiers (%)
15 0.2
0
10 -0.2
-0.4
5 -0.6
-0.8
0 -1
-300 -200 -100 0 100 200 300 -50 -30 -10 10 30 50 70 90 110 130 150
Input Offset Current (pA) D050
N = 94 Mean = –38.82 pA Std. Dev. = 47.24 pA N = 294 G=1
Figure 9. Typical Distribution of Input Offset Current Figure 10. Input Bias Current vs Temperature
0.5 25
0.4
0.3 20
Input Offset Current (nA)
0.2
Amplifiers (%)
0.1 15
0
-0.1 10
-0.2
-0.3 Avg 5
-0.4 3V
3V
-0.5 0
-50 -30 -10 10 30 50 70 90 110 130 150 -20 -16 -12 -8 -4 0 4 8 12 16 20
Common-Mode Rejection Ratio (PV/V) D011
N = 294 G=1 N = 294 Mean = 4.87 µV/V Std. Dev. = 4.14 µV/V
G=1
Figure 11. Input Offset Current vs Temperature Figure 12. Typical CMRR Distribution, G = 1

INA821

30 150
Common-Mode Rejection Ratio (dB)

25
125
20
Amplifiers (%)
15 100
10
Unit 1
75 Unit 2
5 Unit 3
Unit 4
Unit 5
0 50
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -50 -25 0 25 50 75 100 125 150
Common-Mode Rejection Ratio (PV/V) D012
N = 294 Mean = 0.51 µV/V Std. Dev. = 0.42 µV/V N=5 G=1
G = 10
Figure 13. Typical CMRR Distribution, G = 10 Figure 14. CMRR vs Temperature, G = 1

175 10 20
8 16
6 12
150
4 8
Output Voltage (V)

Input Current (mA)
2 4
125 0 0
-2 -4
Unit 1 -4 -8
100 Unit 2
Unit 3 -6 -12
Unit 4 -8 Input Current -16
Unit 5 Output Voltage
75 -10 -20
-50 -25 0 25 50 75 100 125 150 -50 -40 -30 -20 -10 0 10 20 30 40 50
Input Voltage (V) D015
N=5 G = 10 VS = ±18 V
Figure 15. CMRR vs Temperature, G = 10 Figure 16. Input Current vs Input Overvoltage
160 140
140 120
120
100
100
80
80
60
60
40
40 G=1 G=1
G = 10 G = 10
20 G = 100 20 G = 100
G = 1000 G = 1000
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M
Frequency (Hz) D016
Frequency (Hz) D017
Figure 17. CMRR vs Frequency (RTI) Figure 18. CMRR vs Frequency

(RTI, 1-kΩ source imbalance)

INA821

160 160
140 140
120 120
Negative Power Supply

Positive Power Supply
Rejection Ratio (dB)
Rejection Ratio (dB)

100 100
80 80
60 60
40 40
20 20
G=1 G=1
0 G = 10 0 G = 10
-20 G = 100 -20 G = 100
G = 1000 G = 1000
-40 -40
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency (Hz) D018
Frequency (Hz) D019
Figure 19. Positive PSRR vs Frequency (RTI) Figure 20. Negative PSRR vs Frequency (RTI)
80 1000
G=1
60 G = 10
G = 100
40 Spectral Density (nV/—Hz) G = 1000

Voltage Noise
100
Gain (dB)
20
-20
G=1
10
G = 10
-40 G = 100
G = 1000
-60
10 100 1k 10k 100k 1M 10M 100m 1 10 100 1k 10k 100k
Frequency (Hz) D020
Frequency (Hz) D021
Figure 21. Gain vs Frequency Figure 22. Voltage Noise Spectral Density vs Frequency
(RTI)
1k
Current Noise Spectral
Noise (0.5 PV/div)

Density (fA/—Hz)
100
10
100m 1 10 100 1k 10k Time (1 s/div)
Frequency (Hz) D022
D023
G=1
Figure 23. Current Noise Spectral Density vs Frequency Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1
(RTI)

INA821

Noise (0.5 pA/div)

Noise (20 nV/div)
Time (1 s/div) Time (1 s/div)

D024 D025
G = 1000 G=1
Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000 Figure 26. 0.1-Hz to 10-Hz RTI Current Noise
30 20
18
25
16
14
20
Amplifiers (%)
Amplifiers (%)
12
15 10
8
10
6
4
5
2
0 0
-250 -200 -150 -100 -50 0 50 100 150 200 250 -900 -600 -300 0 300 600 900
Gain Error (ppm) D026
N = 5412 Mean = 30 ppm Std. Dev. = 55 ppm N = 293 Mean = 152 ppm Std. Dev. = 291 ppm
G=1 G = 10
Figure 27. Typical Distribution of Gain Error, G = 1 Figure 28. Typical Distribution of Gain Error, G = 10
0.5 100
45qC
25qC 80
0.3 125qC
Input Bias Current (nA)
60
Gain Error (ppm)
0.1 40
20
-0.1
0
-0.3
-20
-0.5 -40
-15 -12 -9 -6 -3 0 3 6 9 12 15 -50 -30 -10 10 30 50 70 90 110 130 150
Common-Mode Voltage (V) D028
VS = ±15 V Average of 294 units G=1
Figure 29. Input Bias Current vs Common-Mode Voltage Figure 30. Gain Error vs Temperature, G = 1

INA821

1500 0.9
1250 0.84
1000
0.78
750
0.72
Gain Error (ppm)
500
250 0.66
IQ (mA)
0 0.6
-250 0.54
-500
0.48
-750
0.42
-1000
0.36 VS = r 15 V
-1250 VS = r 2.25 V
-1500 0.3
-50 -25 0 25 50 75 100 125 150 -50 -30 -10 10 30 50 70 90 110 130 150
Average of 294 units G = 10
Figure 31. Gain Error vs Temperature, G = 10 Figure 32. Supply Current vs Temperature
1 10
8
0.8
6
0.6 4
0.4 2
Nonlinearity (ppm)
Nonlinearity (ppm)
0.2 0
-2
0
-4
-0.2 -6
-0.4 -8
-10
-0.6
-12
-0.8 -14
-1 -16
-10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10
Output Voltage (V) D032
Output Voltage (V) D033
G=1 G = 10
Figure 33. Gain Nonlinearity, G = 1 Figure 34. Gain Nonlinearity, G = 10

175 150
40qC 40qC
150 25qC 125 25qC
125 85qC 85qC
125qC 100 125qC
100
Offset Voltage (PV)
Offset Voltage (PV)
75 75
50 50
25 25
0
0
-25
-50 -25
-75 -50
-15 -14.6 -14.2 -13.8 -13.4 -13 -12.6 -12.2 12 12.4 12.8 13.2 13.6 14 14.4 14.8
Input Common-Mode Voltage (V) D034
Input Common-Mode Voltage (V) D035
Figure 35. Offset Voltage vs Negative Common-Mode Figure 36. Offset Voltage vs Positive Common-Mode
Voltage Voltage

INA821

15 -14
± qC
14.9 -14.1 25qC
14.8 -14.2 85qC
125qC
14.7
Output Voltage (V)
-14.3
Output Voltage (V)

14.6 -14.4
14.5 -14.5
14.4 -14.6
14.3 -14.7
± qC
14.2 25qC -14.8
14.1 85qC -14.9
125qC
14 -15
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Output Current (mA) D036
Output Current (mA) D037
Figure 37. Positive Output Voltage Swing vs Output Current Figure 38. Negative Output Voltage Swing vs Output Current
40 20
Vs = r15 V
30 18 Vs = r5 V
20 16
Short-Circuit Current (mA)
Output Amplitude (Vp)
10 14
0 12
-10 10
-20 8
-30 6
-40 4
-50 ISC, Source 2
ISC, Sink
-60 0
-50 -30 -10 10 30 50 70 90 110 130 150 100 1k 10k 100k 1M 10M
Frequency (Hz) D039
Figure 39. Short-Circuit Current vs Temperature Figure 40. Large-Signal Frequency Response
1 -40 50
G=1 Positive Overshoot
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
G = 10 45 Negative Overshoot
G = 100 40
35
0.1 -60
Overshoot (%)
30
25
20
0.01 -80
15
10
5
0.001 -100 0
10 100 1k 10k 100k 1 10 100 1000
Frequency (Hz) D040
Capacitive Load (pF) D041
500-kHz measurement bandwidth
1-VRMS output voltage 100-kΩ load
Figure 41. THD+N vs Frequency Figure 42. Overshoot vs Capacitive Loads

INA821

75 75
50 50
Output Amplitude (mV)

25 25
0 0
-25 -25
-50 -50
-75 -75
-5 -2.5 0 2.5 5 7.5 10 12.5 15 -5 -2.5 0 2.5 5 7.5 10 12.5 15
Time (µs) D042
Time (µs) D043
G=1 RL = 10 kΩ CL = 100 pF G = 10 RL = 10 kΩ CL = 100 pF
Figure 43. Small-Signal Response Figure 44. Small-Signal Response

75 75
50 50

25 25
0 0
-25 -25
-50 -50
-75 -75
-5 -2.5 0 2.5 5 7.5 10 12.5 15 -25 0 25 50 75
Time (µs) D044
Time (µs) D045
G = 100 RL = 10 kΩ CL = 100 pF G = 1000 RL = 10 kΩ CL = 100 pF
Figure 45. Small-Signal Response Figure 46. Small-Signal Response
Output
Input
100
Output Impedence (:)
Amplitude (2 V/div)
10
0.1
Time (10 µs/div) 1 10 100 1k 10k 100k 1M 10M

D046
Frequency (Hz) D047
Figure 47. Large-Signal Step Response Figure 48. Closed-Loop Output Impedance

INA821

120 140
100 120
100
80
EMIRR (dB)
EMIRR (dB)
80
60
60
40
40
20 20
0 0
10M 100M 1G 10G 10M 100M 1G 10G
Frequency (Hz) D048
Frequency (Hz) D049
Figure 49. Differential-Mode EMI Rejection Ratio Figure 50. Common-Mode EMI Rejection Ratio
5 5
VREF = 0 V VREF = 0 V
VREF = 2.5 V VREF = 2.5 V
Common-Mode Voltage (V)

4 4
3 3
2 2
1 1
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Output Voltage (V) C006 Output Voltage (V) C006
VS = 5 V G=1 VS = 5 V G = 100
Figure 51. Input Common-Mode Voltage vs Output Voltage Figure 52. Input Common-Mode Voltage vs Output Voltage
5 15
4
10
3
2 5
1 0
0
-5
-1
-2 -10
-3
G=1 -15 G=1
-4
G = 100 G = 100
-5 -20
±6 ±4 ±2 0 2 4 6 ±20 ±10 0 10 20
VS = ±5 V VREF = 0 V VS = ±15 V VREF = 0 V

INA821
8 Detailed Description
8.1 Overview
The INA821 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how
the differential input voltage is buffered by Q1 and Q2 and is forced across RG, which causes a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produces
output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
8.2 Functional Block Diagram
+VS
RB VB RB
IB Cancellation IB Cancellation -VS +VS
40 k
40 k
±
+
±
A1 A2
A3 OUT
+
40 k
REF
40 k
+VS +VS
-VS +VS
Q1 Q2
Super- Super-
-IN +IN
NPN NPN
Overvoltage +VS +VS Overvoltage
Protection Protection
R1 R2
25 k RG 25 k
-VS (External) -VS
RG RG
-VS -VS
Copyright © 2017, Texas Instruments Incorporated

INA821
8.3 Feature Description

8.3.1 Setting the Gain
Figure 55 shows that the gain of the INA821 is set by a single external resistor (RG) connected between the RG
pins (pins 1 and 8).
V+
+VS
Overvoltage
-IN + 10 k 10 k
Protection
±
RG
49.4 k: 24.7 k ± OUT

G 1 RG
RG 24.7 k +
RG
VO G V IN V IN VREF
±
+IN Overvoltage + REF

10 k 10 k
Protection
-VS
V-
Figure 55. Simplified Diagram of the INA821 With Gain and Output Equations
The value of RG is selected according to:

49.4 k:
G 1
RG (1)
Table 2 lists several commonly used gains and resistor values. The 49.4-kΩ term in Equation 1 is a result of the
sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate
absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy
and drift specifications of the INA821. As shown in Figure 55 and explained in more details in the Layout section,
make sure to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, that are
placed as close to the device as possible.
Table 2. Commonly-Used Gains and Resistor Values

DESIRED GAIN RG (Ω) NEAREST 1% RG (Ω)
1 NC NC
2 49.4 k 49.9 k
5 12.35 k 12.4 k
10 5.489 k 5.49 k
20 2.600 k 2.61 k
50 1.008 k 1k
100 499 499
200 248 249
500 99 100
1000 49.4 49.9

INA821
8.3.1.1 Gain Drift

The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of
RG to gain accuracy and drift is determined from Equation 1.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA821 uses G = 1 without RG connected. In
this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 10-kΩ
resistors in the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual
drift of the 24.7-kΩ resistors in the feedback of A1 and A2 relative to the drift of the external gain resistor (RG.)
The low temperature coefficient of the internal feedback resistors significantly improves the overall temperature
stability of applications using gains greater than 1 V/V over alternate options.
Low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the
wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of
approximately 100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at
RG connections. Careful matching of any parasitics on the RG pins maintains optimal CMRR over frequency; see
Figure 17.
8.3.2 EMI Rejection

Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad
frequency spectrum extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to
quantify the ability of the INA821 to reject EMI. The offset resulting from an input EMI signal is calculated using
Equation 2:
§ EMIRR (dB) ·
§ VRF _ PEAK 2 · ¨ ¸
'VOS ¨ ¸ ˜ 10 © 20 ¹
¨ 100 mVP ¸
© ¹
where
• VRF_PEAK is the peak amplitude of the input EMI signal. (2)
Figure 56 and Figure 57 show the INA821 EMIRR graph for differential and common-mode EMI rejection across
this frequency range. Table 3 lists the EMIRR values for the INA821 at frequencies commonly encountered in
real-world applications. Applications listed in Table 3 are centered on or operated near the particular frequency
shown. Depending on the end-system requirements, additional EMI filters may be required near the signal inputs
of the system. Incorporating known good practices, such as using short traces, low-pass filters, and damping
resistors combined with parallel and shielded signal routing, may be required.
140 120
120 100
100
80
EMIRR (dB)
EMIRR (dB)
80
60
60
40
40
20 20
0 0
10M 100M 1G 10G 10M 100M 1G 10G
Frequency (Hz) D049
Frequency (Hz) D048
Figure 56. Common-Mode EMIRR Testing Figure 57. Differential-Mode EMIRR Testing

INA821
Table 3. INA821 EMIRR for Frequencies of Interest

DIFFERENTIAL COMMON-MODE
FREQUENCY APPLICATION OR ALLOCATION
EMIRR EMIRR
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-frequency (UHF)
400 MHz 60 dB 88 dB
applications
Global system for mobile communications (GSM) applications, radio communication, navigation,
900 MHz 58 dB 60 dB
GPS (up to 1.6 GHz), GSM, aeronautical mobile, UHF applications
GSM applications, mobile personal communications, broadband, satellite,
1.8 GHz 66 dB 89 dB
L-band (1 GHz to 2 GHz)
®
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications, industrial, scientific
2.4 GHz 73 dB 98 dB
and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 99 dB 111 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and
5 GHz 83 dB 91 dB
satellite operation, C-band (4 GHz to 8 GHz)
8.3.3 Input Common-Mode Range

The linear input voltage range of the INA821 input circuitry extends within 2 V of power supplies and maintains
excellent common-mode rejection throughout this range. The common-mode range for the most common
operating conditions are shown in Figure 58 to Figure 61. The common-mode range for other operating
conditions is best calculated using the Common-Mode Input Range Calculator for Instrumentation Amplifiers.
5 5
VREF = 0 V VREF = 0 V
VREF = 2.5 V VREF = 2.5 V
4 4
3 3
2 2
1 1
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
VS = 5 V G=1 VS = 5 V G = 100
5 15
4
10
3
2 5
1 0
0
-5
-1
-2 -10
-3
G=1 -15 G=1
-4
G = 100 G = 100
-5 -20
±6 ±4 ±2 0 2 4 6 ±20 ±10 0 10 20
VS = ±5 V VREF = 0 V VS = ±15 V VREF = 0 V

INA821
8.3.4 Input Protection

The inputs of the INA821 device are individually protected for voltages up to ±40 V. For example, a condition of
–40 V on one input and +40 V on the other input does not cause damage. Internal circuitry on each input
provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry
limits the input current to a value of approximately 8 mA.
+V
ZD1
+VS
IN Overvoltage
Input Voltage +
Protection
Source ± Input Transistor
-VS
ZD2
-V
Figure 62. Input Current Path During an Overvoltage Condition
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
as shown in Figure 62. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2
in Figure 62) must be placed on the power supplies to provide a current pathway to ground. Figure 63 shows the
input current for input voltages from –40 V to +40 V when the INA821 is powered by ±15-V supplies.
10 20
8 16
6 12
4 8
Output Voltage (V)
Input Current (mA)
2 4
0 0
-2 -4
-4 -8
-6 -12
-8 Input Current -16
Output Voltage
-10 -20
-50 -40 -30 -20 -10 0 10 20 30 40 50
Input Voltage (V) D015
Figure 63. Input Current vs Input Overvoltage

INA821
8.3.5 Operating Voltage

The INA821 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).
CAUTION
Supply voltages higher than 40 V (±20 V) can permanently damage the device.
Parameters that vary over supply voltage or temperature are shown in the Typical
Characteristics section of this data sheet.
8.3.6 Error Sources

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, minimize these errors by
choosing high-precision components, such as the INA821, that have improved specifications in critical areas that
impact the precision of the overall system. Figure 64 shows an example application.
+15 V
C2
RS+
1k
+VS
RG
VDIFF = VOUT / G 5.49 k INA VOUT = 1 V
REF
RG ±VS
RS±
VCM = 10 V 0.99 k
C1
±15 V
Figure 64. Example Application With G = 10 V/V and a 1-V Output Voltage
Resistor-adjustable devices (such as the INA821) show the lowest gain error in G = 1 because of the inherently
well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =
10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the
resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high
gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset
drift.
The INA821 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor).
Table 5 summarizes the major error sources in common INA applications and compares the three cases of G = 1
(no external resistor) and G = 10 (5.49-kΩ external resistor) and G = 100 (499-Ω external resistor). All
calculations are assuming an output voltage of VOUT = 1 V. Thus, the input signal VDIFF (given by VDIFF= VOUT/G)
exhibits smaller and smaller amplitudes with increasing gain G. In this example, VDIFF = 1 mV at G = 1000. All
calculations refer the error to the input for easy comparison and system evaluation. As Table 5 shows, errors
generated by the input stage (such as input offset voltage) are more dominant at higher gain, while the effects of
output stage are suppressed because they are divided by the gain when referring them back to the input. the
gain error and gain drift error are much more significant for gains greater than 1 because of the contribution of
the resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. In most
applications, static errors (absolute accuracy errors) can readily be removed during calibration in production,
while the drift errors are the key factors limiting overall system performance.

INA821
Table 4. System Specifications for Error Calculation

QUANTITY VALUE UNIT
VOUT 1 V
VCM 10 V
VS 1 V
RS+ 1000 Ω
RS– 999 Ω
RG tolerance 0.01 %
RG drift 10 ppm/°C
Temperature range upper limit 105 °C
Table 5. Error Calculation

INA821 VALUES
ERROR SOURCE ERROR CALCULATION G=1 G = 100 G = 1000

SPECIFICATION UNIT ERROR ERROR ERROR
(ppm) (ppm) (ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage VOSI / VDIFF 35 µV 35 350 3500
Output offset voltage VOSO / (G × VDIFF) 300 µV 350 350 350
Input offset current IOS × maximum (RS+, RS–) / VDIFF 0.5 nA 1 5 50
92 (G = 1),
CMRR (min) VCM / (10CMRR/20 × VDIFF) 112 (G = 10), dB 251 251 251
132 (G = 100)
110 (G = 1),
PSRR (min) (VCC – VS)/ (10PSRR/20 × VDIFF) 114 (G = 10), dB 3 20 32
130 (G = 100)
0.02 (G = 1),
Gain error from INA (max) GE(%) × 104 % 200 1500 1500
0.15 (G = 10, 100)
Gain error from external resistor RG (max) GE(%) × 104 0.01 % 100 100 100
Total absolute accuracy error (ppm) at 25°C,
sum of all errors — — 940 2576 5738
worst case
Total absolute accuracy error (ppm) at 25°C,
rms sum of all errors — — 487 1603 3834
average
DRIFT TO 105°C
5 (G = 1),
Gain drift from INA (max) GTC × (TA – 25) ppm/°C 400 2800 2800
35 (G = 10, 100)
Gain drift from external resistor RG (max) GTC × (TA – 25) 10 ppm/°C 800 800 800
Input offset voltage drift (max) (VOSI_TC / VDIFF) × (TA – 25) 0.4 µV/°C 32 320 3200
Output offset voltage drift [VOSO_TC / ( G × VDIFF)] × (TA – 25) 5 µV/°C 400 400 400
IOS_TC × maximum (RS+, RS–) ×
Offset current drift 20 pA/°C 2 16 160
(TA – 25) / VDIFF
Total drift error to 105°C (ppm), worst case sum of all errors — — 1634 4336 7360
Total drift error to 105°C (ppm), typical rms sum of all errors — — 980 2957 4348
RESOLUTION
10 (G = 1, 10),
Gain nonlinearity ppm of FS 10 10 15
15 (G = 100)
2
eNO 6
BW ´ (eNI2 + eNI = 7,
Voltage noise (at 1 kHz) ´ µVPP 1335 886 3566
G VDIFF eNO = 65
IN × maximum (RS+, RS–) × √BW /

Current noise (at 1kHz) 0.13 pA/√Hz 0.4 2 11
VDIFF
Total resolution error (ppm), worst case sum of all errors — — 1345 896 3581
Total resolution error (ppm), typical rms sum of all errors — — 1335 886 3566
TOTAL ERROR
Total error (ppm), worst case sum of all errors — — 3919 7808 16724
Total error (ppm), typical rms sum of all errors — — 1726 3478 6806

INA821
8.4 Device Functional Modes

The INA821 has a single functional mode and is operational when the power supply voltage is greater than 4.5 V
(±2.25 V). The maximum power-supply voltage for the INA821 is 36 V (±18 V).
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

9.1.1 Reference Pin
The output voltage of the INA821 is developed with respect to the voltage on the reference pin (REF.) Often in
dual-supply operation, REF (pin 6) connects to the low-impedance system ground. In single-supply operation,
offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply
environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the
output so that the INA821 drives a single-supply analog-to-digital converter (ADC).
The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 65, any
resistance at the reference pin ( RREF in Figure 65) is in series with one of the internal 10-kΩ resistors.
V+
+VS
Over-
-IN Voltage + 10 k 10 k
Protection
±
RG
24.7 k ±
RG OUT
24.7 k +
RG
± REF
Over-
+IN Voltage + 10 k 10 k RREF
Protection
-VS
V-
Figure 65. Parasitic Resistance Shown at the Reference Pin

INA821
Application Information (continued)

The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal
difference amplifier that results in a degraded common-mode rejection ratio (CMRR). Figure 66 shows the
degradation in CMRR of the INA821 as a result of the increased resistance at the reference pin. For the best
performance, keep the source impedance to the REF pin (RREF) less than 5 Ω.
120

100
80
60
0Ω
40
5Ω
10 Ω
20
15 Ω
20 Ω
0
10 100 1k 10k
Frequency (Hz)
Figure 66. The Effect of Increasing Resistance at the Reference Pin
Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference
pin. However, if a resistor voltage divider generates a reference voltage, buffer the divider by an op amp, as
shown in Figure 67, to avoid CMRR degradation.
5V
+VS
+IN
RG
RG INA821 OUT
REF
RG
±VS
±IN 5V 5V
100 k
OPA191 +
± 1 F
100 k
Figure 67. Use an Op Amp to Buffer Reference Voltages

INA821
Application Information (continued)

9.1.2 Input Bias Current Return Path
The input impedance of the INA821 is extremely high (approximately 100 GΩ.) However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input
impedance means that this input bias current changes little with varying input voltage.
For proper operation, Input circuitry must provide a path for this input bias current. Figure 68 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA821 and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path connects to one input (as shown in the thermocouple example in Figure 68).
With a higher source impedance, using two equal resistors provides a balanced input with possible advantages
of a lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone, TI Device
and So Forth
47 kW 47 kW
Thermocouple TI Device
10 kW
TI Device
Center tap provides

bias current return.
Figure 68. Providing an Input Common-Mode Current Path

INA821
9.2 Typical Application

Figure 69 shows a three-pin programmable-logic controller (PLC) design for the INA821. This PLC reference
design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to
4.8 V). Typically, PLCs have these input and output ranges.
±10 V
15 V
REF5025
R1 = 100 NŸ
VOUT VIN
1 F GND NR 1 F 1 F
15 V
R2 = 4.17 NŸ
±20 mA
-IN +VS
RG
REF
R3 = RG = 10.4 NŸ INA821 OUT VOUT 2.5 V ± 2.3 V
20 Ÿ
RG
+IN -VS
-15 V
Figure 69. PLC Input (±10 V, 4 mA to 20 mA)
9.2.1 Design Requirements

For this application, the design requirements are as follows:
• 4-mA to 20-mA input with less than 20-Ω burden
• ±20-mA input with less than 20-Ω burden
• ±10-V input with impedance of approximately 100 kΩ
• Maximum 4-mA to 20-mA or ±20 mA burden voltage equal to ±0.4 V
• Output range within 0 V to 5 V
9.2.2 Detailed Design Procedure

There are two modes of operation for the circuit shown in Figure 69: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, Equation 3 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
• G represents the gain of the instrumentation amplifier.
• VD represents the differential voltage at the INA821 inputs.
• VREF is the voltage at the INA821 REF pin.
• IIN is the input current. (3)
Equation 4 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN ´ ´ G + VREF
R 1 + R2
where
• VIN is the input voltage (4)

INA821
Typical Application (continued)

R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. The R1
value is 100 kΩ because increasing the R1 value also increases noise. The value of R3 must be extremely small
compared to R1 and R2. The value of R3 is 20 Ω because that resistance value is smaller than R1 and yields an
input voltage of ±400 mV when operating in current mode (±20 mA).
Use Equation 5 to calculate R2 if VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2 R ´ VD
VD = VIN ´ ® R2 = 1 = 4.167 kW
R 1 + R2 VIN - VD (5)
The value obtained from Equation 5 is not a standard 0.1% value, so 4.17 kΩ is selected. R1 and R2 use 0.1%
tolerance resistors to minimize error.
Use Equation 6 to calculate the gain of the instrumentation amplifier.
V - VREF 4.8 V - 2.5 V V
G = OUT = = 5.75 V
VD 400 mV (6)
Equation 7 calculates the gain-setting resistor value using the INA821 gain equation (Equation 1).
49.4 k: 49.4 k:
RG 10.4 k:
G 1 5.75 1 (7)
Use a standard 0.1% resistor value of 10.5 kΩ for this design.
9.2.3 Application Curves

Figure 70 and Figure 71 show typical characteristic curves for the circuit in Figure 69.
C001
5
5
4
4
Output Voltage (V)
Output Voltage (V)
3
3
2
2
1
1
0
-10 -5 0 5 10 0
-20 -10 0 10 20
Input Voltage (V)
Input Current (mA) C001
Figure 70. PLC Output Voltage vs Input Voltage

Figure 71. PLC Output Voltage vs Input Current

INA821
9.3 Other Application Examples

9.3.1 Resistance Temperature Detector Interface
Figure 72 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit
incorporates analog linearization and has an output voltage range from 0 V to 5 V. The linearization technique
employed is described in Analog linearization of resistance temperature detectors analog application journal.
Series and parallel combinations of standard 1% resistor values are used to achieve less than 0.02°C of error
over a 200°C temperature span.
15 V
REF5050
VOUT VIN
1 F
1 F
1 F
GND NR
4.99
4.99 k
k
+VS
-IN
RG VOUT
100 100 0 V at 0°C
801 INA821 OUT
REF
k 5 V at 200°C
RG 25 mV/°C
-VS
+IN
Pt100 RTD
100
-15 V
105 k 1.18 k
Figure 72. A 3-Wire Interface for RTDs With Analog Linearization
5 0.018
4.5 0.016
4 0.014
Output Voltage (V)
3.5
0.012
Error (ƒC)
3
0.01
2.5
0.008
2
0.006
1.5
1 0.004
0.5 0.002
0 0
0 50 100 150 200 0 50 100 150 200
Temperature (°C) Temperature (°C) C001
Figure 73. Transfer Function of 3-Wire RTD Interface Figure 74. Temperature Error Over Full Temperature
Range

INA821
10 Power Supply Recommendations

The nominal performance of the INA821 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and
reference voltage are shown in the Typical Characteristics section.
11 Layout
11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use
good PCB layout practices, including:
• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals. Even slight mismatch in parasitic capacitance at the gain
setting pins can degrade CMRR over frequency. For example, in applications that implement gain switching
using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch
capacitance is as small as possible and most importantly so that capacitance mismatch between the RG pins
is minimized.
• Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 75, keep RG close to
the pins to minimize parasitic capacitance.
• Keep the traces as short as possible.
• Connect exposed thermal pad to negative supply –V.

INA821
11.2 Layout Example

+V
C2
R2
+VS
+IN
RG
R3 INA821 OUT
REF
RG
±VS
-IN
R1
C1
-V
Use ground pours for +V

shielding the input
signal pairs Place bypass
GND capacitors as close to
IC as possible
C2
R1
±IN
1 ±IN +VS 8
2 RG OUT 7 OUT
R3
3 RG REF 6
4 +IN -VS 5
Low-impedance
+IN
connection for
reference terminal
R2
GND
C1
REF
-V
Figure 75. Example Schematic and Associated PCB Layout

INA821
12 Device and Documentation Support
12.1 Device Support

12.1.1 Development Support
• SPICE-based analog simulation program — TINA-TI software folder
• Common-Mode Input Range Calculator for Instrumentation Amplifiers
12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPAx191 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset
Voltage, Low Input Bias Current Op Amp data sheet
12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 22-Oct-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
INA821ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821
& no Sb/Br)
INA821IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1X4Q
& no Sb/Br)
INA821IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1X4Q
& no Sb/Br)
INA821IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821
& no Sb/Br)
INA821IDRGR ACTIVE SON DRG 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821
& no Sb/Br)
INA821IDRGT ACTIVE SON DRG 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA821IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA821IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
INA821IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
INA821IDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
INA821IDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA821IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
INA821IDGKT VSSOP DGK 8 250 366.0 364.0 50.0
INA821IDR SOIC D 8 2500 853.0 449.0 35.0
INA821IDRGR SON DRG 8 3000 367.0 367.0 35.0
INA821IDRGT SON DRG 8 250 210.0 185.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008B SCALE 4.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
3.1
PIN 1 INDEX AREA 2.9
0.8
0.7
SEATING PLANE DIMENSION A

0.05 OPTION 01 (0.1)
0.00 0.05 C
OPTION 02 (0.2)
(DIM A) TYP
EXPOSED 1.45 0.1 OPT 01 SHOWN
THERMAL PAD
4
5
2X
1.5 2.4 0.1
8
1
6X 0.5
0.3
8X
0.2
PIN 1 ID 0.6
8X 0.1 C A B
(OPTIONAL) 0.4
0.08 C
4218886/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008B WSON - 0.8 mm max height
(1.45)
8X (0.7) SYMM
1 8
8X (0.25)
(2.4)
6X (0.5) (0.95)
4
5
(R0.05) TYP
(0.475)
( 0.2) VIA
TYP (2.7)
LAND PATTERN EXAMPLE

SCALE:20X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218886/A 01/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008B WSON - 0.8 mm max height
SYMM METAL
8X (0.7)
TYP
8X (0.25) 1 8
(0.635)
SYMM
6X (0.5)
4 (1.07)
5
(R0.05) TYP
(1.47)
(2.7)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218886/A 01/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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INA821 35-µV Offset, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier

• Process analytics (pH, gas, concentration, force

Changes from Revision C (July 2019) to Revision D Page

Changes from Revision B (May 2019) to Revision C Page

Changes from Revision A (December 2018) to Revision B Page

Changes from Original (August 2018) to Revision A Page

• First release of production-data data sheet ........................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: INA821

5 Device Comparison Table

DEVICE DESCRIPTION GAIN EQUATION RG PINS AT PIN

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Pin Configuration and Functions

D and DGK Packages DRG Package

4 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: INA821

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 5

7.5 Electrical Characteristics

Power-supply rejection G = 10, RTI 114 130

Input stage voltage f = 1 kHz, G = 100, RS = 0 Ω 7 nV/√Hz

Output stage voltage f = 1 kHz, RS = 0 Ω 65 nV/√Hz

(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

Product Folder Links: INA821

Electrical Characteristics (continued)

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 7

7.6 Typical Characteristics: Table of Graphs

8 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: INA821

Typical Characteristics: Table of Graphs (continued)

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 9

7.7 Typical Characteristics

Figure 1. Typical Distribution of Figure 2. Typical Distribution of

Figure 3. Typical Distribution of Figure 4. Typical Distribution of

Input-Referred Offset Voltage (PV)

10 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: INA821

Typical Characteristics (continued)

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 11

Typical Characteristics (continued)

Common-Mode Rejection Ratio (dB)

Figure 13. Typical CMRR Distribution, G = 10 Figure 14. CMRR vs Temperature, G = 1

Output Voltage (V)

Common-Mode Rejection Ratio (dB)

Figure 17. CMRR vs Frequency (RTI) Figure 18. CMRR vs Frequency

12 Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

Product Folder Links: INA821

Typical Characteristics (continued)

Negative Power Supply

Rejection Ratio (dB)

40 Spectral Density (nV/—Hz) G = 1000

Noise (0.5 PV/div)

Copyright © 2018–2020, Texas Instruments Incorporated Submit Documentation Feedback 13

Typical Characteristics (continued)

Noise (0.5 pA/div)