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    Asic DDR Phy

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    lmlululu
    Combination of Northwest Logic's Memory Controller Cores and ASIC DDR PHY is designed for use in ASICs requiring high memory throughput, high clock rates and full programmability. Support for a broad range of programmable features including timing, termination, drive strengths, etc.

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    Asic DDR Phy

    Uploaded by

    lmlululu
    369 views1 page
    Combination of Northwest Logic's Memory Controller Cores and ASIC DDR PHY is designed for use in ASICs requiring high memory throughput, high clock rates and full programmability. Support for a broad range of programmable features including timing, termination, drive strengths, etc.

    Original Title

    ASIC_DDR_PHY

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    © Attribution Non-Commercial (BY-NC)

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    Combination of Northwest Logic's Memory Controller Cores and ASIC DDR PHY is designed for use in ASICs requiring high memory throughput, high clock rates and full programmability. Support for a broad range of programmable features including timing, termination, drive strengths, etc.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    369 views1 page

    Asic DDR Phy

    Uploaded by

    lmlululu
    Combination of Northwest Logic's Memory Controller Cores and ASIC DDR PHY is designed for use in ASICs requiring high memory throughput, high clock rates and full programmability. Support for a broad range of programmable features including timing, termination, drive strengths, etc.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    ASIC DDR PHY

    Product Highlights Block Diagram


    • Silicon-proven DDR PHY for use in ASIC DDR PHY
    ASICs
    Calibration Controls
    • Supports DDR3, DDR2, DDR, Mo- Calibration Controls I/O Calibration
    bile DDR, RLDRAM II operation
    • Uses robust windowing data cap- Write Data
    Write Mask DM
    ture method Write Control
    Write Data Path

    • Uses proven off-the-shelf DDR I/O


    DLL
    and DLL I/O
    Read Data Cells DQ
    • Supports Byte and Nibble DQS Read Control
    Read Capture

    • Supports a broad range of pro-


    grammable features including Data Loopback Datapath DQS
    timing, termination, drive Loopback

    strengths, etc.
    • Supports DFT and JTAG boundary Addr/Ctrl
    Address / Control Alignment
    scan
    I/O Address / Control
    • Supports comprehensive loopback Cells
    Addr/Ctrl Loopback Addr / Ctrl
    testing via add-on BIST Core Loopback

    • Provided as a soft core with tim-


    ing constraints enabling optimiza-
    tion for a target process and pin- Clock Forwarding

    out I/O Clocks


    Cells
    Clock Loopback Clock
    • Customization and Integration Loopback
    services available Configuration Controls

    CLK
    CLK_M90
    RESETN

    Product Overview
    The combination of Northwest Logic’s Memory Controller Cores The combination of the Memory Controller Core and DDR PHY
    and ASIC DDR PHY is designed for use in ASICs requiring high can be fully tested using Northwest Logic’s Memory Test Core
    memory throughput, high clock rates and full programmability. and Data Analyzer Core. The Memory Test Core provides a
    complete memory test using random and directed reads and
    Versions of the ASIC DDR PHY are available which support writes. The Mem Test Analyzer Core provides access to the
    DDR3 1060, DDR2 1066, DDR 800, Mobile DDR 400, RLDRAM II actual and expected memory test results for analysis.
    1066 Mbit/s/pin operation. Multi-mode versions are also
    available. The DDR PHY is delivered as a soft core with timing con-
    straints. This enables the DDR PHY to be optimized for a tar-
    get process and pinout.
    To ensure robust operation the DDR PHY uses a windowing data
    capture method, uses proven off-the-shelf DDR I/O and DLL, Northwest Logic can provides DDR PHY related services includ-
    and supports ASIC-side ODT and calibrated output impedance. ing DDR I/O and DLL replacement, process porting and DDR
    PHY hardening. Contact Northwest Logic for a quote.
    The DDR PHY is specifically designed for flexibility. This in-
    cludes a broad range of programmable features including vari-
    ous timing parameters, termination settings and drive
    Product Deliverables:
    strengths.
    • Core (Netlist or Source Code)
    The DDR PHY can be put into loopback for complete, at-speed • Timing constraints
    production test. This test is orchestrated by the BIST Core in
    • Comprehensive Verification Suite (Source Code)
    conjunction with the Memory Controller Core. The DDR PHY
    also supports DFT scan and JTAG boundary scan. • Complete Documentation
    • Expert Technical Support & Maintenance Updates

    Copyright 2011 Northwest Logic 24 Northwest Logic Proprietary

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