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IP & SoC Functional Verification Methodology

Using UVM

LAB2

Test Sequences & Coverage

Barriga Ponce de Leon Ricardo

GUO Ran
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Objectives:
This lab goes through the concept of sequences.
• Understand the concept of UVM sequences
• Implement directed test sequences
• Implement random test sequences

Introduction:
The design under test (DUT) is a UART 16550 from opencores.org.

The goal of this design is to perform serial transfers on the Tx line and receive Rx
transfers from the Rx line, given registers programmable thru a APB interface.
The testbench includes a APB Verification IP which main driver class is defined and
implemented in the following two files:
- ambersoc\aedvices\vip\APB\src\sv\APB_master_driver.svh (declaration)
- ambersoc\aedvices\vip\APB\src\sv\APB_master_driver.sv (implementation)
The goal of this lab is to implement test sequences to exercise the different
functionalities of the UART.

Work in the session:

Part 1 - Sequences
1. Implement a random init sequence
✦ Create a new class “lab4_uart_init_seq” based on the above template 


Add random parameters for each of the char length, parity, etc.

From the existing lab4_test_sequence, cut and paste the init part doing the
register accesses (between the comments “UART Init start” and “Transmit
Data”) to the newly created lab4_uart_init_seq class.


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Modify the copied register values accordingly using the random

parameters.
Add a constraint to force the parity to be set to even when the width is set
to 8

✦ In “lab4_test_sequence”
Instantiate the new init sequence

We use this phase to instantiate it.

Call the init sequence `uvm_do(init_seq)

And we use the `uvm_do function to run this instance.

✦ The result:
Here is the waveform we generated:

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In order to see more details, we right click the uvn_test_top and select
uvm_details. Then we add wave in this waveform diagram. We can see the
information of the register as the picture below.

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2. More Random Testing

✦ Create a sequence A
Performs a random number (between 10 and 100) of write to the transmit 

buffer of random data.
We use 2 rand variables to generate random number, which are
random_data and data_tx. In order to make these numbers between 10 and
100，we add a constraint to limit the range of these values.

✦ Instantiate the test sequence

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✦ Use uvm_do to call the newly created test sequence 


✦ The result:
Here is the waveform we generated:


✦ Create a sequence B

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In this sequence, we want to write to the transmit buffer of incremental data

(start with a random number, then increment), so we can just modify the class
my_seq_A by adding a loop in task which realise the incrementation. Our code
is as the picture below.



Same with before, we instantiate the test sequence and use uvm_do to call the
instance created. Then we test the sequence B, the waveform is as the picture
below. In order to see more details of the data, In order to see more details, we
right click the uvn_test_top and select uvm_details. Then we add wave of
monitor in this waveform diagram.
We can find in this picture, in tx_byte, the data increase one by one.

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✦ Create a sequence C
We use this sequence to select randomly one of the above two random
sequences A or B. As we can see in code, we set up the sequence C with only 8
bit char width.



Then, it will randomly select the sequence A and sequenceB when we simulate
this program. In our code, the probability of choosing A is as great as choosing
B.
Here is our simulate result of sequence C (it selected sequence B ).

When we simulate agin, it may select sequence A which is random.

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✦ Create a test sequence which randomly selects one of the above sequences
( A, B , C , init ) in a loop of 10 to 20 subsequences. 

We add a rand case in ab_on_seq_test_sequence to randomly selects one of
the above sequences, and for init_seq, it perform with only 8 bit char width. To
make it repeat 10 to 20 times, we use a variable which called count, we use a
constraint to limite it enter 10 to 20.

✦ Then we simulate this test, the result is as the picture below.

Exercice
✦ In one of the previous random sequences, add a “delay” random variables that
take a random value between 1 and 20. 

We add a “delay” variable in the sequence C, with a constraint to limit it
between 1 and 20.

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Then we do the simulation, here is our result:

In this picture, we can find a variable called PENABLE_i which near the
PCLK_i, the variation of PENABLE_i present the random value of “delay”. So
variable “delay” will effect enable signal which can slow down this process.

Part 2 – Code and Functional Coverage

Cover coverage
✦ Open the RTL files of the DUT
At first we open the statement coverage in the analyse window, the results are
as the pictures below:

uart0:

WB_interface:

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REGS:

DBG:

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✦ Explain the lines which are not covered

Code coverage which include Line/Block/Statement coverage, Toggle coverage,
Conditions coverage etc. For the statement coverage, it verifies that “has
each  statement  in the program been executed?” . So the lines which are not
covered (statement) which means it hasn’t been executed, some parts of the
statement may not be reachable.

✦ In the analysis window, open the toggle coverage. 


uart0:

WB_interface:

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REGS:






DBG:

✦ Explain
Toggle coverage reports describe design activity in terms of changes in signal
values. It verifies that “did this bit of this wire/register change from a value of 0
to 1 and back from 1 to zero 0 during simulation?” . A bit is said to be fully
covered when it toggles back and forth at least once.
If a bit is never changes value, it is usually an indication that a mode is not
being exercised in the design or a data path has a stuck-at issue.

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✦ Now look at the regs/transmitter and the regs/receiver FSM.

✦ Explain what is not covered in the transmitter FSM.

The FSM transition between state s_send_byte and state s_send_stop.

✦ Explain globally the FSM coverage

Finite state machine (FSM) coverage verifies that "Did I reach all of the states
and traverse all possible paths through a given state machine?”.
there are 2 parts of FSM coverage, one is verifying whether all the FSM states
hit during the simulation, the other is verifying if the FSM transition between all
states is reachable in simulation.

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Functional Coverage

We implement coverage groups to add further functional information of the

targeted feature.

Open the cover group window and analyse coverage

After we change the repeat number, The percentage of coverage has gone up.


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Conclusion:

During this lab, we understand well UVM sequence design. We have also
successfully implemented the different sequences and randomised tests in order
to exercise the different functionalities of UART. Then we implemented code
coverage and functional coverage to check if the sequences cover well.

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