Uc2625 Ep

UC2625-EP
www.ti.com .................................................................................................................................................................................................. SLUS802 MARCH 2008
BRUSHLESS DC MOTOR CONTROLLER

1FEATURES
Controlled Baseline Drives Power MOSFETs or Power Darlingtons
One Assembly Site Directly
One Test Site 50-V Open Collector High-Side Drivers
One Fabrication Site Latched Soft Start
Extended Temperature Performance of 55C High-speed Current-Sense Amplifier with Ideal
to 125C Diode
Enhanced Diminishing Manufacturing Sources Pulse-by-Pulse and Average Current Sensing
(DMS) Support Over-Voltage and Under-Voltage Protection
Enhanced Product-Change Notification Direction Latch for Safe Direction Reversal
Qualification Pedigree (1) Tachometer
(1) Component qualification in accordance with JEDEC and Trimmed Reference Sources 30 mA
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited Programmable Cross-Conduction Protection
to, Highly Accelerated Stress Test (HAST) or biased 85/85, Two-Quadrant and Four-Quadrant Operation
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The UC2625 motor controller integrates most of the functions required for high-performance brushless dc motor
control into one package. When coupled with external power MOSFETs or Darlingtons, this device performs
fixed-frequency PWM motor control in either voltage or current mode while implementing closed loop speed
control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection.
Although specified for operation from power supplies between 10 V and 18 V, the UC2625 can control higher
voltage power devices with external level-shifting components. The UC2625 contains fast, high-current push-pull
drivers for low-side power devices and 50-V open-collector outputs for high-side power devices or level shifting
circuitry.
The UC2625 is characterized for operation over the military temperature range of 55C to 125C.
ORDERING INFORMATION (1)

ORDERABLE PART TOP-SIDE
TA PACKAGE (2)
NUMBER MARKING
PDIP N UC2625MNEP UC2625EP
55C to 125C
SOIC DW UC2625MDWREP UC2625EP
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2008, Texas Instruments Incorporated
UC2625-EP
SLUS802 MARCH 2008 .................................................................................................................................................................................................. www.ti.com
Typical Application
+5 V TO HALL +15 V VMOTOR
VREF
SENSORS
3 kW +
100 nF 100 nF + 100 m F
2N3904
20 m F
20 m F 10 W
10 kW
3 kW 10 kW
ROSC 2 19 11
QUAD 33 kW 2N3906
IRF9350
22 3 kW
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
100 nF
CHANNELS
18
28 UC3625
4 kW
14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10 W REVERSE
2200 pF IRF532
12
COSC
15 20
BRAKE 21 26 3 24 23 8 9 10 4 5 7 10 kW
100 nF
5 nF
3 nF 68 kW REQUIRED
CT RT 240 W FOR
100 nF FROM HALL
AVERAGE
SENSORS 0.02 W
2 nF CURRENT
5 nF 240 W RS SENSING
51 kW 2 nF
0.02 W
2 nF RD
VREF
ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VCC 20
Supply voltage
PWR VCC 20
PWM IN 0.3 to 6
E/A IN(+), E/A IN() 0.3 to 12
V
ISENSE1, ISENSE2 1.3 to 6
OV-COAST, DIR, SPEED-IN, SSTART, QUAD SEL 0.3 to 8
H1, H2, H3 0.3 to 12
PU Output Voltage 0.3 to 50
PU +200 continuous
PD 200 continuous
E/A 10
Output current mA
ISENSE 10
TACH OUT 10
VREF 50 continuous
TJ Operating temperature range 55 to 125 C
(1) Currents are positive into and negative out of the specified terminal.
2 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s) :UC2625-EP

UC2625-EP
CONNECTION DIAGRAM
E/A IN(+) 1 28 E/A IN(-)
VREF 2 27 E/A OUT
ISENSE 3 26 PWM IN
ISENSE1 4 25 RC-OSC
ISENSE2 5 24 SSTART
DIR 6 23 OV-COAST
SPEED-IN 7 22 QUAD SEL
H1 8 21 RC-BRAKE
H2 9 20 TACH-OUT
H3 10 19 VCC
PWR VCC 11 18 PUA
PDC 12 17 PUB
PDB 13 16 PUC
PDA 14 15 GND
A. This pinout applies to the SOIC (DW) package.
Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

UC2625-EP
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for: TA = 25C; Pwr VCC = VCC = 12 V; ROSC = 20 k to VREF; COSC = 2 nF;
RTACH = 33 k; CTACH = 10 nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
Supply current 14.5 30.0 mA
VCC turn-on threshold -55C to 125C 8.65 8.95 9.55
V
VCC turn-off threshold 7.75 8.05 8.55
Overvoltage/Coast
OV-COAST inhibit threshold 1.65 1.75 1.85
OV-COAST restart threshold 1.535 1.65 1.75 V
-55C to 125C
OV-COAST hysteresis 0.05 0.10 0.155
OV-COAST input current 10 1 10 A
Logic Inputs
H1, H2, H3 low threshold 0.8 1.0 1.25
-55C to 125C V
H1, H2, H3 high threshold 1.6 1.9 2.0
H1, H2, H3 input current -55C to 125C, to 0 V 400 250 120 A
QUAD SEL, dir thresholds -55C to 125C 0.8 1.4 3.0 V
QUAD SEL hysteresis 70 mV
DIR hysteresis 0.6 V
QUAD SEL input current 30 50 150
A
DIR input current 30 1 30
PWM Amp/Comparator
E/A IN(+), E/A IN() input current To 2.5 V 5.0 0.1 5.0
A
PWM IN input current To 2.5 V 0 3 30
Error amp input offset 0 V < VCOMMON-MODE < 3 V 10 10 mV
Error amp voltage gain 70 90 dB
E/A OUT range 0.25 3.50
V
-55C to 125C 0.25 4.55
Pullup current To 0 V -16 10 5
A
To 0 V , -55C to 125C 17.5 -5
SSTART
Discharge current To 2.5 V 0.1 0.4 3.0 mA
Restart threshold 0.1 0.2 0.3 V
Current Amp
Gain ISENSE1 = 0.3 V, ISENSE2 = 0.5 V to 0.7 V 1.75 1.95 2.15 V/V
Level shift ISENSE1 = 0.3 V, ISENSE2 = 0.3 V 2.4 2.5 2.65
Peak current threshold 0.14 0.20 0.26 V
ISENSE1 = 0 V, force ISENSE2
Over current threshold 0.26 0.30 0.36
ISENSE1, ISENSE2 input current 850 320 0
To 0 V A
ISENSE1, ISENSE2 offset current 2 12
Range ISENSE1, ISENSE2 1 2 V
Tachometer/Brake
TACH-OUT high level 4.7 5 5.3
-55C to 125C, 10 k to 2.5 V V
TACH-OUT low level 0.2
On time 170 220 280 s
On time change with temp -55C to 125C 0.1%
RC-BRAKE input current To 0 V 4.0 1.9 mA
Threshold to brake, RC-brake -55C to 125C 0.8 1.0 1.2
V
Brake hysteresis, RC-brake 0.09

UC2625-EP
ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for: TA = 25C; Pwr VCC = VCC = 12 V; ROSC = 20 k to VREF; COSC = 2 nF;
RTACH = 33 k; CTACH = 10 nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SPEED-IN threshold -55C to 125C 220 257 290 mV
SPEED-IN input current 30 5 30 A
Low-Side Drivers
Voh, 1 mA, down from VCC 1.60 2.50
Voh, 50 mA, down from VCC 1.75 2.45
-55C to 125C V
Vol, 1 mA 0.05 0.4
Vol, 50 mA 0.36 0.8
Rise/fall time 10% to 90% slew time, into 1 nF 50 ns
High-Side Drivers
Vol, 1 mA 0.1 0.4
-55C to 125C V
Vol, 50 mA 1.0 1.8
Leakage current Output voltage = 50 V 30 A
Fall time 10% to 90% slew time, 50 mA load 50 ns
Oscillator
40 50 60
Frequency -40C to 105C 35 65 kHz
-55C to 125C 30 80
Reference
Iref = 0 mA 4.9 5.0 5.1
Output voltage V
-55C to 125C 4.7 5.0 5.3
Load regulation 0 mA to 20 mA load 40 5
mV
Line regulation 10 V to 18 V VCC 10 1 10
Short circuit current -55C to 125C 50 100 150 mA
Miscellaneous
Output turn-on delay 1
s
Output turn-off delay 1

UC2625-EP
Block Diagram
QUAD SEL 22
5V
2 VREF
RC-OSC 25 OSC S Q REFERENCE
PWM CLOCK
PWM IN 26 R
E/A OUT 27
E/A IN(+) 1 2.9 V
E/A IN () 28
10A
SSTART 24
ISENSE 3 R Q Q1
ABS VALUE 0.2 V
2.5 V 250
ISENSE1 4 S
2X
ISENSE2 5 3.1 V
VCC 19
9V
PWM
OV-COAST 23 CLOCK
1.75 V 18 PUA
DIR 6 17 PUB
DIRECTION
SPEED-IN 7 LATCH
0.25 V 16 PUC
+5 V PWM CLOCK
DIR COAST CHOP QUAD 11 PWR VCC
H1 8 D Q H1 CROSS
14 PDA
CONDUCTION
+5 V L PROTECTION
LATCHES
H2 9 D Q H2 DECODER
13 PDB
+5 V L
H3 10 D Q H3
BRAKE 12 PDC
L
EDGE
DETECT 15 GND
+5 V
2k
RC-BRAKE 21 ONE 20 TACH-OUT
SHOT
1V

UC2625-EP
DEVICE INFORMATION
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
The position decoder logic translates the Hall signals and the DIR signal to the
correct driver signals (PUs and PDs). To prevent output stage damage, the signal
on DIR is first loaded into a direction latch, then shifted through a two-bit register.
As long as SPEED-IN is less than 250 mV, the direction latch is transparent. When
SPEED-IN is higher than 250 mV, the direction latch inhibits all changes
indirection. SPEED-IN can be connected to TACH-OUT through a filter, so that the
direction latch is only transparent when the motor is spinning slowly, and has too
little stored energy to damage power devices.
Additional circuitry detects when the input and output of the direction latch are
DIR, SPEED-IN 6, 7
different, or when the input and output of the shift register are different, and inhibits
all output drives during that time. This can be used to allow the motor to coast to a
safe speed before reversing.
The shift register ensures that direction can not be changed instantaneously. The
register is clocked by the PWM oscillator, so the delay between direction changes
is always going to be between one and two oscillator periods. At 40 kHz, this
corresponds to a delay of between 25 s and 50 s. Regardless of output stage,
25 s deadtime should be adequate to ensure no overlap cross-conduction.
Toggling DIR causes an output pulse on TACH-OUT regardless of motor speed.
E/A IN(+) and E/A IN() are not internally committed to allow for a wide variety of
uses. They can be connected to the ISENSE, to TACH-OUT through a filter, to an
external command voltage, to a D/A converter for computer control, or to another
op amp for more elegant feedback loops. The error amplifier is compensated for
unity gain stability, so E/A OUT can be tied to E/A IN() for feedback and major
E/A IN(+), E/A IN(), E/A 1, 28, 27, loop compensation.
OUT, PWM IN 26 E/A OUT and PWM In drive the PWM comparator. For voltage-mode PWM
systems, PWM In can be connected to RC-OSC. The PWM comparator clears the
PWM latch, commanding the outputs to chop.
The error amplifier can be biased off by connecting E/A IN() to a higher voltage
than /EA IN(+). When biased off, E/A OUT appears to the application as a resistor
to ground. E/A OUT can then be driven by an external amplifier.
All thresholds and outputs are referred to the GND pin except for the PD and PU
GND 15
outputs.
The three shaft position sensor inputs consist of hysteresis comparators with input
pullup resistors. Logic thresholds meet TTL specifications and can be driven by
5-V CMOS, 12-V CMOS, NMOS, or open-collectors.
Connect these inputs to motor shaft position sensors that are positioned 120
electrical degrees apart. If noisy signals are expected, zener clamp and filter these
H1, H2, H3 8, 9, 10 inputs with 6-V zeners and an RC filter. Suggested filtering components are 1 k
and 2 nF. Edge skew in the filter is not a problem, because sensors normally
generate modified gray code with only one output changing at a time, but rise and
fall times must be shorter than 20 s for correct tachometer operation. Motors with
60 electrical degree position sensor coding can be used if one or two of the
position sensor signals is inverted.
The current sense amplifier has a fixed gain of approximately two. It also has a
built-in level shift of approximately 2.5 V. The signal appearing on ISENSE is:
ISENSE = 2.5 V + (2 ABS ( ISENSE1 ISENSE2) )
ISENSE1 and ISENSE2 are interchangeable and can be used as differential inputs.
The differential signal applied can be as high as 0.5 V before saturation.
If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a
capacitor from ISENSE to ground. Filtering this way allows fast signal inversions to
be correctly processed by the absolute value circuit. The peak-current comparator
ISENSE1, ISENSE2,
3, 4, 5 allows the PWM to enter a current-limit mode with current in the windings never
ISENSE
exceeding approximately 0.2 V / RSENSE. The overcurrent comparator provides a
fail-safe shutdown in the unlikely case of current exceeding 0.3 V / RSENSE. Then,
softstart is commanded, and all outputs are turned off until the high current
condition is removed. It is often essential to use some filter driving ISENSE1 and
ISENSE2 to reject extreme spikes and to control slew rate. Reasonable starting
values for filter components might be 250- series resistors and a 5-nF capacitor
between ISENSE1 and ISENSE2. Input resistors should be kept small and
matched to maintain gain accuracy.
This input can be used as an over-voltage shut-down input, as a coast input, or
OV-COAST 23
both. This input can be driven by TTL, 5-V CMOS, or 12-V CMOS.

UC2625-EP
Terminal Functions (continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
These outputs can drive the gates of N-channel power MOSFETs directly or they
can drive the bases of power Darlingtons if some form of current limiting is used.
They are meant to drive low-side power devices in high-current output stages.
PDA, PDB, PDC 12, 13, 14 Current available from these pins can peak as high as 0.5 A. These outputs feature
a true totem-pole output stage. Beware of exceeding device power dissipation
limits when using these outputs for high continuous currents. These outputs pull
high to turn a low-side device on (active high).
These outputs are open-collector, high-voltage drivers that are meant to drive
high-side power devices in high-current output stages. These are active low
outputs, meaning that these outputs pull low to command a high-side device on.
These outputs can drive low-voltage PNP Darlingtons and P-channel MOSFETs
PUA, PUB, PUC 16, 17, 18
directly, and can drive any high-voltage device using external charge pump
techniques, transformer signal coupling, cascode level-shift transistors, or
opto-isolated drive (high-speed opto devices are recommended). (See
applications).
This supply pin carries the current sourced by the PD outputs. When connecting
PD outputs directly to the bases of power Darlingtons, the PWR VCC pin can be
PWR VCC 11
current limited with a resistor. Darlington outputs can also be "Baker Clamped" with
diodes from collectors back to PWR VCC. (See Applications)
The device can chop power devices in either of two modes, referred to as
two-quadrant (Quad Sellow) and four quadrant (Quad Sel high). When
two-quadrant chopping, the pulldown power devices are chopped by the output of
the PWM latch while the pullup drivers remain on. The load chops into one
commutation diode, and except for back-EMF, will exhibit slow discharge current
and faster charge current. Two-quadrant chopping can be more efficient than
QUAD SEL 22
four-quadrant.
When four-quadrant chopping, all power drivers are chopped by the PWM latch,
causing the load current to flow into two diodes during chopping. This mode
exhibits better control of load current when current is low, and is preferred in servo
systems for equal control over acceleration and deceleration. The QUAD SEL input
has no effect on operation during braking.
Each time the TACH-OUT pulses, the capacitor tied to RC-BRAKE discharges
from approximately 3.33 V down to 1.67 V through a resistor. The tachometer
pulse width is approximately T = 0.67 RT CT, where RT and CT are a resistor and
capacitor from RC-BRAKE to ground. Recommended values for RT are 10 k to
500 k, and recommended values for CT are 1 nF to 100 nF, allowing times
between 5 s and 10 ms. Best accuracy and stability are achieved with values in
the centers of those ranges.
RC-BRAKE also has another function. If RC-BRAKE pin is pulled below the brake
RC-BRAKE 21 threshold, the device enters brake mode. This mode consists of turning off all three
high-side devices, enabling all three low-side devices, and disabling the
tachometer. The only things that inhibit low-side device operation in braking are
low-supply, exceeding peak current, OV-COAST command, and the PWM
comparator signal. The last of these means that if current sense is implemented
such that the signal in the current sense amplifier is proportional to braking current,
the low-side devices will brake the motor with current control. (See applications)
Simpler current sense connections results in uncontrolled braking and potential
damage to the power devices.
The UC3625 can regulate motor current using fixed-frequency pulse width
modulation (PWM). The RC-OSC pin sets oscillator frequency by means of timing
resistor ROSC from the RC-OSC pin to VREF and capacitor COSC from RC-OSC
to Gnd. Resistors 10 k to 100 k and capacitors 1 nF to 100 nF works the best,
but frequency should always be below 500 kHz. Oscillator frequency is
approximately:
RC-OSC 25 F = 2/(ROSC x COSC )
Additional components can be added to this device to cause it to operate as a
fixed off-time PWM rather than a fixed frequency PWM, using the RC-OSC pin to
select the monostable time constant.
The voltage on the RC-OSC pin is normally a ramp of about 1.2 V peak-to-peak,
centered at approximately 1.6 V. This ramp can be used for voltage-mode PWM
control, or can be used for slope compensation in current-mode control.

UC2625-EP
Terminal Functions (continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
Any time that VCC drops below threshold or the sensed current exceeds the
over-current threshold, the soft-start latch is set. When set, it turns on a transistor
that pulls down on SSTART. Normally, a capacitor is connected to this pin, and the
transistor will completely discharge the capacitor. A comparator senses when the
NPN transistor has completely discharged the capacitor, and allows the soft-start
latch to clear when the fault is removed. When the fault is removed, the soft-start
capacitor charges from the on-chip current source.
SSTART clamps the output of the error amplifier, not allowing the error amplifier
SSTART 24
output voltage to exceed SSTART regardless of input. The ramp on RC-OSC can
be applied to PWM In and compared to E/A OUT. With SSTART discharged below
0.2 V and the ramp minimum being approximately 1.0 V, the PWM comparator
keeps the PWM latch cleared and the outputs off. As SSTART rises, the PWM
comparator begins to duty-cycle modulate the PWM latch until the error amplifier
inputs overcome the clamp. This provides for a safe and orderly motor start-up
from an off or fault condition. A 51-k resister is added between VREF and
SSTART to ensure switching.
Any change in the H1, H2, or H3 inputs loads data from these inputs into the
position sensor latches. At the same time data is loaded, a fixed-width 5-V pulse is
triggered on TACH-OUT. The average value of the voltage on TACH-OUT is
directly proportional to speed, so this output can be used as a true tachometer for
speed feedback with an external filter or averaging circuit which usually consists of
TACH-OUT 20 a resistor and capacitor.
Whenever TACH-OUT is high, the position latches are inhibited, such that during
the noisiest part of the commutation cycle, additional commutations are not
possible. Although this effectively sets a maximum rotational speed, the maximum
speed can be set above the highest expected speed, preventing false commutation
and chatter.
This device operates with supplies between 10 V and 18 V. Under-voltage lockout
keeps all outputs off below 7.5 V, insuring that the output transistors never turn on
VCC 19 until full drive capability is available. Bypass VCC to ground with an 0.1-F ceramic
capacitor. Using a 10-F electrolytic bypass capacitor as well can be beneficial in
applications with high supply impedance.
This pin provides regulated 5 V for driving Hall-effect devices and speed control
circuitry. VREF reaches 5 V before VCC enables, ensuring that Hall-effect devices
VREF 2 powered from VREF becomes active before the UC3625 drives any output. For
proper performance VREF should be bypassed with at least a 0.1-F capacitor to
ground.

UC2625-EP
TYPICAL CHARACTERISTICS
Oscillator Frequency Tachometer on Time
vs vs
COSC and ROSC RT and CT
1 MHz 100 ms
10 ms RT 500 k
ROSC 10 k RT 100 k
100 kHz
Oscillator Frequency
ROSC 10 k
1 ms
On Time
ROSC 100 k
10 kHz
100 ms
RT 10 k
1 kHz 10 ms RT 30 k
1 ms
0.001 0.01 0.1
100 Hz
0.001 0.01 0.1 CT mF
COSC (mF)
Figure 1. Figure 2.
Supply Current Soft-Start Pullup Current

vs vs
Temperature Temperature
20 -5
18 -6
16 -7
14 -8
Soft Start Current mA
Supply Current mA
12 -9
10 -10
8 -11
6 -12
4 -13
2 -14
0 -15
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
Temperature C Temperature C
Figure 3. Figure 4.

UC2625-EP
TYPICAL CHARACTERISTICS (continued)
Soft-Start Discharge Current Current Sense Amplifier Transfer Function

vs vs
Temperature ISENSE2 ISENSE1
1.25 3.5
1.00
Soft Start Current mA
.75
ISENSE V
3
.50
.25
0 2.5
-75 -50 -25 0 25 50 75 100 125 -0.5 0.0 0.5
Temperature C
ISENSE2 ISENSE1 V
Figure 5. Figure 6.

UC2625-EP
APPLICATION INFORMATION
Cross Conduction Prevention

The UC2625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought
must always be given to cross conduction in output stage design because no amount of dead time can prevent
fast slewing signals from coupling drive to a power device through a parasitic capacitance.
The UC2625 contains input latches that serve as noise blanking filters. These latches remain transparent through
any phase of a motor rotation and latch immediately after an input transition is detected. They remain latched for
two cycles of the PWM oscillator. At a PWM oscillator speed of 20 kHz, this corresponds to 50 s to 100 s of
blank time which limits maximum rotational speed to 100 kRPM for a motor with six transitions per rotation or 50
kRPM for a motor with 12 transitions per rotation.
This prevents noise generated in the first 50 s of a transition from propagating to the output transistors and
causing cross-conduction or chatter.
The UC2625 also contains six flip flops corresponding to the six output drive signals. One of these flip flops is set
every time that an output drive signal is turned on, and cleared two PWM oscillator cycles after that drive signal
is turned off. The output of each flip flop is used to inhibit drive to the opposing output (Figure 7). In this way, it is
impossible to turn on driver PUA and PDA at the same time. It is also impossible for one of these drivers to turn
on without the other driver having been off for at least two PWM oscillator clocks.
EDGE SHIFT
S Q
FINDER REG
PWM R Q PUA
CLK
PULL UP
FROM S Q
DECODER
R Q
PULL PDA
DOWN
Figure 7. Cross Conduction Prevention

UC2625-EP
Power Stage Design

The UC2625 is useful in a wide variety of applications, including high-power in robotics and machinery. The
power output stages used in such equipment can take a number of forms, according to the intended performance
and purpose of the system. Figure 8 show four different power stages with the advantages and disadvantages of
each.
For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the
windings. These diodes should have a continuous current rating at least equal to the operating motor current,
since diode conduction duty-cycle can be high. For low-voltage systems, Schottky diodes are preferred. In higher
voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended.
In a pulse-by-pulse current control arrangement, current sensing is done by resistor RS, through which the
transistor's currents are passed (Fig. A, B, and C). In these cases, RD is not needed. The low-side circulating
diodes go to ground and the current sense terminals of the UC2625 (ISENSE1 and ISENSE2) are connected to RS
through a differential RC filter. The input bias current of the current sense amplifier causes a common mode
offset voltage to appear at both inputs, so for best accuracy, keep the filter resistors below 2 k and matched.
The current that flows through RS is discontinuous because of chopping. It flows during the on time of the power
stage and is zero during the off time. Consequently, the voltage across RS consists of a series of pulses,
occurring at the PWM frequency, with a peak value indicative of the peak motor current.
To sense average motor current instead of peak current, add another current sense resistor (RD in Fig. D) to
measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high). The
negative voltage across RD is corrected by the absolute value current sense amplifier. Within the limitations
imposed by Table 1, the circuit of Fig. B can also sense average current.

UC2625-EP
FIGURE A FIGURE B
TO TO
MOTOR MOTOR
RS RS
FIGURE C
FIGURE D
TO
TO
MOTOR
MOTOR
RS RD
RS
Figure 8. Four Power Stage Designs
Table 1. Imposed Limitations for Figure 8

SAFE CURRENT SENSE
2 QUADRANT 4 QUADRANT POWER REVERSE
BRAKING Pulse-by-Pulse Average
Figure A Yes No No N0 Yes No
Figure B Yes Yes No In 4-quad mode only Yes Yes
Figure C Yes Yes Yes In 4-quad mode only Yes No
Figure D Yes Yes Yes In 4-quad mode only Yes Yes

UC2625-EP
For drives where speed is critical, P-channel MOSFETs can be driven by emitter followers as shown in Figure 9.
Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to limit
gate-source voltage on the MOSFET. A series gate resistor is not necessary, but always advisable to control
overshoot and ringing.
High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 V greater
than the motor supply is provided (See Figure 10) To protect the MOSFET, the boost supply should not be
higher than 18 V above the motor supply.
For under 200-V 2-quadrant applications, a power NPN driven by a small P-Channel MOSFET performs well as
a high-side driver as in Figure 11. A high voltage small-signal NPN is used as a level shift and a high voltage
low-current MOSFET provides drive. Although the NPN does not saturate if used within its limitations, the
base-emitter resistor on the NPN is still the speed-limiting component.
Figure 12 shows a power NPN Darlington drive technique using a clamp to prevent deep saturation. By limiting
saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of
base series resistance also adds to the speed of this approach.
Figure 9. Fast High-Side P-Channel Driver Figure 10. Optocoupled N-Channel High-Side Driver

UC2625-EP
Figure 11. Power NPN High-Side Driver Figure 12. Power NPN Low-Side Driver

UC2625-EP
Fast High-Side N-Channel Driver with Transformer Isolation

A small pulse transformer can provide excellent isolation between the UC2625 and a high-voltage N-Channel
MOSFET while also coupling gate drive power. In this circuit (shown in Figure 13), a UC3724 is used as a
transformer driver/encoder that duty-cycle modulates the transformer with a 150-kHz pulse train. The UC3725
rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2-A peak
current.
+12V VMOTOR
3
33kW 6 7
PUA 2
7 UC3724N UC3725N
4
4 8
1:2
8 1 2 5 1 6 3
5kW 1nF 100nF
TO MOTOR
Figure 13. Fast High-Side N-Channel Driver with Transformer Isolation
Both the UC3724 and the UC3725 can operate up to 500 kHz if the pulse transformer is selected appropriately.
To raise the operating frequency, either lower the timing resistor of the UC3724 (1 k min), lower the timing
capacitor of the UC3724 (500 pF min) or both.
If there is significant capacitance between transformer primary and secondary, together with very high output
slew rate, then it may be necessary to add clamp diodes from the transformer primary to 12 V and ground.
General purpose small signal switching diodes such as 1N4148 are normally adequate.
The UC3725 also has provisions for MOSFET current limiting. See the UC3725 data sheet for more information
on implementing this.

UC2625-EP
Computational Truth Table

Table 2 shows the outputs of the gate drive and open collector outputs for given hall input codes and direction
signals. Numbers at the top of the columns are pin numbers.
These devices operate with position sensor encoding that has either one or two signals high at a time, never all
low or all high. This coding is sometimes referred to as "120 Coding" because the coding is the same as coding
with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals,
only one low-side driver turns on (go high) and one high-side driver turns on (pull low) at any time.
Table 2. Computational Truth Table

INPUTS OUTPUTS
DIR H1 H2 H3 Low-Side High-Side
6 8 9 10 12 13 14 16 17 18
1 0 0 1 L H L L H H
1 0 1 1 L L H L H H
1 0 1 0 L L H H L H
1 1 1 0 H L L H L H
1 1 0 0 H L L H H L
1 1 0 1 L H L H H L
0 1 0 1 L L H H L H
0 1 0 0 L L H L H H
0 1 1 0 L H L L H H
0 0 1 0 L H L H H L
0 0 1 1 H L L H H L
0 0 0 1 H L L H L H
X 1 1 1 L L L H H H
X 0 0 0 L L L H H H

UC2625-EP
+5V TO HALL +15V VMOTOR

VREF
SENSORS
3kW +
100nF 100nF + 100mF
2N3904
20mF
20mF 10W
10kW
3kW 10kW
ROSC 2 19 11
QUAD 33kW 2N3906
IRF9350
22 3kW
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
CHANNELS
18
28 UC3625
4kW
100nF 14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10W REVERSE
2200pF IRF532
12
COSC
15 20
BRAKE 21 26 3 24 23 8 9 10 4 5 7 10kW
5nF 100nF
3nF 68kW REQUIRED
CT RT FROM 240W FOR
100nF HALL AVERAGE
2nF SENSORS 0.02 CURRENT
5nF 240W W SENSING
51kW 2nF RS
0.02
2nF W
RD
VREF
Figure 14. 45-V/8-A Brushless DC Motor Drive Circuit
N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for
high-side drivers. Resistors are used to level shift the UC2625 open-collector outputs, driving emitter followers
into the MOSFET gate. A 12-V zener clamp insures that the MOSFET gate-source voltage never exceeds 12 V.
Series 10- gate resistors tame gate reactance, preventing oscillations and minimizing ringing.
The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the
capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation
signal.
The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed
control. This control is often referred to as "voltage mode" because the potentiometer position sets the average
motor voltage. This controls speed because steady-state motor speed is closely related to applied voltage.
Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the
motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be
forced into the power MOSFETs.
A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that
braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous
current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant
operation.
The 68-k and 3-nF tachometer components set maximum commutation time at 140 s. This permits smooth
operation up to 35,000 RPM for four-pole motors, yet gives 140 s of noise blanking after commutation.

PACKAGE OPTION ADDENDUM
www.ti.com 17-Apr-2008
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
UC2625MDWREP ACTIVE SOIC DW 28 1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2625MNEP ACTIVE PDIP N 28 13 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
V62/08624-01XE ACTIVE PDIP N 28 13 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
V62/08624-01YE ACTIVE SOIC DW 28 1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
UC2625MDWREP SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2625MDWREP SOIC DW 28 1000 346.0 346.0 49.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Copyright 2008, Texas Instruments Incorporated

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www.ti.com .................................................................................................................................................................................................. SLUS802 MARCH 2008

BRUSHLESS DC MOTOR CONTROLLER

ORDERING INFORMATION (1)

ABSOLUTE MAXIMUM RATINGS (1)

2 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

E/A IN(+) 1 28 E/A IN(-)

VREF 2 27 E/A OUT

SPEED-IN 7 22 QUAD SEL

PWR VCC 11 18 PUA

A. This pinout applies to the SOIC (DW) package.

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

ELECTRICAL CHARACTERISTICS (continued)

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 5

E/A IN(+) 1 2.9 V

6 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 7

Terminal Functions (continued)

8 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

Terminal Functions (continued)

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 9

Supply Current Soft-Start Pullup Current

10 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

TYPICAL CHARACTERISTICS (continued)

Soft-Start Discharge Current Current Sense Amplifier Transfer Function

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 11

Cross Conduction Prevention

Figure 7. Cross Conduction Prevention

12 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

Power Stage Design

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 8. Four Power Stage Designs

Table 1. Imposed Limitations for Figure 8

14 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 15

16 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

Fast High-Side N-Channel Driver with Transformer Isolation

5kW 1nF 100nF

Figure 13. Fast High-Side N-Channel Driver with Transformer Isolation

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 17

Computational Truth Table

Table 2. Computational Truth Table

18 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated

Product Folder Link(s) :UC2625-EP

+5V TO HALL +15V VMOTOR

Figure 14. 45-V/8-A Brushless DC Motor Drive Circuit

Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 19

TAPE AND REEL INFORMATION

*All dimensions are nominal

*All dimensions are nominal