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CDCVF2310
SCAS666D – JUNE 2001 – REVISED OCTOBER 2015

CDCVF2310 2.5-V to 3.3-V High-Performance Clock Buffer

1 Features 3 Description
•
1 High-Performance 1:10 Clock Driver The CDCVF2310 device is a high-performance, low-
skew clock buffer that operates up to 200 MHz. Two
• Operates up to 200 MHz at VDD 3.3 V banks of five outputs each provide low-skew copies
• Pin-to-Pin Skew < 100 ps at VDD 3.3 V of CLK. After power up, the default state of the
• VDD Range: 2.3 V to 3.6 V outputs is low regardless of the state of the control
• Operating Temperature Range –40°C to 105°C pins. For normal operation, the outputs of bank
1Y[0:4] or 2Y[0:4] can be placed in a low state when
• Supports 105ºC Ambient Temperature (see the control pins (1G or 2G, respectively) are held low
Thermal Considerations) and a negative clock edge is detected on the CLK
• Output Enable Glitch Suppression input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be
• Distributes One Clock Input to Two Banks of Five switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge
Outputs
is detected on the CLK input. The device operates in
• 25-Ω On-Chip Series Damping Resistors a 2.5-V and 3.3-V environment. The built-in output
• Packaged in 24-Pin TSSOP enable glitch suppression ensures a synchronized
output enable sequence to distribute full period clock
2 Applications signals.
• General-Purpose Applications The CDCVF2310 is characterized for operation from
–40°C to 85°C.
(1)
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
CDCVF2310 TSSOP (24) 4.40 mm × 7.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Functional Block Diagram

VDD VDD VDD VDD VDD VDD

1G Logic

1Y(4...0)
25 Ω 5

CLK

2Y(4...0)
25 Ω 5

2G Logic
CDCVF2310
GND GND GND GND GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 8.3 Feature Description................................................. 10
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 11
4 Revision History..................................................... 2 9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 12
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3 10 Power Supply Recommendations ..................... 14
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 15
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 15
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 15
6.5 Electrical Characteristics........................................... 4 11.3 Thermal Considerations ........................................ 15
6.6 Timing Requirements ............................................... 5 12 Device and Documentation Support ................. 16
6.7 Jitter Characteristics.................................................. 5 12.1 Documentation Support ........................................ 16
6.8 Switching Characteristics ......................................... 6 12.2 Community Resources.......................................... 16
6.9 Switching Characteristics .......................................... 6 12.3 Trademarks ........................................................... 16
6.10 Typical Characteristics ............................................ 7 12.4 Electrostatic Discharge Caution ............................ 16
7 Parameter Measurement Information .................. 8 12.5 Glossary ................................................................ 16
8 Detailed Description .............................................. 9 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................... 9
Information ........................................................... 16

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (January 2008) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

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5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View

GND 1 24 CLK
VDD 2 23 VDD
1Y0 3 22 VDD
1Y1 4 21 2Y0
1Y2 5 20 2Y1
GND 6 19 GND
GND 7 18 GND
1Y3 8 17 2Y2
1Y4 9 16 2Y3
VDD 10 15 VDD
1G 11 14 VDD
2Y4 12 13 2G

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1G 11 I
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2G 13 I
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4] 3, 4, 5, 8, 9 O Buffered output clocks
2Y[0:4] 21, 20, 17, 16, 12 O Buffered output clocks
CLK 24 I Input reference frequency
GND 1, 6, 7, 18, 19 — Ground
2, 10, 14, 15, 22,
VDD — DC power supply, 2.3 V – 3.6 V
23

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD Supply voltage –0.5 4.6 V
(2) (3)
VI Input voltage –0.5 VDD + 0.5 V
VO (2) (3)
Output voltage –0.5 VDD + 0.5 V
IIK Input clamp current VI < 0 or VI> VDD ±50 mA
Output clamp
IOK VO < 0 or VO > VDD ±50 mA
current
Continuous total
IO VO = 0 to VDD ±50 mA
output current
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.

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6.2 ESD Ratings

VALUE UNIT
(1)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

(1)
See
MIN NOM MAX UNIT
2.3 2.5
VDD Supply voltage V
3.3 3.6
VDD = 3 V to 3.6 V 0.8
VIL Low-level input voltage V
VDD = 2.3 V to 2.7 V 0.7
VDD = 3 V to 3.6 V 2
VIH High-level input voltage V
VDD = 2.3 V to 2.7 V 1.7
VI Input voltage 0 VDD V
VDD = 3 V to 3.6 V 12
IOH High-level output current mA
VDD = 2.3 V to 2.7 V 6
VDD = 3 V to 3.6 V 12
IOL Low-level output current mA
VDD = 2.3 V to 2.7 V 6
TA Operating free-air temperature –40 85 °C

(1) Unused inputs must be held high or low to prevent them from floating.

6.4 Thermal Information

CDCVF2310
(1)
THERMAL METRIC PW (TSSOP) UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 91.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.2 °C/W
RθJB Junction-to-board thermal resistance 46.4 °C/W
ψJT Junction-to-top characterization parameter 1.5 °C/W
ψJB Junction-to-board characterization parameter 45.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIK Input voltage VDD = 3 V II = –18 mA –1.2 V
II Input current VI = 0 V or VDD ±5 μA
CLK = 0 V or VDD , -40°C to 85°C 80 μA
IDD Static device current
IO = 0 mA ≤105°C 100 μA
CI Input capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.5 pF
CO Output capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.8 pF

(1) All typical values are at respective nominal VDD.

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Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VDD = 3.3 V ±0.3 V
VDD = min to max IOH = –100 μA VDD – 0.2
VOH High-level output voltage IOH = –12 mA 2.1 V
VDD = 3 V
IOH = –6 mA 2.4
VDD = min to max IOL = –100 μA 0.2
VOL Low-level output voltage IOL = 12 mA 0.8 V
VDD = 3 V
IOL = 6 mA 0.55
VDD = 3 V VO = 1 V –28
IOH High-level output current VDD = 3.3 V VO = 1.65 V –36 mA
VDD = 3.6 V VO = 3.135 V –14
VDD = 3 V VO = 1.95 V 28
IOL Low-level output current VDD = 3.3 V VO = 1.65 V 36 mA
VDD = 3.6 V VO = 0.4 V 14
VDD = 2.5 V ±0.2 V
VDD = min to max IOH = –100 μA VDD – 0.2
VOH High-level output voltage V
VDD = 2.3 V IOH = –6 mA 1.8
VDD = min to max IOL = 100 μA 0.2
VOL Low-level output voltage V
VDD = 2.3 V IOL = 6 mA 0.55
VDD = 2.3 V VO = 1 V –17
IOH High-level output current VDD = 2.5 V VO = 1.25 V –25 mA
VDD = 2.7 V VO = 2.375 V –10
VDD = 2.3 V VO = 1.2 V 17
IOL Low-level output current VDD = 2.5 V VO = 1.25 V 25 mA
VDD = 2.7 V VO = 0.3 V 10

6.6 Timing Requirements

over recommended ranges of supply voltage and operating free-air temperature
MIN MAX UNIT
VDD = 3 V to 3.6 V 0 200
fclk Clock frequency MHz
VDD = 2.3 V to 2.7 V 0 170

6.7 Jitter Characteristics

Characterized using CDCVF2310 Performance EVM when VDD= 3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER TEST CONDITIONS TYP UNIT
12 kHz to 5 MHz, fout = 30.72 MHz 52
tjitter Additive phase jitter from input to output 1Y0 fs rms
12 kHz to 20 MHz, fout = 125 MHz 45

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6.8 Switching Characteristics

VDD= 3.3V ±0.3V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tPLH f = 0 MHz to 200 MHz
CLK to Yn 1.3 2.8 ns
tPHL For circuit load, see Figure 2.
(1)
tsk(o) Output skew (Ym to Yn) (see Figure 4) 100 ps
tsk(p) Pulse skew (see Figure 5) 250 ps
tsk(pp) Part-to-part skew 500 ps
tr Rise time (see Figure 3) VO = 0.4 V to 2 V 0.7 2 V/ns
tf Fall time (see Figure 3) VO = 2 V to 0.4 V 0.7 2 V/ns
tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns
tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns
th(en) Enable hold time, G_high after CLK ↓ 0.4 ns
th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns

(1) The tsk(o) specification is only valid for equal loading of all outputs.

6.9 Switching Characteristics

VDD= 2.5V ±0.2V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tPLH f = 0 MHz to 170 MHz
CLK to Yn 1.5 3.5 ns
tPHL For circuit load, see Figure 2.
(1)
tsk(o) Output skew (Ym to Yn) (see Figure 4 ) 170 ps
tsk(p) Pulse skew (see Figure 5) 400 ps
tsk(pp) Part-to-part skew 600 ps
tr Rise time (see Figure 3) VO = 0.4 V to 1.7 V 0.5 1.4 V/ns
tf Fall time (see Figure 3) VO = 1.7 V to 0.4 V 0.5 1.4 V/ns
tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns
tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns
th(en) Enable hold time, G_high after CLK ↓ 0.4 ns
th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns

(1) The tsk(o) specification is only valid for equal loading of all outputs.

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6.10 Typical Characteristics

180
ICC 3.3V 25°C
ICC 2.5V 25°C
160

ICC Supply Current [mA]

140

120

100

80

60

40

20
0 20 40 60 80 100 120 140 160 180 200
Frequency [MHz]

Figure 1. Supply Current vs Frequency

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7 Parameter Measurement Information

From Output
Under Test

CL = 25 pF on Y n 500 Ω

A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.

Figure 2. Test Load Circuit

VDD
CLK 50% VDD
0V
t PLH t PHL
VOH
1.7 V or 2 V
Yn 50% VDD
0.4 V 0.4 V VOL
tr tf

Figure 3. Voltage Waveforms Propagation Delay Times

VDD
CLK
0V

VOH
Any Y 50% VDD
VOL

VOH
Any Y 50% VDD
VOL
t sk(o) t sk(o)

Figure 4. Output Skew

VDD
CLK 50% VDD
0V
t PLH t PHL
VOH
Yn 50% VDD
VOL
NOTE: tsk(p) = | tPLH – tPHL |

Figure 5. Pulse Skew

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8 Detailed Description

8.1 Overview
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-
V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.

8.2 Functional Block Diagram

3 1Y0
25 Ω

4
1Y1
25 Ω

5
1Y2
25 Ω

8
1Y3
25 Ω

9
1Y4
25 Ω

11 Logic Control
1G

13 Logic Control
2G

21
2Y0
24 25 Ω
CLK

20
2Y1
25 Ω

17
2Y2
25 Ω

16
2Y3
25 Ω

12
2Y4
25 Ω

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8.3 Feature Description

8.3.1 Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 6).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.

CLK

Gn

Yn

tsu(en) th(en)

a) Enable Mode

CLK

Gn

Yn

tsu(dis) th(dis)

b) Disable Mode
Figure 6. Enable and Disable Mode Relative to CLK↓

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8.4 Device Functional Modes

Table 1 lists the functional modes for the CDCVF2310.

Table 1. Function Table

INPUT OUTPUT
1G 2G CLK 1Y[0:4] 2Y[0:4]
L L ↓ L L
(1)
H L ↓ CLK L
L H ↓ L CLK (1)
H H ↓ CLK (1) CLK (1)

(1) After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCVF2310 is a LVCMOS buffer solution that can operate up to 200 MHz. Low output skew as well as the
ability for glitchless output enable and disable is featured to simultaneously enable or disable buffered clock
outputs as necessary in the application.

9.2 Typical Application

100 MHZ
LVCMOS Oscillator
50 W Trace
CLKIN VDD CMOS
Y0
CPU Clock

CMOS
Y1 FPGA Clock

1G 100 W
50 W Trace
From CPU PLL
GND Yn
Reference
100 W

Figure 7. Example System Configuration

9.2.1 Design Requirements

The CDCVF2310 shown in Figure 7 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.
The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
CDCVF2310 to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the CDCVF2310.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC-coupling can be used when common-mode voltage is
mismatched.

9.2.2 Detailed Design Procedure

Refer to Electrical Characteristics table to determine the appropriate series resistance needed for matching the
output impedance of the CDCVF2310 to that of the characteristic impedance of the transmission line.

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Typical Application (continued)

9.2.3 Application Curves

Figure 8. CDCVF2310 Output Phase Noise 89.1 fs Figure 9. CDCVF2310 Output Phase Noise 169.6 fs
(12 kHz to 20 MHz), Reference Phase Noise 76.9 fs, Output (12kHz to 5MHz), Reference Phase Noise 161.5 fs,
Frequency 125 MHz Frequency 30.72 MHz

The low-additive jitter of the CDCVF2310 can be seen in the previous application plots. The low-noise, 125-MHz
input source drives the CDCVF2310, resulting in 45-fs RMS additive jitter when integrated from 12 kHz to 20
MHz for this configuration. The low-noise 30.72-MHz input source drives the CDCVF2310, resulting in 52-fs RMS
additive jitter when integrated from 12 kHz to 5 MHz for this configuration.

CLK

GN

YN

Figure 10. CDCVF2310 Configured as Gate Function for Output Clock

The CDCVF2310 can be configured to generate a gated clock using the GN Please refer to Output Enable Glitch
Suppression Circuit for required timings.

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10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI
recommends adding as many high-frequency (for example, 0.1 µF) bypass capacitors, as there are supply
terminals in the package. TI recommends, but does not require, inserting a ferrite bead between the board power
supply and the chip power supply that isolates the high-frequency switching noises generated by the clock buffer;
these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an
appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and
the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage
required for proper operation.
Figure 12 shows this recommended power supply decoupling method.
VCC
Board Chip
Supply Ferrite Bead
Supply

C C C
10 µF 1 µF 0.1 µF

Figure 11. Power Supply Decoupling

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11 Layout

11.1 Layout Guidelines

Figure 12 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.

11.2 Layout Example

Ground bypass capacitor with low impedance

connection to ground plane
0402 or smaller body size capacitors are
recommended
Place bypass power supply capacitors as short
as possible to device pin

Figure 12. PCB Conceptual Layout

11.3 Thermal Considerations

CDCVF2310 supports high ambient temperature up to 105°C. The system designer needs to ensure that the
maximum junction temperature is not exceeded. Following Equation 1 can be used to calculate the junction
temperature based on the measured case temperature. The case temperature is defined as the hottest
temperature on the top of the device. The case temperature measurement can be performed with (in order of
accuracy) an IR camera, a fluor-optic probe, a thermocouple, or IR gun with a maximum field view of 4-mm
diameter just to name a few techniques. Further information can be found at SPRA953 and SLUA566
Tjunction = Tcase + (ψtj x Power) (1)

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
Using Thermal Calculation Tools for Analog Components, SLUA566

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CDCVF2310PW ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310

& no Sb/Br)
CDCVF2310PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310
& no Sb/Br)
CDCVF2310PWR ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310
& no Sb/Br)
CDCVF2310PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CKV2310
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Jul-2015

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CDCVF2310 :

• Enhanced Product: CDCVF2310-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jul-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCVF2310PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Jul-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCVF2310PWR TSSOP PW 24 2000 367.0 367.0 38.0

Pack Materials-Page 2
 IMPORTANT NOTICE

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