Data Sheet

ADuM340E/ADuM341E/ADuM342E
5.7 kV rms Quad Digital Isolators

FEATURES GENERAL DESCRIPTION

► High common-mode transient immunity: 180 kV/µs typical The ADuM340E/ADuM341E/ADuM342E1 are quad-channel digital
► High robustness to radiated and conducted noise isolators based on Analog Devices, Inc., iCoupler® technology.
► Low propagation delay Combining high speed, complementary metal-oxide semiconductor
(CMOS) and back-to-back monolithic air core transformer technolo-
► 6.2 ns typical (10 ns maximum) for 5 V operation
gy, these isolation components provide outstanding performance
► Low dynamic power consumption, <1.65 mA/ch at 1 Mbps characteristics and meet CISPR 32/EN 55032 Class B limits at 5
► 2.25 V to 5.5 V level translation Mbps. The maximum propagation delay is 10 ns with a pulse width
► 150 Mbps maximum guaranteed data rate for 5 V operation distortion of less than 3 ns at 5 V operation. Channel matching is
► High temperature operation: 125°C tight at 3.0 ns maximum.
► Safety and regulatory approvals The ADuM340E/ADuM341E/ADuM342E data channels are inde-
► UL recognition: 5700 V rms for 1 minute per UL 1577 pendent and are available in a variety of configurations with a
► VDE certificate of conformity (pending) withstand voltage rating of 5.7 kV rms (see Figure 26). The devices
► DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 operate with the supply voltage on either side ranging from 2.25
► VIORM = 1173 V peak
V to 5.5 V, providing compatibility with lower voltage systems as
well as enabling voltage translation functionality across the isolation
► 10,000 V peak reinforced surge isolation voltage
barrier.
► CSA certification per IEC 62368-1 and IEC 61010-1 (pending)
► TÜV Süd certification per EN 62368-1 (pending)
Two different fail-safe options are available, by which the outputs
transition to a predetermined state when the input power supply is
► CQC certification per GB4943.1-2022 (pending)
not applied.
► ±8 kV IEC 61000-4-2 ESD protection across isolation barrier
► ±5 kV HBM ESD protection on input/output pins
► Fail-safe high (E1) or low (E0) options
► 16-lead, RoHS compliant, SOIC package
► Backward compatibility with
► ADuM1400/ADuM1401/ADuM1402
► ADuM2400/ADuM2401/ADuM2402
► ADuM140E/ADuM141E/ADuM142E
► ADuM240E/ADuM241E/ADuM242E
► AEC-Q100 qualified for automotive applications
APPLICATIONS
► Serial peripheral interface (SPI) data converter isolation
► RS-485 and controller area network with flexible data rate (CAN
FD) industrial field bus isolation
► PWM controller signal isolation
► General-purpose multichannel isolation

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
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Data Sheet ADuM340E/ADuM341E/ADuM342E
TABLE OF CONTENTS

Features................................................................ 1 Electrostatic Discharge (ESD) Ratings.............15

Applications........................................................... 1 ESD Caution.....................................................15
General Description...............................................1 Pin Configurations and Function Descriptions.....16
Functional Block Diagrams....................................3 Typical Performance Characteristics................... 18
Specifications........................................................ 4 Theory of Operation.............................................20
Electrical Characteristics—5 V Operation.......... 4 Truth Table....................................................... 21
Electrical Characteristics—3.3 V Operation....... 7 Applications Information...................................... 22
Electrical Characteristics—2.5 V Operation..... 10 PCB Layout...................................................... 22
Insulation and Safety Related Specifications... 12 Propagation Delay Related Parameters...........22
Package Characteristics...................................12 Jitter Measurement...........................................22
Regulatory Information..................................... 13 Insulation Lifetime............................................ 22
DIN V VDE V 0884-11 (VDE V 0884-11) Outline Dimensions............................................. 24
Insulation Characteristics (Pending)...............13 Ordering Guide.................................................24
Recommended Operating Conditions.............. 14 Evaluation Boards............................................ 25
Absolute Maximum Ratings.................................15 Automotive Products........................................ 25

REVISION HISTORY

8/2023—Rev. 0 to Rev. A
Changes to Ordering Guide........................................................................................................................... 24

1/2023—Revision 0: Initial Version

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Data Sheet ADuM340E/ADuM341E/ADuM342E
FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADuM340E Functional Block Diagram

Figure 2. ADuM341E Functional Block Diagram

Figure 3. ADuM342E Functional Block Diagram

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation
range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 1. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within pulse width distortion (PWD) limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 3.5 6.2 10 ns 50% input to 50% output
Pulse Width Distortion PWD 0.3 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.1 ns Between any two units at the same temperature,
voltage, and load
Channel Matching
Codirectional tPSKCD 0.3 3.0 ns
Opposing Direction tPSKOD 0.3 3.0 ns
Jitter1 See the Jitter Measurement section
Random Jitter, RMS (1σ)2 tJIT(RJ) 7.19 ps 1 MHz clock input, all channels switching
Deterministic Jitter, Peak-to-Peak3, 4 tJIT(DJ) 223 ps 100 Mbps, 215 − 1 PRBS input
Total Jitter, Peak-to-Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS input5
(BER) 1 × 10−12
Without Crosstalk 292 ps Single channel switching
With Crosstalk 559 ps All channels switching
Output Enabled to High-Z tPHZ, tPLZ 3 5.5 12 ns Output high/low to high impedance
Output High-Z to Enabled tPZH, tPZL 3 5.5 12 ns Output high impedance to high/low
DC SPECIFICATIONS
Input Threshold Voltage VIx,VEx
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.85 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −4 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6 = 4 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx
VE1, VE2 Enable Input Pull-Up Current IPU −10 −6 µA VEx = 0 V
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx, VEx ≤ VIL
Quiescent Supply Current
ADuM340E
IDD1 (Q) 0.61 0.85 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.5 2.3 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 7.6 11.2 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 3.3 5.1 mA VI9 = 1 (E0), 0 (E1)10
ADuM341E
IDD1 (Q) 0.8 1.3 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.3 1.9 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 6.3 9.2 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 4.2 6 mA VI9 = 1 (E0), 0 (E1)10

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 1. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
ADuM342E
IDD1 (Q) 1.0 1.7 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.0 1.7 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 5.2 8.0 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 5.3 7.8 mA VI9 = 1 (E0), 0 (E1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.005 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.015 mA/Mbps Inputs switching, 50% duty cycle, CL = 0 nF
Undervoltage Lockout UVLO
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time11 tUVLO 60 μs UVLO release delay after VUVLO+ threshold
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM = 1000 V
|CML| 100 180 kV/µs VIx = 0 V, VCM = 1000 V
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, or D.
7 VIxH is the input side logic high.
8 VIxL is the input side logic low.
9 VI is the voltage input.
10 E0 refers to the ADuM340E0/ADuM341E0/ADuM342E0 models, and E1 refers to the ADuM340E1/ADuM341E1/ADuM342E1 models. See the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 2. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM340E
1 Mbps
Supply Current Side 1 IDD1 4.2 6.1 mA
Supply Current Side 2 IDD2 2.5 3.6 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.6 6.4 mA
Supply Current Side 2 IDD2 3.9 5.3 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 6.3 8.7 mA
Supply Current Side 2 IDD2 8.5 10.9 mA CL = 0 nF
ADuM341E
1 Mbps
Supply Current Side 1 IDD1 3.6 5.3 mA CL = 0 nF
Supply Current Side 2 IDD2 2.8 4.1 mA CL = 0 nF

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 2. Total Supply Current vs. Data Throughput (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions
25 Mbps
Supply Current Side 1 IDD1 4.4 6.0 mA CL = 0 nF
Supply Current Side 2 IDD2 4.0 5.6 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 6.7 9.2 mA CL = 0 nF
Supply Current Side 2 IDD2 7.9 10.5 mA CL = 0 nF
ADuM342E
1 Mbps
Supply Current Side 1 IDD1 3.1 4.9 mA CL = 0 nF
Supply Current Side 2 IDD2 3.2 4.8 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.1 6.1 mA CL = 0 nF
Supply Current Side 2 IDD2 4.2 5.9 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 7.3 10.0 mA CL = 0 nF
Supply Current Side 2 IDD2 7.3 10.0 mA CL = 0 nF

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation
range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 3. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 3.6 6.6 10 ns 50% input to 50% output
Pulse Width Distortion PWD 0.5 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.5 3.0 ns
Opposing Direction tPSKOD 0.5 3.0 ns
Jitter1 See the Jitter Measurement section
Random Jitter, RMS (1σ)2 tJIT(RJ) 7.1 ps 1 MHz clock input
Deterministic Jitter, Peak-to-Peak3, 4 tJIT(DJ) 243 ps 100 Mbps, 215 − 1 PRBS input
Total Jitter, Peak-to-Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS input5
(BER) 1 × 10−12
Without Crosstalk 318 ps Single channel switching
With Crosstalk 444 ps All channels switching
Output Enabled to High-Z tPHZ, tPLZ 3 5 12 ns Output high/low to high Impedance
Output High-Z to Enabled tPZH, tPZL 3 5 12 ns Output high impedance to high/low
DC SPECIFICATIONS
Input Threshold Voltage VIx,VEx
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.7 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −2 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6= 2 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −4 µA VE2 = 0 V
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx, VEx ≤ VIL
Quiescent Supply Current
ADuM340E
IDD1 (Q) 0.6 0.82 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.4 2.2 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 7.5 11.0 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 3.2 5.0 mA VI9 = 1 (E0), 0 (E1)10
ADuM341E
IDD1 (Q) 0.8 1.3 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.2 1.8 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 6.6 8.8 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 4.1 5.9 mA VI9 = 1 (E0), 0 (E1)10

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 3. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
ADuM342E
IDD1 (Q) 0.9 1.6 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.0 1.6 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 5.1 7.6 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 5.2 7.6 mA VI9 = 1 (E0), 0 (E1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.004 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.009 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time11 tUVLO 60 μs UVLO release delay after VUVLO+ threshold
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude
= 800 V
|CML| 100 180 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude =
800 V
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, or D.
7 VIxH is the input side logic high.
8 VIxL is the input side logic low.
9 VI is the voltage input.
10 E0 refers to ADuM340E0/ADuM341E0/ADuM342E0 models, and E1 refers to ADuM340E1/ADuM341E1/ADuM342E1 models. See the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 4. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM340E
1 Mbps
Supply Current Side 1 IDD1 4.1 6.0 mA
Supply Current Side 2 IDD2 2.4 3.5 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.5 6.2 mA
Supply Current Side 2 IDD2 3.4 4.6 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 5.8 7.5 mA
Supply Current Side 2 IDD2 6.3 8.8 mA CL = 0 nF
ADuM341E
1 Mbps

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 4. Total Supply Current vs. Data Throughput (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions
Supply Current Side 1 IDD1 3.7 4.9 mA CL = 0 nF
Supply Current Side 2 IDD2 2.7 3.9 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.3 5.4 mA CL = 0 nF
Supply Current Side 2 IDD2 3.5 4.9 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 6.2 7.5 mA CL = 0 nF
Supply Current Side 2 IDD2 6.1 8.4 mA CL = 0 nF
ADuM342E
1 Mbps
Supply Current Side 1 IDD1 3.1 4.7 mA CL = 0 nF
Supply Current Side 2 IDD2 3.2 4.7 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 3.7 5.4 mA CL = 0 nF
Supply Current Side 2 IDD2 3.8 5.4 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 6.0 8.5 mA CL = 0 nF
Supply Current Side 2 IDD2 5.9 8.1 mA CL = 0 nF

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended operation
range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with
CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty-cycle signals.
Table 5. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 10 ns Within PWD limit
Data Rate 100 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.1 7.2 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.3 4.5 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.8 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.4 5.0 ns
Opposing Direction tPSKOD 0.4 5.0 ns
Jitter1 See the Jitter Measurement section
Random Jitter, RMS (1σ)2 tJIT(RJ) 8.58 ps 1 MHz clock input
Deterministic Jitter, Peak to Peak3, 4 tJIT(DJ) 222 ps 100 Mbps, 215 − 1 PRBS
Total Jitter, Peak to Peak, at Bit Error Rate tJIT(TJ) 100 Mbps, 215 − 1 PRBS5
(BER) 1 × 10−12
Without Crosstalk 295 ps Single channel switching
With Crosstalk 450 ps All channels switching
Output Enabled to High-Z tPHZ, tPLZ 6 20 ns Output high/low to high impedance
Output High-Z to Enabled tPZH, tPZL 6 20 ns Output high impedance to high/low
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VHYS 0.65 V VIH − VIL
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx6 = −20 µA, VIx = VIxH7
VDDx − 0.4 VDDx − 0.2 V IOx6 = −2 mA, VIx = VIxH7
Logic Low VOL 0.0 0.1 V IOx6 = 20 µA, VIx = VIxL8
0.2 0.4 V IOx6 = 2 mA, VIx = VIxL8
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx, VEx ≤ VIL
Quiescent Supply Current
ADuM340E
IDD1 (Q) 0.6 0.82 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.4 2.2 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 7.6 10.4 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 3.2 4.8 mA VI9 = 1 (E0), 0 (E1)10
ADuM341E
IDD1 (Q) 0.8 1.3 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.2 2.0 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 6.6 8.9 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 4.1 5.9 mA VI9 = 1 (E0), 0 (E1)10

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 5. Electrical Characteristics (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions/Comments
ADuM342E
IDD1 (Q) 1.0 1.6 mA VI9 = 0 (E0), 1 (E1)10
IDD2 (Q) 1.0 1.6 mA VI9 = 0 (E0), 1 (E1)10
IDD1 (Q) 5.1 8.1 mA VI9 = 1 (E0), 0 (E1)10
IDD2 (Q) 5.2 7.6 mA VI9 = 1 (E0), 0 (E1)10
Dynamic Supply Current
Dynamic Input IDDI (D) 0.004 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.008 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout
Positive VDDx Threshold VUVLO+ 2.0 2.2 V Rising supply voltage enable threshold
Negative VDDx Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold
VDDx Hysteresis VUVLO_HYS 0.2 V UVLO hysteresis
UVLO Release Time11 tUVLO 60 μs UVLO release delay after VUVLO+ threshold
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity11, 12 |CMH| 100 180 kV/µs VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
|CML| 100 180 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude
= 800 V
1 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
2 This specification is measured over a population of ~100,000 edges.
3 Peak-to-peak jitter specifications include jitter due to PWD.
4 This specification is measured over a population of ~300,000 edges.
5 Using the following formula: tJIT(TJ) = 14 × tJIT(RJ) + tJIT(DJ).
6 IOx is the Channel x output current, where x = A, B, C, or D.
7 VIxH is the input side logic high.
8 VIxL is the input side logic low.
9 VI is the voltage input.
10 E0 refers to ADuM340E0/ADuM341E0/ADuM342E0 models, and E1 refers to ADuM340E1/ADuM341E1/ADuM342E1 models. See the Ordering Guide section.
11 Guaranteed by design and not subject to production test.
12 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode
voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 6. Total Supply Current vs. Data Throughput
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
ADuM340E
1 Mbps
Supply Current Side 1 IDD1 4.0 5.9 mA
Supply Current Side 2 IDD2 2.4 3.5 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.5 6.1 mA
Supply Current Side 2 IDD2 3.1 4.3 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 5.6 7.3 mA
Supply Current Side 2 IDD2 5.4 7.4 mA CL = 0 nF
ADuM341E
1 Mbps

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 6. Total Supply Current vs. Data Throughput (Continued)

Parameter Symbol Min Typ Max Unit Test Conditions
Supply Current Side 1 IDD1 3.7 4.9 mA CL = 0 nF
Supply Current Side 2 IDD2 2.7 3.9 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 4.2 5.6 mA CL = 0 nF
Supply Current Side 2 IDD2 3.3 4.9 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 5.8 7.6 mA CL = 0 nF
Supply Current Side 2 IDD2 5.4 8.4 mA CL = 0 nF
ADuM342E
1 Mbps
Supply Current Side 1 IDD1 3.1 4.7 mA CL = 0 nF
Supply Current Side 2 IDD2 3.2 4.7 mA CL = 0 nF
25 Mbps
Supply Current Side 1 IDD1 3.6 5.3 mA CL = 0 nF
Supply Current Side 2 IDD2 3.7 5.3 mA CL = 0 nF
100 Mbps
Supply Current Side 1 IDD1 5.4 7.5 mA CL = 0 nF
Supply Current Side 2 IDD2 5.5 7.5 mA CL = 0 nF

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.
Table 7. RW-16 Wide-Body [SOIC_W] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 5700 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 7.8 mm Measured from input terminals to output terminals, shortest distance
through air
Minimum External Tracking (Creepage) L (I02) 7.8 mm Measured from input terminals to output terminals, shortest distance
path along body
Minimum Clearance in the Plane of the Printed Circuit Board L (PCB) 8.1 mm Measured from input terminals to output terminals, shortest distance
(PCB Clearance) through air, line of sight, in the PCB mounting plane
Distance through insulation DTI 34 μm Minimum internal clearance
Tracking Resistance (Comparative Tracking Index) CTI >600 V Tested in accordance to IEC 60112
Material Group I Material Group per IEC 60664-1

PACKAGE CHARACTERISTICS
Table 8. RW-16 Wide-Body [SOIC_W] Package
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Insulation Resistance1 RI-O 1013 Ω Input to output voltage (VI-O) = 500 V DC
Insulation Capacitance1 CI-O 0.85 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Ambient Thermal Resistance θJA 65 °C/W Simulated per JEDEC JESD-51
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to the respective ground.

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

REGULATORY INFORMATION
See Table 13 for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Certifications available at Safety and Regulatory Certification for Digital Isolation.
Table 9. RW-16 Wide-Body [SOIC_W] Package
Regulatory Agency Standard Certification/Approval File
UL Recognized under 1577 component recognition program E214100 Volume 1, Section 21
Single protection, 5700 V rms1 isolation voltage
VDE (Pending) Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 Pending
Reinforced insulation, VIORM = 1173 V peak2, VIOSM = 10,000 V peak
CSA3 (Pending) Approved under CSA component acceptance Pending
CSA 62368-1-19, EN 62368-1:2020, and IEC 62368-1:2018 third edition:
Basic insulation at 780 V rms
Reinforced insulation at 390 V rms
IEC 60601-1 Edition 3.1, CSA 60601-1:14:
Basic insulation (1 means of patient protection (1 MOPP)), 490 V rms
CSA 61010-1-12 and IEC 61010-1 third edition:
Basic insulation at 300 V rms mains
Reinforced insulation at 600 V rms mains
TÜV Süd (Pending) Certified as component level device Pending
EN 62368-1: 2020+A11:2020
CQC (Pending) Certified by CQC11-471543-2012, GB4943.1-2022 Pending
Basic insulation at 760 V rms (1075 V peak)
Reinforced insulation at 380 V rms (537 V peak), tropical climate, altitude ≤5000 meters
1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥6840 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-11, each product is proof tested by applying an insulation test voltage ≥ 2199 V peak for 1 sec (partial discharge detection limit = 5
pC).
3 Working voltages are quoted for Pollution Degree 2, Material Group III.

DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS (PENDING)

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the
safety data. The asterisk (*) marking on packages denotes DIN V VDE V 0884-11 approval (pending).
Table 10. DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending)
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 1173 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, Vpd (m) 2199 V peak
partial discharge < 5 pC
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge 1759 V peak
< 5 pC
After Input and/or Safety Test Subgroup 2 and VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge 1407 V peak
Subgroup 3 < 5 pC
Highest Allowable Overvoltage VIOTM 8000 V peak

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Data Sheet ADuM340E/ADuM341E/ADuM342E
SPECIFICATIONS

Table 10. DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics (Pending) (Continued)
Description Test Conditions/Comments Symbol Characteristic Unit
Surge Isolation Voltage Reinforced VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 10000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 4)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C PS 1.92 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-11

RECOMMENDED OPERATING CONDITIONS

Table 11. Recommended Operating Conditions
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages
VDD1 2.25 V to 5.5 V
VDD2 2.25 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms

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Data Sheet ADuM340E/ADuM341E/ADuM342E
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Table 13. Maximum Continuous Working Voltage, RW-16 Wide-Body
[SOIC_W] Package (Continued)
Table 12. Absolute Maximum Ratings
Parameter Rating1 Constraint
Parameter Rating
Reinforced Insulation 779 V DC Rating limited by package creepage
Supply Voltages per IEC 60664-1:2020 in Pollution
VDD1 to GND1 −0.5 V to +7.0 V Degree 2 environment.
VDD2 to GND2 −0.5 V to +7.0 V 1 Maximum continuous working voltage refers to the continuous voltage magni-
Input Voltages (VIA, VIB, VIC, VID, VE1, VE2)1 −0.5 V to VDDI + 0.5 V
tude imposed across the isolation barrier in a Pollution Degree 2 environment.
Output Voltages (VOA, VOB, VOC, VOD)2 −0.5 V to VDDO + 0.5 V
See the Insulation Lifetime section for more details.
Average Output Current per Pin3
Side 1 Output Current (IO1) −10 mA to +10 mA ELECTROSTATIC DISCHARGE (ESD) RATINGS
Side 2 Output Current (IO2) −10 mA to +10 mA
The following ESD information is provided for handling of ESD-sen-
Common-Mode Transients4 −300 kV/μs to +300 kV/μs sitive devices in an ESD protected area only.
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature (TA) Range −40°C to +125°C Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Moisture Sensitivity Level MSL3 Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
1 VDDI is the input side supply voltage. International Electrotechnical Commission (IEC) electromagnetic
2 VDDO is the output side supply voltage. compatibility: Part 4-2 (IEC) per IEC 61000-4-2.
3 See Figure 4 for the maximum rated current values for various ambient
temperatures. ESD Ratings for ADuM340E/ADuM341E/
4 Refers to the common-mode transients across the insulation barrier. Common- ADuM342E
mode transients exceeding the absolute maximum ratings may cause latchup
Table 14. ADuM340E/ADuM341E/ADuM342E, 16-Lead SOIC_W
or permanent damage.
ESD Model Withstand Threshold (V) Class
Stresses at or above those listed under Absolute Maximum Ratings HBM1 ±5000 3A
may cause permanent damage to the product. This is a stress CDM1 ±1250 C3
rating only; functional operation of the product at these or any other IEC2 ±8000 Level 4
conditions above those indicated in the operational section of this
1 With respect to local VDDx and GNDx pins.
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability. 2 Across the isolation barrier between GND1 and GND2.
Table 13. Maximum Continuous Working Voltage, RW-16 Wide-Body ESD CAUTION
[SOIC_W] Package
ESD (electrostatic discharge) sensitive device. Charged devi-
Parameter Rating1 Constraint
ces and circuit boards can discharge without detection. Although
AC Voltage this product features patented or proprietary protection circuitry,
Bipolar Waveform damage may occur on devices subjected to high energy ESD.
Basic Insulation 1000 V rms Basic insulation rating per Therefore, proper ESD precautions should be taken to avoid
IEC60747-17. Accumulative failure performance degradation or loss of functionality.
rate over lifetime (FROL) ≤ 1000
ppm at 20 years.
Reinforced Insulation 779 V rms Rating limited by package creepage
per IEC 60664-1:2020 in Pollution
Degree 2 environment.
DC Voltage
Basic Insulation 1414 V DC Basic insulation rating per
IEC60747-17. Accumulative failure
rate over lifetime (FROL) ≤ 1000
ppm at 20 years.

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Data Sheet ADuM340E/ADuM341E/ADuM342E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM340E Pin Configuration

Table 15. ADuM340E Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1. This pin requires a 0.1 µF bypass capacitor.
2, 8 GND1 Ground Reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 NIC No Internal Connection. Leave this pin floating.
9, 15 GND2 Ground Reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB, VOC, and VOD outputs are enabled.
When VE2 is low, the VOA, VOB, VOC, and VOD outputs are disabled to the high-Z state.
11 VOD Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2. This pin requires a 0.1 µF bypass capacitor.

Figure 6. ADuM341E Pin Configuration

Table 16. ADuM341E Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1. This pin requires a 0.1 µF bypass capacitor.
2, 8 GND1 Ground Reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. When VE1 is high or disconnected, the VOD output is enabled. When VE1 is low, the VOD
output is disabled to the high-Z state.
9, 15 GND2 Ground Reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB, and VOC outputs are enabled. When VE2
is low, the VOA, VOB, and VOC outputs are disabled to the high-Z state.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.

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Data Sheet ADuM340E/ADuM341E/ADuM342E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Table 16. ADuM341E Pin Function Descriptions (Continued)

Pin No. Mnemonic Description
16 VDD2 Supply Voltage for Isolator Side 2. This pin requires a 0.1 µF bypass capacitor.

Figure 7. ADuM342E Pin Configuration

Table 17. ADuM342E Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1. This pin requires a 0.1 µF bypass capacitor.
2, 8 GND1 Ground Reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. When VE1 is high or disconnected, the VOD output is enabled. When VE1 is low, the VOD
output is disabled to the high-Z state.
9, 15 GND2 Ground Reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB, and VOC outputs are enabled. When VE2
is low, the VOA, VOB, and VOC outputs are disabled to the high-Z state.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2. This pin requires a 0.1 µF bypass capacitor.

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Data Sheet ADuM340E/ADuM341E/ADuM342E
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. ADuM340E IDD1 Supply Current vs. Data Rate at Various Voltages Figure 11. ADuM341E IDD2 Supply Current vs. Data Rate at Various Voltages

Figure 9. ADuM340E IDD2 Supply Current vs. Data Rate at Various Voltages Figure 12. ADuM342E IDD1 Supply Current vs. Data Rate at Various Voltages

Figure 10. ADuM341E IDD1 Supply Current vs. Data Rate at Various Voltages Figure 13. ADuM342E IDD2 Supply Current vs. Data Rate at Various Voltages

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Data Sheet ADuM340E/ADuM341E/ADuM342E
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 14. Propagation Delay, tPLH, tPHL vs. Temperature at Various Voltages Figure 15. Pulse Width Distortion, tPWD vs. Temperature at Various Voltages

analog.com Rev. A | 19 of 25
Data Sheet ADuM340E/ADuM341E/ADuM342E
THEORY OF OPERATION

The ADuM340E/ADuM341E/ADuM342E use a high frequency car- Figure 16 illustrates the waveforms for models of the AD-
rier to transmit data across the isolation barrier via iCoupler chip uM340E/ADuM341E/ADuM342E that have the condition of the
scale transformer coils separated by layers of polyimide isolation. fail-safe output state equal to low, where the carrier waveform
Using an on/off keying (OOK) technique and the differential ar- is off when the input state is low. If the input side is off or not
chitecture shown in Figure 16 and Figure 17, the ADuM340E/AD- operating, the low fail-safe output state (ADuM340E0/ ADuM341E0/
uM341E/ADuM342E have very low propagation delay and high ADuM342E0) sets the output to low. For the ADuM340E/AD-
speed. uM341E/ADuM342E that have a high fail-safe output state, Figure
17 illustrates the conditions where the carrier waveform is off
There is no interdependency between the VDD1 and VDD2 supplies. when the input state is high. When the input side is off or not op-
They can simultaneously operate at any voltage within their speci- erating, the high fail-safe output state (ADuM340E1/ ADuM341E1/
fied operating ranges and can sequence in any order. This feature ADuM342E1) sets the output to high. See Figure 26 for the model
enables the isolator to perform voltage translation of 2.5 V, 3.3 V, numbers that have the fail-safe output state of low or the fail-safe
and 5 V logic. The architecture is designed for high common-mode output state of high.
transient (CMTI) immunity and high immunity to electrical noise and
magnetic interference. Radiated emissions are minimized with a
spread spectrum OOK carrier and other techniques.

Figure 16. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State

Figure 17. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State

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Data Sheet ADuM340E/ADuM341E/ADuM342E
THEORY OF OPERATION

TRUTH TABLE
Table 18. ADuM340E/ADuM341E/ADuM342E Truth Table (Positive Logic)
Default Low (E0), VOx Default High (E1), VOx
VIx Input1, 2 VEx Input1, 2 VDDI State2 VDDO State2 Output1, 2, 3 Output1, 2, 3 Test Conditions/ Comments
L H or NC Powered Powered L L Normal operation
H H or NC Powered Powered H H Normal operation
X L Powered Powered Z Z Outputs disabled
L H or NC Undervoltage Powered L H Fail-safe output
X4 L4 Undervoltage Powered Z Z Outputs disabled
X4 X4 Powered Undervoltage Indeterminate Indeterminate

1 L means low, H means high, X means don’t care, NC means not connected, and Z means high impedance within one diode drop of GNDx.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
3 E0 refers to ADuM340E0/ADuM341E0/ADuM342E0 models, and E1 refers to ADuM340E1/ADuM341E1/ADuM342E1 models. See the Ordering Guide section.
4 Input pins (VIx, VEx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.

I/O Schematics

Figure 18. VIA, VIB, VIC, VID Input Schematics

Figure 20. VOA, VOB, VOC, VOD Output Schematics

Figure 19. VE1, VE2 Input Schematics

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Data Sheet ADuM340E/ADuM341E/ADuM342E
APPLICATIONS INFORMATION

PCB LAYOUT JITTER MEASUREMENT

The ADuM340E/ADuM341E/ADuM342E digital isolators require no Figure 23 shows the resulting eye diagram for the ADuM341E.
external interface circuitry for the logic interfaces. Power supply The measurement was taken using a Keysight 81160A pulse pat-
bypassing is strongly recommended at the input and output supply tern generator at 100 Mbps with a pseudorandom bit sequence
pins (see Figure 21). Bypass capacitors are to be connected be- (PRBS15) input. Jitter was measured using the Tektronix 6 Series
tween Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for B mixed-signal oscilloscope, with a TAP1500 probe and using the
VDD2. The required bypass capacitor value is between 0.01 µF and Tektronix jitter and analysis software. The 10% to 90% rise and fall
0.1 µF. The total lead length between both ends of the capacitor times of the input signal from the generator approximately equals
and the input power supply pin must not exceed 10 mm. Low ESR 1.2 ns. The result shows a typical output eye diagram measured
capacitors are important for direct power injection (DPI) and CMTI on the ADuM341E. Figure 23 shows random and deterministic jitter
performance. Bypassing between Pin 1 and Pin 8 and between Pin characteristics for a PRBS input.
9 and Pin 16 must also be considered, unless the ground pair on
each package side is connected close to the package. Total Jitter is evaluated at a BER of 1 × 10−12 and calculated
for a PRBS input with and without the effects of crosstalk. The
total jitter measurement without crosstalk consists of examining one
channels input, while the adjacent channels inputs are grounded.
The jitter measurement with crosstalk consists of all channels
switching simultaneously at the same rate.

Figure 21. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, ensure that

board coupling across the isolation barrier is minimized. Further-
more, design the board layout such that any coupling that does
occur equally affects all pins on a given component side. Failure
to ensure this design can cause voltage differentials between pins
exceeding the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage (see Table 12).
PROPAGATION DELAY RELATED
PARAMETERS
Propagation delay is a parameter that describes the time required Figure 23. ADuM341E Output Channel Eye Diagram (VDD1 = VDD2 = 3.3 V, 100
for a logic signal to propagate through a component. The propaga- Mbps, TA = 25°C, CL = 15 pF, PRBS15 Input
tion delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output. INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
and material interfaces.
Figure 22. Propagation Delay Parameters
The two types of insulation degradation of primary interest are
Pulse width distortion is the maximum difference between these two breakdown along surfaces exposed to the air and insulation wear
propagation delay values and is an indication of how accurately the out. Surface breakdown is the phenomenon of surface tracking,
timing of the input signal is preserved. and the primary determinant of surface creepage requirements in
system level standards. Insulation wear out is the phenomenon
Channel matching is the maximum amount the propagation where charge injection or displacement currents inside the insula-
delay differs between channels within a single ADuM340E/AD- tion material cause long-term insulation degradation.
uM341E/ADuM342E component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM340E/ADuM341E/ADuM342E
components operating under the same conditions.
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Data Sheet ADuM340E/ADuM341E/ADuM342E
APPLICATIONS INFORMATION

Surface Tracking Calculation and Use of Parameters Example

Surface tracking is addressed in electrical safety standards by set- The following example frequently arises in power-conversion appli-
ting a minimum surface creepage based on the working voltage, the cations. Assume that the line voltage on one side of the isolation
environmental conditions, and the properties of the insulation mate- is 240 V AC rms and a 400 V DC bus voltage is present on the
rial. Safety agencies perform characterization testing on the surface other side of the isolation barrier. The isolator material is polyimide.
insulation of components that allows the components to be cate- To establish the critical voltages in determining the creepage, clear-
gorized in different material groups. Lower material group ratings ance, and lifetime of a device, see Figure 24 and the following
are more resistant to surface tracking and, therefore, can provide equations.
adequate lifetime with smaller creepage. The minimum creepage
for a given working voltage and material group is in each system
level standard and is based on the total RMS voltage across the
isolation, pollution degree, and material group. The material group
and creepage for the ADuM340E/ADuM341E/ADuM342E isolators
are presented in Table 7.

Insulation Wear Out

The lifetime of insulation caused by wear out is determined by its
thickness, material properties, and the voltage stress applied. It
is important to verify that the product lifetime is adequate at the
application working voltage. The working voltage supported by an Figure 24. Critical Voltage Example
isolator for wear out may not be the same as the working voltage
supported for tracking. The working voltage applicable to tracking is The working voltage across the barrier from Equation 1 is
specified in most standards.
VRMS = VAC RMS2 + VDC2
Testing and modeling have shown that the primary driver of long-
term degradation is displacement current in the polyimide insulation VRMS = 2402 + 4002 (3)
causing incremental damage. The stress on the insulation can be VRMS = 466 V
broken down into broad categories, such as DC stress, which caus-
es very little wear out because there is no displacement current, This VRMS value is the working voltage used together with the
and an AC component time varying voltage stress, which causes material group and pollution degree when looking up the creepage
wear out. required by a system standard.

The ratings in certification documents are usually based on 60 Hz To determine if the lifetime is adequate, obtain the time varying
sinusoidal stress because this reflects isolation from line voltage. portion of the working voltage. To obtain the AC RMS voltage, use
However, many practical applications have combinations of 60 Hz Equation 2.
AC and DC across the barrier as shown in Equation 1. Because VAC RMS = VRMS2 − VDC2
only the AC portion of the stress causes wear out, the equation
can be rearranged to solve for the AC RMS voltage, as is shown VAC RMS = 4662 − 4002 (4)
in Equation 2. For insulation wear out with the polyimide materials VAC RMS = 240 V rms
used in these products, the AC RMS voltage determines the prod-
uct lifetime. In this case, the AC RMS voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform
VRMS = VAC RMS2 + VDC2 (1) is not sinusoidal. The value is compared to the limits for working
voltage in Table 13 for the expected lifetime, less than a 60 Hz sine
or wave, and it is well within the limit for a 50-year service life.
VAC RMS = VRMS2 − VDC2 (2) Note that the DC working voltage limit in Table 13 is set by the
creepage of the package as specified in IEC 60664-1. This value
where: can differ for specific system level standards.
VRMS is the total RMS working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the DC offset of the working voltage.

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Data Sheet ADuM340E/ADuM341E/ADuM342E
OUTLINE DIMENSIONS

10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

Figure 26. Product Selector Guide

Updated: July 26, 2023

ORDERING GUIDE
Table 19. Ordering Guide
Package
Model1, 2 Temperature Range Package Description Packing Quantity Option
ADUM340E0BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM340E0BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM340E0WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM340E0WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM340E1BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM340E1BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM340E1WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM340E1WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM341E0BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM341E0BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM341E0WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM341E0WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM341E1BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM341E1BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM341E1WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM341E1WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM342E0BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM342E0BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM342E0WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM342E0WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16

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Data Sheet ADuM340E/ADuM341E/ADuM342E
OUTLINE DIMENSIONS

Table 19. Ordering Guide (Continued)

Package
Model1, 2 Temperature Range Package Description Packing Quantity Option
ADUM342E1BRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM342E1BRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
ADUM342E1WBRWZ -40°C to +125°C 16-Lead SOIC Wide RW-16
ADUM342E1WBRWZ-RL -40°C to +125°C 16-Lead SOIC Wide Reel, 1000 RW-16
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.

EVALUATION BOARDS
Model1 Description
EVAL-ADuM34XEEBZ Evaluation Board for the ADuM340E, ADuM341E, and ADuM342E
1 Z = RoHS Compliant Part.

AUTOMOTIVE PRODUCTS
The ADuM340E0W/ADuM340E1W/ADuM341E0W/ADuM341E1W/ADuM342E0W/ ADuM342E1W models are available with controlled manu-
facturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have
specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully.
Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account
representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

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