Introduction to ASICs

ni logic Pvt. Ltd., Pune

 The Wonderful World of Silicon

About every two years, the number of transistors on a CMOS silicon chip doubles
and the clock speed doubles ..This rate of improvement will continue for the
next 20 years.

Technology Drivers:
Decreasing lithographic feature size, typically measured by the transistor gate
length:
0.35 m . 0.25 m . 0.18 m 0.15 m etc.... 0.050 m (?)
Increasing wafer size:
6 inch diameter .. 8 inch diameter ..etc .. 12 inches (?)
Increasing number of metal interconnect layers:
4 .. 6 .. 8 9 (?)

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 The Wonderful World of Silicon

With the advent of VLSI in the 1980s engineers began to realize the advantages
of designing an IC that was customized or tailored to a particular system or
application rather than using standard ICs alone.

This design paradigm shift was due to advancement in semi-conductor

technology to satisfy the increasing complexity and performance needs of the
applications.

Building a microelectronic system with fewer ICs allows you to reduce cost and
improve reliability.

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 Agenda

An Introduction
ASIC Cell Library
Types of ASICs and their comparison.
Applications of ASICs
ASIC Design Flow and Approach
ASIC Vs FPGA
ASIC Design Issues and Verification
Backend Design and Issues
FPGA to ASIC Conversion
Packaging Technology
Current Trend and Conclusion

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 What are ASICs..?

ASICs are silicon chips that have been designed for a specific application. Putting
in other words, it is a chip designed to perform a particular operation as opposed to
general purpose integrated circuits:
An ASIC is NOT software programmable to perform different tasks.
ICs that are not ASICs are :
DRAM
SRAM
Silicon Die
74xx series ICs
ICs which are ASICs:
Baseband processor in mobile phone
Chipsets in PCs
MPEG encoders/ decoders
DSP functions in hardware, e.g. FFT

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 What Is In Them..?

These are made on a thin circular wafer, with each wafer holding hundreds of
dies.

Each wafer consists of many mask layers, built on top of one another.

Every mask layer corresponds to either a transistor

(semiconductor ) mask or the interconnect ( metal wires ).
The logic cells made up of transistors are fabricated on the semiconductor mask
and the metal mask is used for the interconnection between them.

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 WHY USE ASICs?

Design Requirements
Technology-driven:
Greater Complexity
Increased Performance
Higher Density
Lower Power Dissipation
Market-driven:
Shorter Time-to-Market (TTM)
Cheaper with the competition

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 ASIC Cell Library

Everybody has seen PCBs designed with the MSI or SSI discrete
components..? How do they make it..?
The PCB designer uses TTL, CMOS etc. component library for it.
The libraries contains standard components with their mechanical, electrical and
other specifications, which are fixed for the specific technology.
The basic design principles are the same for designing on silicon as for using
standard MSI or SSI parts on a PCB.

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 ASIC Cell Library
The cell library is the key part of ASIC design.
What is a Cell..?
An electronic functional unit normally defined in terms of its layout on silicon.
Similar to PCB components, ASIC vendors have libraries build of Core Cells of the
specific technology, viz 0.5 , 0.25 , or 0.18 .
Each cell in an ASIC cell library must contain the following:
A physical layout
A behavioral model
A Verilog/VHDL model
A detailed timing model
A test strategy
A circuit schematic
A cell icon
A wire-load model
A routing model

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 FARADAYs ASIC CELL LIBRARY
A standard cell library includes the primitive cell library, the I/O cell library, RAM/ROM
blocks, and Megacell functional blocks.
Primitive Cell Library
Consists of basic primitive gates like, AND, NAND,XOR, Half & Full Adder, decoders,
D F/Fs, Pull ups, Multiplexers, etc.
I/O Cell Library
Divided into many groups.
True 2.5V programmable I/O
True 3.3V programmable I/O
3.3V PCI I/O(66MHz)
Megacells
16-bit & 8-bit Micro Controller, MIPS R3000 compatible RISC, Programmable
Peripheral Interface, Direct Memory Access Controller, etc.

The FS9000A is a 0.25 m standard cell library from Faraday Inc.,USA 10

 Inverter Cell
Symbol Schematic

Group Name : INV

Function : Inverter
Pin Order O I
Truth Table

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 XOR Gate Cell
Schematic
Symbol
Group Name : XOR2
Function : Exclusive OR2
Truth Table

Pin Order O I1 I2

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 D- F/F Cell
Group name : QDFF Symbol
Function : D Flip-Flop, Single Output
Truth Table Schematic

Pin Order: Q D CK
Tsu = 0.37 ns
Th = 0.11 ns

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 Types of ASICs

ASICs are fabricated on a circular silicon wafer. The fabrication process remains
the same, but the architecture makes ASICs to be divided into types.
We will categorize the ASIC broadly in four types;
Full custom ASIC
Semi custom ASIC
Gate Array based ASIC
Programmable ASIC

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 Full Custom ASIC

When engineers have a specific application to be designed and they are

bothered about the performance, speed, power and cost, they go for designing
Full Custom ASIC.
The circuit is partitioned into a collection of sub-circuits according to some
criteria such as functionality. Which are laid out specifically for one chip.
Every transistor is designed and drawn by hand.
Typically only way to design analog portions of ASICs.
Usually used for layout of microprocessors.
Full-custom design is very time consuming; thus the method is inappropriate for
very large circuits, unless performance is of utmost importance

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 Full Custom ASIC

Actual 0.35? full-custom layout 16

 Semi Custom ASIC

A semi-custom ASIC, also known as a cell-basedASIC, uses pre-designed

logic cells (AND gates, OR gates, Multiplexers, Flip-flops etc.) known as
standard cells.
Simpler than full-custom design.
Only the placement of the standard cells and the interconnection is done in a
semi-custom ASIC. However, the standard cells can be placed anywhere on the
silicon die.
Possibly megacells , megafunctions , full-custom blocks , system-level macros(
SLMs ), fixed blocks , cores , or Functional Standard Blocks ( FSBs ). Eg.
Microprocessor, multiplier, etc.

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 Semi Custom ASIC

All mask layers are customized - transistors and interconnect

Automated buffer sizing, placement and routing
Custom blocks can be embedded
Manufacturing lead time is about eight weeks.

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 Gate-Array Based ASICs

In a gate-array-based ASIC, the transistors are predefined on the silicon wafer.

The predefined pattern of transistors is called the base array.
The smallest element that is replicated to make the base array is called the base or
primitive cell.
The top level interconnect between the transistors is defined by the designer in custom
masks - Masked Gate Array (MGA)
Design is performed by connecting predesigned and characterized logic cells from a
library (macros).
After validation, automatic placement and routing are typically used to convert the
macro-based design into a layout on the ASIC using primitive cells.
Types of MGAs:
Channeled Gate Array
Channelless Gate Array
Structured Gate Array

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 Gate-Array Based ASICs
Channeled Gate Array
Only the interconnect is customized.
The interconnect uses predefined spaces between rows
of base cells.
Manufacturing lead time is between two days and two
weeks.

Channel gate-array die

Channelless Gate Array

There are no predefined areas set aside for routing,
routing is over the top of the gate-array devices.
Achievable logic density is higher than for channeled
gate arrays.
Manufacturing lead time is between two days and two
weeks.
Sea-Of-Gates (SOG) array die

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 Gate-Array Based ASICs
Structured Gate Array
Only the interconnect is customized
Custom blocks (the same for each design) can be
embedded
These can be complete blocks such as a processor or
memory array, or
An array of different base cells better suited to
implementing a specific function
Manufacturing lead time is between two days and two Gate array die with embedded block
weeks.

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 Programmable ASICs
Programmable Logic Device (PLD) die
Programmable Logic Devices
No customized mask layers or logic cells
Fast design turnaround
A single large block of programmable interconnect
Erasable PLD (EPLD)
Mask-programmed PLD
A matrix of logic macrocells that usually consist of
programmable array logic followed by a flip-flop or latch.

Field-Programmable Gate Array (FPGA) die

Field Programmable Gate Array
None of the mask layers are customized
A method for programming the basic logic cells and the
interconnect.
The core is a regular array of programmable basic logic cells
that can implement combinational as well as sequential logic
(flip-flops).
A matrix of programmable interconnect surrounds the basic
logic cells.
Programmable I/O cells surround the core.
Design turnaround is a few hours.

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 Comparison of different design styles

Architectural Difference

STYLE
Full Standard cell Gate array FPGA
custom
Cell size Variable Fixed height Fixed Fixed

Cell type Variable Variable Fixed Programmable

Cell placement Variable In row Fixed Fixed

Interconnections Variable Variable Variable programmable

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Comparison of different design styles
Comparison of Area, Performance, and Fabrication layers

STYLE
Full Standard cell Gate array FPGA
custom

Area compact Compact to moderate large

moderate

Performance high High to moderate low

moderate

Fabrication layers all all Routing layer none

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 ASIC Applications

The application field for ASICs could, in theory, be considered endless. Here are
a few applications :
Aerospace subsystems and sensors
Wireless communication systems
Medical instrumentation
Telecommunications products
Consumer electronics, CDs, digital synthesizers, mini-discs
Computer products, graphics cards, MPEG technology.
Etc .

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