System-on-Chip Design:

Introduction

Dr. Syed Azhar Ali Zaidi

Assistant Professor
[email protected]

https://sites.google.com/site/cmsdrsyedazhar/home/s
oc-design

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 Application Specific Integrated Circuit
(IC)
• An Integrated Circuit (IC) or a Chip designed to
address a specific application.
• Not Software Programmable
• ASIC may be implemented as an FPGA (discuss
later).
• Examples of ASIC
– DSP functions in hardware e.g. FFT
– Video processor to decode or encode video standards
– Encryption processor for security
– Channel decoders of a communication system such as
WIFI or WIMAX etc.

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 ASIC
• Size of an IC is measured by the number of transistors
or the number of logic gates that the IC contains
– Gate equivalent corresponds to a two input NAND gate. A
100K gate IC contains equivalent of 100,000 two input
NAND gates
– Conversion between the gates and transistors is obtained
by multiplying the number of gates by 4
• The IC is also defined by the smallest feature size
(roughly half the length of the smallest transistor)
imprinted on IC, also termed as Fabrication process
technology. E.g. 10 μm or 65 nm etc.

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 Introduction to ASIC

• Introduced in 1971
• 2300 transistors
• 10 μm technology
• Run around 100 KHz

The First Integrated Microprocessor: 4004

 Introduction to ASIC
• Introduced in year 2000.
• 54 million transistors
• Runs at around 1.5 GHz
• 0.18 μm technology
• Currently the
microprocessors are
designed using 14nm or
less technology with over 1
Billion transistors
• E.g. Intel core i9 contains
approx. 7 billion transistors

Pentium 4 Micrograph
 Introduction to ASIC
• ICs are made on a thin
circular wafer holding
hundreds of die.
• Many mask layers (6, 8 or 9
etc) built on top of one
another.
– Some layers define the
transistors
– Some layers define the metal
wires between the transistors
(the interconnect)
• Mask is a pattern for each
layer.
 Types of ASICs
Full-Custom ASICs
• Some or all of the logic cells, circuits or layout
is designed for one ASIC.
• Every transistor is designed and drawn by
hand.
• To optimize speed, area or power.
• Usually microprocessors are full custom ICs.
• Most expensive to manufacture and longest
production time.
 Types of ASICs
Standard-Cell-Based ASICs
• Cell based IC (CBIC) or semicustom IC
• A CBIC is designed using predesigned and pre
characterized logic cells known as standard cells.
– Logic cells – AND, OR, multiplexers, flip flops etc.

D-Flip Flop NOR

 Standard-Cell-Based ASICs

• Possibly megacells, mega

functions or Functional standard
blocks perhaps microcontrollers
or even microprocessors
• The ASIC designer only defines
the placement of standard cells
and the interconnect in a CBIC.
• Standard cells can be placed any
where on silicon.
• Manufacturing lead time is
about eight weeks.
 Types of ASICs
Gate-Array-Based ASICs
• In gate-array transistor layers masks are fully
defined and user can not change them
• The designer only programs the interconnect
between the transistors to implement the
desired functionality
• RTL based methods and synthesis together
with other CAD tools are used for gate arrays.
 Programmable ASICs
Field Programmable
Gate Array (FPGA)
• ICs that are
programmed by the
user to implement a
design
• No custom mask
layers so the design
time is few hours
• High power
consumption
• Slower than ASIC
ASIC Design Flow

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 Moore’s Law
“About every eighteen months,
the number of transistors on a
CMOS silicon chip doubles and
the clock speed doubles”
– Transistors/Chip increasing by
50% per year (by 4X in 3.5
years)
– Gate Delay decreasing by 13%
per year (by ½ in 5 years)
Moore’s Law

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Why Scaling?

The virtuous circle of the semiconductor industry

 System-on-Chip (SoC)
• SoC or system on chip is the design approach of
integrating the components of an electronic
system into a single chip.

ARM cores

AMBA buses

Physical IPs

Mother board of a PC System on a Chip

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 System-on-Chip (SoC) Examples

Nvidia Tegra

Xilinx ZYNQ SoC 17

Qualcomm Snapdragon SoC

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 SoC Components
• Key to the SoC approach
– Integration
• A typical SoC chip has
– One or more microprocessors (Brain of SoC): for
controlling and coordinating operations inside chip
– Application specific custom logic functions
– Memory
– Possibly an array of Reconfigurable Logic
– Analog Circuitry: for managing sensors data, wireless
data transmission etc.
– Interconnects

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 SoC System Model
• E.g. A smart Phone
– ARM Cortex-A53 Core
Processor
– Media Processor such as
Mali-400 MP and Mali-VE
video engine
– System components and
custom circuitry for
interfacing peripherals
such as the camera, the
touch screen and the wire
less communication unit
– AXI interconnects/AMBA
Bus ARM/ Network on
Chip (NoC)
• SOC vs SOB A Basic SoC System Model
• Embedded Software

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 Hardware/Software Partitioning
• Programmability vs. performance
– Fundamental decision in SoC: which components of
the system are to be implemented in hardware and in
software.
– Software executed on a general purpose processor.
More flexibility but slower and more power hungry as
compared to the dedicated hardware for the same
function.
– Custom hardware built for the application has higher
performance and low power at the expense of
programmability, productivity and cost
– SoC design aims to combine the individual benefits of
the two.

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 Programmability vs. Performance
• Custom ASICs
and GPPs on
extreme with
various other
technologies
lie b/w the
two extremes

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SoC Complexity

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 Intellectual Property (IP) Cores –
Forms
• Essential Components of SoCs – Pre-designed and Pre-verified
Cores (or Macro, Blocks, IP)
– E.g. Many Embedded systems contain ARM microprocessor
core
• Flexibility of using the cores depends on the form in which it is
available
1. Soft Cores: available as HDL description ( as an RTL Synthesizable
code). The user is responsible for actual implementation
2. Firm Cores: available as synthesized code or as a netlist of generic
library elements. Optimized for performance, area and power.
3. Hard Cores: available as fully placed and route netlist and as a
fixed layout such as in GDSII format. Optimized for performance,
area and power and mapped to a specific process technology

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Trade-Off among Cores

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 Advantages of SoC
Higher performance benefiting from:
Less propagation delay since internal wires are shorter.
Less gate delay as internal transistors have lower electrical impedance.
Power efficiency benefiting from:
Lower voltage required (typically < 2.0 volts) compared with external chip
voltage (typically >3.0 volts).
Less capacitance.
Lighter footprint:
Device size and weight is reduced.
Higher reliability:
All encapsulated in a single chip package, less interference from the
external world.
Low cost:
The cost per unit is reduced since a single chip design can be fabricated in a
large volumes.
 Key Design Issues in SoC
• Which/How many Processors
• Partitioning functionality b/w CPU, DSP and
accelerators
• Hardwired vs. programmable accelerators
• How to interconnect the components
• Re-use Legacy/ Pre-designed components
– Portability issues, Aspect ratio misfit, layout
dependent, timing and synchronization,
verification and testing etc.

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 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 SoC Design Flow
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers

SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW
partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation

Physical optimization HW/ SW Application development

and fabrication co-verification and test

Foundries:
Volume manufacture Chip fabrication
and ship

Device vendors:
PCB manufacture
and device assembly Final products
 Programmable SoC
SoCs can be prototyped and tested on FPGAs.
Two options:
1.Use soft cores to embed a processor in the logic fabric (Soft Processor) and
use device interconnect resources to implement a bus which communicates with
other custom design blocks.
2.Use modern Programmable SoCs (e.g. Xilinx Zynq), which include hard
processors (e.g. ARM) connected to peripherals and to the logic fabric through a
bus (e.g. AXI bus).
Programmable SoCs (PSoCs) can overcome ASIC SoC limitations in some
application areas by providing:
Flexibility for upgrading and functionality modification.
Faster time-to-market for low to medium production volumes.
Architecture of a PSoC
Processing System (PS) Programmable Logic (PL)

Memory
Custom Custom
Periphe Periphe
ral ral
AXI
A B

AXI
Microproce
ssor
(ARM
Cortex-A9)

Custom Custom
AXI Peripher Peripher
al al
C X
Hard silicon
peripherals
 Example: Xilinx Zynq-7000
Dual core ARM-A9 processor.
On chip memory.
Memory interfaces.
Integrated peripherals: timers, USB, UART,
I2C, SPI...
AXI buses and AXI ports.
Programmable Logic.

Picture source:
http://www.xilinx.com/publications/prod_mktg/zynq-7000-
generation-ahead-backgrounder.pdf
 Suggested Readings
• Michael J. Sebastian, “Application Specific
Integrated Circuits”
• Michael J. Flynn and Wayne Luk, “Computer
System Design: System-on-Chip”
• Rochit Rajsuman, “System-on-a-chip: Design
and test”

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