Digital System Design

Lecture # 4
VERILOG HDL DESCRIPTION
ENGR. DR. MUHAMMAD AQEEL ASLAM
ASSISTANT PROFESSOR
SCHOOL OF ENGINEERING AND APPLIED SCIENCES
ELECTRICAL ENGINEERING DEPARTMENT
GIFT UNIVERSITY
GUJRANWALA
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Table of Contents

 Definition
 Integrated Circuits
 ASIC Design Flow
 Overview of ASIC Fabrication Process
 ASIC Packages
 HDL
 Verilog HDL
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Definition

 ASIC: Application Specific Integrated Circuit

 An IC designed for a specific application to perform a dedicated task
 e.g. an ASIC to do table lookups for routers
 e.g. an ASIC to process real-time data stream encryption

 As opposed to a general purpose IC

 e.g. general purpose micro-processors (intel x86)
 e.g. RAM
 e.g. ROM
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Common Terms

 Some commonly used terms

 HDL: Hardware Description Language (Verilog, VHDL etc)
 Netlist: HDL representation of a circuit in the form of gates (NAND, NOR etc)
 RTL: HDL representation of a circuit in the form of functions, procedures etc
 Layout: A drawing of the physical circuits…contains different layers for mask production
 Cell: Basic building blocks of an ASIC…a simple logic gate (NAND NOR etc) or more complex
functions (RAM adder etc)
 Die: a piece of silicon on which an IC is fabricated
 Wafer: A large round piece of silicon on which several dies are made
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ASIC: Advantages

 ASICs offer several benefits over general purpose Integrated Circuits

 Maybe the only way to implement a given design
 May include unique features that add value and differentiation from competing
products
 May replace a large number of standard IC’s and offer power, die size or board space
savings
 Performance – Frequency and speed of operation
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ASIC: Disadvantages

 ASICs have some disadvantages as well

 Cost of Design and Development
 Design to silicon cycle is very long
 Typically 6- to 8- weeks
 Design changes not easy
 Testing and debug difficult
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Overview of ASIC Design Flow
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Types of Digital Integrated Circuits
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Types of ICs: Full Custom

 Full Custom : Circuit elements of the design are individually drawn and
Circuit elements of the design are individually drawn and positioned in the
layout.
 Transistors, resistors, capacitors and element interconnects
 Requires high skill and is process specific!
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Types of ICs: Cell-based

 Cell-based: Layout uses predefined circuit elements called “cells”

 Available in cell libraries
 Interconnects between cells are made as specified by the netlist
 Process is known as routing
 Permit integration of macros or 3rd party cores
 Microprocessors and peripheral controllers, RAM, ROM,
 Mixed digital/analog functions and complex datapath elements
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What is an FPGA?
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Types of ICs (contd.)

 FPGA : Field Programmable Gate Array

 Array of logic blocks embedded in a matrix of programmable
interconnect lines
 Each logic block consists of flip-flops and combinational logic that can be
configured via user programming
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Two competing implementation
approaches

ASIC: Application Specific FPGA: Field Programmable Gate

Integrated Circuit Array
designed all the way from No physical design layout, design
behavioral description to physical ends with a bitstream used to
layout configure a device
designs must be sent for expensive bought off the shelf and
and time consuming fabrication in reconfigured by designers
semiconductor foundry themselves
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FPGAs vs. ASICs

ASICs FPGAs
High performance Low development cost
Low power Short time to market
Low cost (but only in high volumes) Reconfigurability
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Overview of ASIC Design Flow (contd.)

 Functional Specification: Document describing the features behavior of design

 Algorithmic description flow charts, block diagrams, C/C++, SPW(Cadence Signal
Processing Worksystem), Matlab
 Emphasis on design of functions, algorithms and interfaces
 Underlying hardware implementation not fixed at this stage
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Overview of ASIC Design Flow (contd.)

 Logic Design
 RTL (Register Transfer Level) description
 Hardware description language Verilog, VHDL
 Focus on actual implementation (data flow) of the design using logic elements (busses,
registers, FSM, data paths, RAM’s)
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Overview of ASIC Design Flow (contd.)

 Logic Implementation:
 RTL description is synthesized using automatic synthesis tools
 E.g. Synopsys Design Compiler
 The result is a gate-level netlist
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Overview of ASIC Design Flow (contd.)

 Physical Design: The gate The gate-level netlist is used to

level netlist is used to layout the ASIC
 An automatic P&R tool is used
 The tool reads the netlist
 Places the cells
 Routes the interconnects As described by the netlist
 Outputs a layout map of the entire chip
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ASIC Fabrication Process

 Tools read in the layout map of the chip

 Circuits to be formed on the ASIC are drawn on a
mask as a pattern
 Light is projected on silicon wafer through the
mask to transfer the pattern on the die
 Various electrical/chemical processes are used to
convert these patterns into desired features
 Series of masks are used to form transistors and
interconnects
 The process of forming features on silicon using
light is called Photolithography
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ASIC Fabrication Process (Contd.)

 Each layer is made using its

associated mask
 Transistors are formed using
series of layers of polygate, P
– Diffusion, N- Diffusion
 Interconnects are formed
using another series of layers
 Many ASIC’s can be layed
out
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ASIC Packages

 Several types of packages for various applications

 Dual-inline (DIP):
 Cheap, old technology, obsolete
 Poor electric characteristics, low (pin) density

 PLCC: (Plastic Leaded Chip Carrier)

 Cheap, better density than DIP, obsolete

 QFP: (Quad Flat Package)

 Cheap, high density
 moderate thermal/electrical characteristics
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ASIC Packages (contd.)

 BGA: (Ball Grid Array)

 Relatively expensive, very high density
 Very good thermal/electrical characteristics,
 Very common in ASIC
 MCM:
 Multi Chip Module, a type of BGA where several die’s are housed in the same package
 Very good characteristics, very high density, very high speed, Very expensive, modern technology
 Flip Chip BGA
 A more sophisticated form of BGA which allows 23 A more sophisticated form of BGA which allows
even greater pin density
 New technology, expensive. With time, all high end ASIC’s will move to such packages
 Introduction to
Hardware Description
Language (HDL)
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What is HDL

 In electronics, a hardware description language or HDL is any language

from a class of computer languages for formal description of electronic
circuits.
 The two most widely-used and well-supported HDL varieties used in industry
are:
 VHDL (VHSIC hardware description language)
 Verilog is a hardware description language (HDL) used to model electronic
systems. The language (sometimes called Verilog HDL) supports the design,
verification, and implementation of analog, digital, and mixed-signal circuits at
various levels of abstraction
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Verilog-I

 Verilog is a hardware description language (HDL)

 Verilog is used by several companies in the commercial chip design and manufacturing
sector today and manufacturing sector today. It is rapidly overtaking the rival HDL It is
rapidly overtaking the rival HDL called VHDL
 Verilog allows a designer to develop a complex hardware system, e.g., a VLSI chip
containing millions of transistors, by defining it at various levels of abstraction
 at the (highest) behavioral, or algorithmic, level the design consists of C like procedures that
express functionality without regard to implementation
 at the dataflow level the design consist of specifying how data is processed and moved
between registers
 at the gate level the structure is defined as an interconnection of logic gates
 at the (lowest) switch level the structure is an interconnection of transistors
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Verilog-II

 Verilog allows the designer to simulate and verify the design at each level
 EDA (electronic design automation electronic design automation) tools help the designer to
move ) tools help the designer to move from higher to lower levels of abstraction
 Behavioral synthesis tools create dataflow descriptions from a behavioral description
 Logic synthesis tools convert an RTL description to a switch level interconnection of transistors, which
is input to an automatic place and route tool that creates the chip layout
 With Verilog and EDA tools one could sit at a computer at home, design a complex chip,
email the design to a silicon foundry in California and receive the fabricated chip through
regular mail in a 28 California, and receive the fabricated chip through regular mail in a few
weeks!
 The Verilog environment is that of a programming language. Designers, particularly with C
programming experience, find it easy to learn and work with
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Comparison

VHDL Verilog
Government Developed Commercially Developed
Ada based C based
Strongly Type Cast Mildly Type Cast
Case-insensitive Case-sensitive
Difficult to learn Easier to Learn
More Powerful Less Powerfu
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Learning Verilog

 Verilog is essentially a programming language – similar to C with some Pascal-like constructs

 The best way to learn any programming language is from live code
 We will get you started by going through several example programs and explaining the key
concepts
 We will not try to teach you the syntax line-by-line: pick up what you need from the books
and on-line tutorials
 Tip: Start by copying existing programs and modifying them incrementally making sure you
understand the output behavior at each step
 Tip: The best way to understand and remember a construct or 30 : The best way to
understand and remember a construct or keyword is to experiment with it in code, not by
reading about it
 We shall not design at the switch (transistor) level in this course – the lowest level we shall
reach is the gate level. The transistor level is more appropriate for an electronics-oriented
course
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Overview

 Simulation and Synthesis

 Modules and Primitives
 Styles
 Structural Descriptions
 Language Conventions
 Data Types
 Delay
 Behavioral Constructs
 Compiler Directives
 Simulation and Testbenches
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Simulation and Synthesis

 Simulation tools typically accept full set of Verilog language constructs

 Some language constructs and their use in a Verilog description make simulation
efficient and are ignored by synthesis tools
 Synthesis tools typically accept only a subset of the full Verilog language constructs
 In this lecture, Verilog language constructs not supported in Xilinx ISE are in red italics
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Modules

 Modules are basic building blocks of Verilog

 Description of the logic being modeled is placed inside modules
 Module definition starts with keyword module
 Ends with the keyword endmodule
 Module declarations cant be nested
 Modules are
 Declared
 Instantiated
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Module Example
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Module Ports

 Modules communicate with the outside world through ports

 Module port are similar to pins in hardware
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Port Types

 Inputs
 Inputs are values being provided to the module
 Outputs
 Outputs are values being driven by the module
 Inouts
 Ports that act as input and output ports
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Module Declaration
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Module Declaration

 Identifiers - must not be keywords!

 Ports
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Module Instances

 Modules can be instantiated within other modules to create a hierarchy

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Module Instantiation
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Primitives

 Gate Level
 and nand
 or, nor
 xor, xnor
 buf , not
 bufif0, bufif1, notif0, notif1 (three-state)
 Switch Level
 *mos where * is n, p, c, rn, rp, rc; pullup, pulldown; *tran+ where * is (null), r and +
(null), if0, if1 with both * and + not (nul)
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Primitives

 No declaration; can only be

 (X, C, D, E); //delay
instantiated
 /*Usually better to provide
 and( out, in1,in2)
instance name for debugging.*/
 All output ports appear in list
 Example: or N30 (SET, Q1, AB, N5),
before any input ports
 N41 (N25, ABC, R1);
 Optional drive strength, delay,
name of instance  Example: and #10 N33(Z, A, B, X);
// name + delay
 Example: and N25 (Z, A, B, C);
//instance name
 Example: and #10 (Z, A, B, X); //
delay