Sub Code: EC8001 Sub Name: VLSI Design

Unit-1
Introduction, Size and complexity of Integrated Circuits, The Microelectronics Field, IC Production Process,
Processing Steps, Packaging and Testing, MOS Processes, NMOS Process, CMOS Process, Bipolar Technology,
Hybrid Technology, Design Rules and Process Parameters.

Introduction

An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of
electronic circuits on one small plate of semiconductor material, normally silicon. This can be made much
smaller than a discrete circuit made from independent components. ICs can be made very compact, having up
to several billion transistors and other electronic components in an area the size of a fingernail. The width of
each conducting line in a circuit can be made smaller and smaller as the technology advances; in 2008 it
dropped below 100 nanometers and in 2017 about 7 nanometer.

ICs were made possible by experimental discoveries showing that semiconductor devices could perform the
functions of vacuum tubes and by mid-20th-century technology advancements in semiconductor device
fabrication. The integration of large numbers of tiny transistors into a small chip was an enormous
improvement over the manual assembly of circuits using discrete electronic components. The integrated
circuits mass production capability, reliability, and building-block approach to circuit design ensured the rapid
adoption of standardized integrated circuits in place of designs using discrete transistors.

There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the
chips, with all their components, are printed as a unit by photolithography rather than being constructed one
transistor at a time. Furthermore, much less material is used to construct a packaged IC die than to construct a
discrete circuit. Performance is high because the components switch quickly and consume little power
(compared to their discrete counterparts) as a result of the small size and close proximity of the components.

Integrated circuits are used in virtually all electronic equipment today and have revolutionized the world of
electronics. Computers, mobile phones, and other digital home appliances are now inextricable parts of the
structure of modern societies, made possible by the low cost of producing integrated circuits.

Terminologies associated with integrated circuit design are:

1) Integrated circuit (IC) : IC is a combination of interconnected circuit elements associated on or within a

substrate.

2) Substrate: Supporting material upon or within an IC is fabricated.

3) Hybrid IC: IC consists of a combination of two or more IC or an IC with some discrete elements.

4) Monolithic IC: An IC whose elements are formed in place upon or within a semiconductor substrate with
atleast one of the elements formed within the substrate.

5) Wafer or Slice: It is a physical unit used in processing. Typically wafer is circular; production wafers have a
diameter of 4,5 or 6 in.

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 6) Chip or die or bar: It is one of the repeated ICs on a wafer. Production wafer may contains 20 or 30 ICs, or
several hundreds or thousands depending upon the complexity and size of circuit fabricated.

7) Test Plug: It is a special chip repeated only for few times on each wafer. Used to monitor the process
parameters of the technology. After processing, the verification of process is verified by measuring, at the
wafer probe level, the characteristics of devices or circuits on the test plug. If the key parameters at the test
plug level are not matched , the wafer is discarded. Test plug is also known as process control bar (PCB) or
process control monitor (PCM).

8) Test cell: Special chip repeated only few times on each wafer. The circuit designers include test cell to
monitor the performance of subcircuits or subcomponents.

Size and complexity of Integrated Circuits

IC are classified in terms of device count used in the design of the circuit and in terms of the minimum feature
size (such as minimum gate length or minimum polysilicon width or minimum metal width) or in terms of the
pitch ( minimum of the sum of the minimum width of a feature and minimum spacing between similar
features). The pitch is often nearly twice the minimum feature size.

Classification of IC by device count:

Nomenclature Active device count

SSI Small scale integration. 1-100
MSI Medium scale integration. 100-1000.
LSI Large scale integration. 1000-100000
VLSI Very large scale integration. 10 5 - 10 6

Classification based on feature size:

Year Minimum Feature Size in microns (µ)
1970 7 to 10
1980 5
Mid-1980 2 to 1.25
1990 0.75 to 0.25

For Example: In 5µ process, the minimum value of Width (W) and Length (L) of a gate would be 5µ and the
area required for the gate of FET is 25µ2.
Impact of shrinking of feature size:
The number of devices (transistors) that can be fabricated on a given piece of silicon can be determined. For 4-
inch wafer used in a 5µ process can accommodate-

Now when feature size shrinks - the number of transistors for 4-inch wafer used in a 0.5µ process can
accommodate-

This is the impact of shrinking the feature size from 5µ process to 0.5µ process.
Due to the shrinking of feature size, there is the significance of 100-fold increase in the device count as well as
the speed of the circuit increases linearly with the feature size reduction.

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 Limitations associated with shrinking the feature size:
a) Wear and tear in matching characteristics.
b) Increased cost of equipments required for processing the wafers.
c) Advanced software design aids required.
d) Increased impact of interconnection delays.
e) Increased power dissipation and processing complications associated with heat cycling limitations during
fabrication.
Wafer Size: The number of devices that could potentially be placed on a wafer is strongly dependent upon
the wafer size. For example, in a 5µ process, the 1 cm2 chip can accommodate the gates of about 4 million 5µ x
5µ transistors.
Advantages of using smaller size die or chip are:
a) Fabrication of more chips per wafer. b) Reduction in effective cost per chip. C) Percentage of good chips
increases. D) Rectangular chips are fabricated on round wafers, the amount of wafer wasted around the
periphery is reduced.

Major factors which place limits on decreasing device dimensions:

a) Gate oxide thickness: If gate oxides thickness becomes thinner about 50 Armstrong, by decreasing
dimensions, quantum mechanical tunneling occurs, thus placing a practical bound on oxide thickness.
b) Electric field strength: High electric field strengths are also taken into concern. Voltages upto 5v are placed
across 1000 Armstrong silicon dioxide insulating layer. Hence, the electric field of magnitude is

This field is large but less than the break down voltage of silicon dioxide ie. (5 -10 MV/cm)
If the same voltage is applied to 100 A° thickness of oxide layer, the electric field would be very near to the
breakdown field for the oxide. So the only option is to decrease the voltage applied across the oxide layer. But
this is not an option because the voltage decrease noise effect becomes more significant and thus increasing
the chance of errors in the circuit.

Question :
As an OP-AMP required an area 100 mil X 100 mil and a microprocessor required an area 1 cm x 1 cm. How
many of each type of chip can be fabricated on a 5 inch wafer?
Solution
Nopamp= π‘opamp2/A2 = π;Ϯ.ϱ iŶͿ2/(0.1 in)2 = 1963
Nµp= π‘µp2/A2 = π;Ϯ.ϱ iŶͿ2/(1 cm)2 = π;Ϯ.ϱ iŶͿ2/(.39 in)2 =126

If the yield for the OP-AMP is 98% and that for the microprocessor is 30% compare the average no. of good
chips per wafer of each device that can be anticipated.
Solution
Nopamp.effective = (0.98) x (1963) = 1923
Nµp.effective = (0.3)x(126) = 37

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The Microelectronics Field

Microelectronics is a subfield of electronics. As the name suggests, microelectronics relates to the study and
manufacture (or micro fabrication) of very small electronic designs and components. These devices are
typically made from semiconductor materials. Many components of normal electronic design are available in a
microelectronic equivalent. These include transistors, capacitors, inductors, resistors, diodes and insulators
and conductors can all be found in microelectronic devices. Unique wiring techniques such as wire bonding are
also often used in microelectronics because of the unusually small size of the components, leads and pads.
This technique requires specialized equipment and is expensive.
A type of major process used in IC fabrication is as follows:

Microelectronics

Inert Active
Substrate Substrate

Thin film Thick film Silicon GaAs

MOS Bipolar MOSFE Bipolar

NMOS CMOS
ECL
PMOS TTL

Bi - MOS

I2C Many
linear ICs
Ist divison in major process types occurs between active and inert substrate. High volume ICs utilizes active
substrates whereas low volume ICs use inert substrates. Inert substrate are also used in hybrid ICs.
Inert substrate utilizes two types of processes- thick and thin film processes. These processes are used in
producing resistors with good temperature characteristics. Active substrate is a silicon or doped silicon or
gallium arsenide (GaAs). Two types of silicon processes have evolved:
(a) BJT process use BJT as basic active device . this process offers potential for high frequencies and
advantages as large transconductances. Power dissipation in BJT ICs are quite high. Examples: TTL, ECL etc.
(b) MOS process use MOSFET as basic active device. MOS process is divided into 3 -categories: NMOS, PMOS
and CMOS. PMOS refers to the MOS process that uses only p-channel FETs. NMOS refers to the MOS process
that uses only n-channel FETs. PMOS are rarely used than NMOS because the mobility of p-type material is
poorer than that of n-type material. CMOS process refers to the MOS process that simultaneously provides
both n and p channel devices.

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In digital applications, MOS devices offer very low static power consumption. In analog applications, circuit
complexity is reduced in CMOS process rather than using NMOS or PMOS process. Applications of CMOS
process are memories, interfacing, microprocessors, basic logic functions etc.
Bi-MOS is a process combining bipolar and MOS devices in a single process. This is complex and expensive
process.
IC Design Process:
Two approaches to IC design:
a) Bottom up approach: Design starts at the transistor level or gate level and design subcircuits which are then
interconnected to realize the required functionality.
b) Top-down approach: Designer decompose the system level specifications into groups and subgroups of
simpler task. The lowest level task are implemented in silicon and tested.
Block diagram of conventional IC design process:
Starting point is a set of design specifications.
Specifications : Preliminary designs are based upon simple models of devices or
subcircuits. Simple models are typically at the behavioral or
logical level for digital circuits and component or device level for
analog circuits.
Preliminary Design
: Computer simulation is used to verify the performance of
preliminary design.
Computer Simulation : Once the preliminary design is accepted, the actual layout takes
place. A good overall floor plan is obtained. The floor plan
contains all major busing and cell (subcircuits) placement
No information as well as I/O pad designations.
Acceptable : Additional computer simulation on subcircuits after layout is
Yes undertaken. These simulation will provides the parasitic effects
associated with the layout. Parasitics tends to degrade the
Lay Out performance and causes delays.
: Following an acceptable computer simulation of the entire
circuits, the circuit is committed to fabrication. In evaluation
Computer Simulation process of complicated designs, subcircuits and or test structures
are often fabricated early in the design process to provide
modeling information and to verify functionality of subcircuits. A
No No single error in the circuit design, simulation or layout makes
Acceptable
circuit totally non functional. Based upon the expected
Yes evaluation, either the circuit is released to production or the
Initial Fabrication appropriate steps of the design process is re-entered.

Test and Evaluation

No No
Acceptable
Yes
Production
 IC Production Process, Processing Steps

Creating the Diffusion and Photolithograph Etching and

wafer Deposition y Metallization
Wafer preparation:-
A wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are
constructed by doping (for example, diffusion or ion implantation, etching and deposition of various materials.
Wafers are cut out of silicon ingots (a single crystal silicon) from which wafers are cut using diamond saws.
Oxidation:-
Process where growth of a oxide layer on the surface of substrate. Oxidation process produce silicon dioxide. It
serves as a good insulator between the substrate and whatever is placed upon it. Oxidation of silicon is
achieved by heating silicon wafers in an oxidizing atmosphere.
Masking:-
IC masks are high-contrast photographic positives or negatives, used to prevent light from striking a
photosensitized wafer during a photolithographic process. The masks are made of glass covered with a thin
film of opaque material. Electron beam method is used to generate the actual patterns directly onto the final
masks. This method produces the best quality masks and used for small geometries. Another method used to
generate masks is laser beam pattern generator.
Photolithography:-
The regions of dopants, polysilicon, metal and contacts are defined using masks. Places covered by the mask,
ion implantation not occur or the dielectric or metal layers might be left intact. When mask is left or absent,
implantation can occur or dielectric or metal could be etched away.
The patterning is achieved by a process called photolithography. Photolithography steps are:
Ist step : By use of photoresist materials on the wafer, we have to define the area of interest where we want
material to be present or absent.
2nd step: This photoresist wafer is subjected to selective illumination through photomask.

UV Light

Photo Mask
Chrome pattern
Exposed
Unexposed Photoresist
photoresist
Wafer

Figure: Photomasking with a negative resist (Photolithography process)

Photo mask is constructed with chromium covered quartz glass. UV light is used to expose the photoresist.
Photo mask has chrome where light should be blocked. Positive photoresist is initially insoluble and when
exposed to UV light becomes soluble. Reverse of negative photoresist.

Deposition:- Films of various materials must be applied on the wafer during processing. Films that are
deposited include insulators, resistive films, conductive films, dielectrics, n and p type materials Available
technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical

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5
 deposition (ECD) and molecular beam epitaxial (MBE) and more recently, atomic layer deposition (ALD) among
others.

Removal or Etching Process:-

Etching is removing of unwanted materials from the surface of the substrate. The physical characteristics of
the surface are changed by etching. The chemical used for etching reacts with the unprotected areas on the
wafer .
2-types of etching: Wet etching called chemical etching uses liquids etching agents. Dry etching also called ion
etching. This technique includes sputter etching, ion beam etching and plasma etching. Dry etching is widely
used. Figure Characteristics of etches: (a) Isotropic etch is non directional etch. Problem with isotropic etch is
that effective opening and the undercut will be larger than desired. (b) Anisotropic etch is a directional etch.
Has an abrupt edge. Problem for applying subsequent layers uniformly across the edge. (c) Preferential etch is
a directional etch but less directional than anisotropic etch.

Protective layer Protective layer

Etch layer Under Etch
Under Etch
Underlying Layer
Ideally Etch
Isotropic Etch Over Etch Anisotropic Etch

Protective
Under Etch

Preferential Etch
Figure: Characteristics of etches

Diffusion:
Diffusion refers to the controlled forced migration of impurities into the substrate .this plays a major role in
the performance of the IC and is affected by temperature and time during the processing. Methods of
diffusion: A solid deposition layer or a gaseous layer above the surface can be used as a source of impurities.
Impurities can be bombarded to the substrate so that they actually become lodged inside the substrate very
near the surface. This is ion implantation, very accurate control of impurity concentrations but causes damage
to the crystal surface.
Impurities typically diffuse both vertically and laterally from the surface at comparable rates.

Contacts and Metallization:

Contact cuts are made to source, drain and gate according to the contact mask. These holes are etched.
Aluminium is used for wires but tungsten can be used as a plug to fill contact holes. Metallization is a process
of building wires to connect the devices. Metal films are useful for interconnections that carry large currents.
Nonmetallic films (polysilicon )are widely used for conductors and interconnections when current flow is
small. Polysilicon is good conductor when heavily doped and good resistor when lightly doped. Polysilicon is
often used for gates of MOSFETs and electrodes for capacitors. Polysilicon can be deposited over silicon
dioxide.

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 Packaging and Testing
After processing, the circuits are tested and packaged. The first step in the testing process generally involves a
process verification to make certain that the process parameters are within the tolerance acceptable for the
product. To facilitate this verification, test plug containing special test structures specially designed for this
purpose are included on the wafer at several locations in place of the regular circuits themselves.
Packaging for integrated circuits:
Proper packaging technology is critical to the success of the chip development.
Package issues have to be taken into consideration in early stages of chip development.
Ensure sufficient design margins to accommodate the parasitic of the package.
Important packaging concerns:
Hermetic seals to prevent the penetration of moisture.
Thermal conductivity.
Thermal expansion coefficient.
Pin density.
Parasitic inductance and capacitance. α
paƌtiĐle pƌoteĐtioŶ.
Cost.

MOS PROCESSES:
The principle of operation of the MOS transistor at DC and low frequency provide a close into the MOS
process.
Operation of MOSFET:
Consider the n- channel enhancement MOSFET as shown in figure .

Figure: Operation of n-channel MOSFET

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 Complementary MOS Technology
It is a combination of both n-channel and p-channel devices in one chip. Compared to both other process,
CMOS is complex in fabrication and requires larger chip area. Biggest advantage of a CMOS circuit is reduced
power consumption (less than NMOS); it is designed for zero power consumption in steady state condition for
both logic states. As you may already know, CMOS circuits are widely used in digital equipments like watches,
computers etc.

CMOS offers comparatively higher circuit density and high speed performance (used in VLSI); and this is the
pƌiŵaƌLJ ƌeasoŶ ǁhLJ CMOS is still pƌefeƌƌed despite its͛ Đoŵpledž ŵaŶufaĐtuƌiŶg pƌoĐess. Meŵoƌies aŶd
microprocessors made of CMOS usually employ silicon gate process.

There are variations of MOS technology which offer either better performance or density advantages over the
standard process. Some of those are named as VMOS (V-groove MOS), DSA (Diffusion Self Aligned), SOS
(Silicon on Sapphire), D-MOS (Double diffused MOS) etc.

Characteristics of CMOS Technology

Lower static power dissipation
Higher noise margins
Higher packing density - lower manufacturing cost per device
High yield with large integrated complex functions
High input impedance (low drive current)
Scalable threshold voltage
High delay sensitivity to load (fan-out limitations)
Low output drive current (issue when driving large capacitive loads)
Low trans conductance, where trans conductance, gm a Vin
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device

Bi-CMOS technology: -
(Bipolar CMOS) The driving capability of MOS transistors is less because of limited current sourcing and
sinking capabilities of the transistors. To drive large capacitive loads we can think of Bi-CMOS technology. This
technology combines Bipolar and CMOS transistors in a single integrated circuit, by retaining benefits of
bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously
unattainable with either technology individually.

Characteristics of Bipolar Technology

Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency characteristics
Better analogue capability
Improved I/O speed (particularly significant with the growing importance of package limitations in high speed
systems).
High power dissipation
Lower input impedance (high drive current)
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High unity gain band width (ft) at low currents

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Essentially unidirectional from the two previous paragraphs we can get a comparison between bipolar
and CMOS technology

Hybrid Technology
A hybrid integrated circuit, HIC, hybrid microcircuit, or simply hybrid is a miniaturized electronic circuit
constructed of individual devices, such as semiconductor devices (e.g. transistors and diodes) and passive
components (e.g. resistors, inductors, transformers, and capacitors), bonded to a substrate or printed circuit
board (PCB). Hybrid circuits are often encapsulated in epoxy.
The advantage of hybrid circuits is that components which cannot be included in a monolithic IC can be used,
e.g., capacitors of large value, wound components, crystals, inductors.
Thick film technology is often used as the interconnecting medium for hybrid integrated circuits. The use of
screen printed thick film interconnect provides advantages of versatility over thin film although feature sizes
may be larger and deposited resistors wider in tolerance. Multi-layer thick film is a technique for further
improvements in integration using a screen printed insulating dielectric to ensure connections between layers
are made only where required. One key advantage for the circuit designer is complete freedom in the choice
of resistor value in thick film technology. Planar resistors are also screen printed and included in the thick film
interconnect design. The composition and dimensions of resistors can be selected to provide desired values.
The final resistor value is determined by design and can be adjusted by laser trimming. Once the hybrid circuit
is fully populated with components, fine tuning prior to final test may be achieved by active laser trimming.

Design Rules and Process Parameters:

Design rules are well documented specifications consists of minimum width of features (resistors, conductors
etc), minimum spacing allowable between adjacent features, overlap requirements and other measurements
compatible with the given process. Factors such as mask alignment, mask non-linearities, wafer wrapping,
oxide growth profile, lateral etch, optical resolution and their relationship with performance and yields are
considered when specifying the design rules for the process. The rules were derived under the assumption
that large circuits with many devices sized at the minimum allowable levels must have good performance and
high yields. Consider the design rules and process parameters as a set of constraints within which the circuit
designer must work.
CMOS design rules:
Two sets of design dimensions are specified. First corresponds to the 3µ CMOS process provided by MOSIS.
Second is in terms of the scaling parameter, , which characterizes the feature size of the process. The feature
size ( minimum poly width, active width, and metal width ) is 2 .
Design rules described in two ways:
Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature
separations, are stated in terms of absolute dimensions in micrometers.
Lambda rules, which specify the layout constraints in terms of a single parameter and thus, allow linear,
proportional scaling of all geometrical constraints.
Lambda-based layout design rules were originally devised to simplify the industry- standard micron-based
design rules and to allow scaling capability for various processes. It must be emphasized, however, that most
of the submicron CMOS process design rules do not lend themselves to straightforward linear scaling. The use
of lambda-based design rules must therefore be handled with caution in sub-micron geometries. In the
following, we present a sample set of the lambda-based layout design rules devised for the MOSIS CMOS
process and illustrate the implications of these rules on a section a simple layout which includes two
transistors.
Design rules for a typical p-well CMOS process
Sr. Rule
No. number Description Dimensions
Microns Scalable
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 1 p-well Layer
1.1 Width 5 4
1.2 Spacing to well at different potential 15 10
1.3 Spacing to well at same potential 9 6
2 Active (Diffusion ) Layer
2.1 Width 4 2
2.2 Spacing to active 4 2
2.3 P+ active in n-subs to p-well edge 8 6
2.4 n+ active in n-subs to p-well edge 7 5
2.5 n+ active in p-well to p-well edge 4 2
2.6 p+ active in p-well to p-well edge 1
3 Poly
3.1 Width 3 2
3.2 Spacing 3 2
3.3 Field poly to active 2
3.3 Poly overlap of active 3 2
3.4 Active overlap of poly 4 2
4 P+ Select
4.1 Overlap of active 2
4.2 Space to n+ active 2
4.3 Overlap of channel 3.5 2
4.4 Space to channel 3.5 2
4.5 Space to P+ select 3 2
4.6 width 3 2

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