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    Exception and Interrupt Handler: B.Tech ECE V Semester SENSE VIT University

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    sophieee19
    When an exception or interrupt occurs on an ARM processor, the processor suspends normal execution and loads instructions from a vector table located in memory. The vector table contains the addresses of dedicated exception handlers for different exception types like Reset, Undefined Instruction, and interrupts. Exception handlers save processor state, service the exception, and return using a defined protocol to ensure correct system operation. Interrupts are prioritized as FIQ or IRQ and assigned to handlers to minimize latency and ensure timely system response.

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    Exception and Interrupt Handler: B.Tech ECE V Semester SENSE VIT University

    Uploaded by

    sophieee19
    13K views36 pages
    When an exception or interrupt occurs on an ARM processor, the processor suspends normal execution and loads instructions from a vector table located in memory. The vector table contains the addresses of dedicated exception handlers for different exception types like Reset, Undefined Instruction, and interrupts. Exception handlers save processor state, service the exception, and return using a defined protocol to ensure correct system operation. Interrupts are prioritized as FIQ or IRQ and assigned to handlers to minimize latency and ensure timely system response.

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    Exceptions

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    When an exception or interrupt occurs on an ARM processor, the processor suspends normal execution and loads instructions from a vector table located in memory. The vector table contains the addresses of dedicated exception handlers for different exception types like Reset, Undefined Instruction, and interrupts. Exception handlers save processor state, service the exception, and return using a defined protocol to ensure correct system operation. Interrupts are prioritized as FIQ or IRQ and assigned to handlers to minimize latency and ensure timely system response.

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    Attribution Non-Commercial (BY-NC)
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    Download as pdf or txt
    13K views36 pages

    Exception and Interrupt Handler: B.Tech ECE V Semester SENSE VIT University

    Uploaded by

    sophieee19
    When an exception or interrupt occurs on an ARM processor, the processor suspends normal execution and loads instructions from a vector table located in memory. The vector table contains the addresses of dedicated exception handlers for different exception types like Reset, Undefined Instruction, and interrupts. Exception handlers save processor state, service the exception, and return using a defined protocol to ensure correct system operation. Interrupts are prioritized as FIQ or IRQ and assigned to handlers to minimize latency and ensure timely system response.

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    of 36

    ARM

    Exception and Interrupt Handler

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    Exceptions, Interrupts, and the Vector Table


    When an exception or interrupt occurs, the processor set the PC to a specific memory address The address is within a special address range called the vector table The entries in the vector table are instructions that branch to specific routines designed to handle a particular exception or interrupt When an exception or interrupt occurs,the processor suspends normal execution and starts loading instructions from the exception vector table.
    B.Tech ECE V semester SENSE VIT University

    Exceptions, Interrupts, and the Vector Table


    Exception / Interrupt
    Reset Undefined Instruction Software Interrupt

    Shorthand
    RESET UNDEF SWI

    Address
    0x00000000 0x00000004 0x00000008

    High Address
    0xffff0000 0xffff0004 0xffff0008

    Prefetch Abort
    Data Abort Reserved Interrupt Request Fast Interrupt Request

    PABT
    DABT IRQ FIQ

    0x0000000C
    0x000000010 0x000000014 0x000000018 0x00000001C

    0xffff000C
    0xffff0010 0xffff0014 0xffff0018 0xffff001C

    B.Tech ECE V semester SENSE VIT University

    Exceptions, Interrupts, and the Vector Table


    RESET when power is applied, branches to initialization code UNDEF when the processor cannot decode an instruction SWI when a SWI instruction is called PABT attempts to fetch an instruction from an address without the correct access permissions DABT attempts to access data memory without the correct access permissions IRQ by external hardware FIQ by external hardware requiring faster response time
    B.Tech ECE V semester SENSE VIT University

    Exception Handling
    ARM processor modes and Exceptions Vector table Exception Priorities Link Register Offsets

    B.Tech ECE V semester SENSE VIT University

    ARM processor modes and Exceptions


    When an exception causes the mode change, the core automatically
    Save CPSR to SPSR PC to LR Sets cpsr to exception mode Set PC to address of exception handler

    B.Tech ECE V semester SENSE VIT University

    When an exception occurs ARM processor always switches to ARM STATE.

    B.Tech ECE V semester SENSE VIT University

    Vector table
    B<address> LDR pc, [pc, #offset] MOV pc, #immediate

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    priorities

    B.Tech ECE V semester SENSE VIT University

    Link register offset

    B.Tech ECE V semester SENSE VIT University

    Interrupts
    Two types of interrupts
    External SWI

    B.Tech ECE V semester SENSE VIT University

    Interrupt Latency

    Interrupt latency can be minimized by two methods


    Nested Interrupt-system can respond to new interrupts while handling the old Giving priorities to different interrupt sources

    B.Tech ECE V semester SENSE VIT University

    IRQ and FIQ Exception


    The ARM processor will continue executing the current instruction in the pipeline before handling the interrupt. The processor hardware go through the following standard procedure
    The processor changes to a specific mode depending on the received interrupt. The previous mode CPSR is saved in SPSR of the new mode. The PC is saved in the LR of the new mode. Either IRQ or both IRQ and FIQ exceptions are disabled in the cpsr. The processor branches to a specific entry in the vector table.

    B.Tech ECE V semester SENSE VIT University

    IRQ

    B.Tech ECE V semester SENSE VIT University

    FIQ

    Stack Organization
    Stack area is different for each and every mode Descending Stack is common Nested interrupt handler requires larger stack While choosing stack location Should not overrun the vector table
    B.Tech ECE V semester SENSE VIT University

    Interrupt Stack
    Context switching Each mode has a dedicated register containing a stack pointer

    B.Tech ECE V semester SENSE VIT University

    Exception handlers
    Reset Handler
    Initializes the system, setting Stack pointers, memory, External interrupt sources before enabling the FIQ and IRQ. Code should be designed to avoid further triggering of exceptions

    B.Tech ECE V semester SENSE VIT University

    Data Abort
    FIQ can be raised within DATA abort handler

    FIQ
    External peripheral generates FIQ signal Core disables both FIQ and IRQ

    B.Tech ECE V semester SENSE VIT University

    IRQ
    Occurs when an External device generates IRQ signal IRQ handler will be entered if neither an FIQ and Data abort occurs. On entry IRQ exception is disabled and should remain disabled for the handler if not enabled by the handler

    B.Tech ECE V semester SENSE VIT University

    Prefetch abort
    Occurs when an attempt to fetch an instruction results in memory fault. FIQ exception can be serviced

    Undefined instruction
    Occurs when an instruction is not in ARM or thumb instruction

    SWI and undefined instruction have the same level of priority


    B.Tech ECE V semester SENSE VIT University

    FIQ and IRQ can be serviced after the Execution stage Others can be serviced during execution stage.

    B.Tech ECE V semester SENSE VIT University

    Returning from exception handler


    Exception handler must not corrupt lr Moving correct value of lr into PC Restoring CPSR from SPSR For interrupt ,
    When accessing r15[PC], r15=address of current instruction +8 Proper adjustment of LR is required while returning from handler
    B.Tech ECE V semester SENSE VIT University

    Interrupt Assignment
    An interrupt controller connects multiple external interrupts to either FIQ or IRQ IRQ are normally assigned to general purpose interrupts
    Ex: periodic timer interrupt to force a context switch

    FIQ is reserved for an interrupt source which requires fast response time [less latency]
    B.Tech ECE V semester SENSE VIT University

    Interrupt Latency
    Hardware and software latency
    Eg for HW is FIQ Eg for SW is Nested handler, priority assignment, Average latency of Higher priority interrupt is less.

    B.Tech ECE V semester SENSE VIT University

    3 stage pipeline
    At any time slice, 3 different instruction may occupy each of these stages, so the hardware in each stage has to be capable of independent operations When the processor is executing data processing instructions, Latency =3 cycles When accessing R15, r15 = address of current instruction +8
    B.Tech ECE V semester SENSE VIT University

    Pipelined instruction sequence


    Fetch Time Cycle 1 Cycle 2
    Cycle 3

    Decode

    Execute

    ADD
    SUB ADD

    CMP

    SUB

    ADD

    Filling the pipeline Allows the core to execute an instruction every cycle
    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

    SWI Handler

    B.Tech ECE V semester SENSE VIT University

    B.Tech ECE V semester SENSE VIT University

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