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    Lecture26 - Transmission Gates: Jagannadha Naidu K

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    sophieee19
    This document discusses transmission gates and pass-transistor logic. It begins by explaining the basic concept of a pass-transistor logic switch network that uses transistors as switches to implement logic functions with no static power consumption. It then discusses using only NMOS transistors which causes threshold voltage loss issues. To address this, a level restoring transistor can be added. The document goes on to explain complementary pass-transistor logic that uses both NMOS and PMOS transistors to implement common logic gates. It also discusses how transmission gates can be used as switches controlled by both true and complement inputs. Examples provided include a multiplexer, XOR gate, and full adder built using pass-transistor and transmission gate logic.

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    Lecture26 - Transmission Gates: Jagannadha Naidu K

    Uploaded by

    sophieee19
    18 views12 pages
    This document discusses transmission gates and pass-transistor logic. It begins by explaining the basic concept of a pass-transistor logic switch network that uses transistors as switches to implement logic functions with no static power consumption. It then discusses using only NMOS transistors which causes threshold voltage loss issues. To address this, a level restoring transistor can be added. The document goes on to explain complementary pass-transistor logic that uses both NMOS and PMOS transistors to implement common logic gates. It also discusses how transmission gates can be used as switches controlled by both true and complement inputs. Examples provided include a multiplexer, XOR gate, and full adder built using pass-transistor and transmission gate logic.

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    Transmission Gates

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    This document discusses transmission gates and pass-transistor logic. It begins by explaining the basic concept of a pass-transistor logic switch network that uses transistors as switches to implement logic functions with no static power consumption. It then discusses using only NMOS transistors which causes threshold voltage loss issues. To address this, a level restoring transistor can be added. The document goes on to explain complementary pass-transistor logic that uses both NMOS and PMOS transistors to implement common logic gates. It also discusses how transmission gates can be used as switches controlled by both true and complement inputs. Examples provided include a multiplexer, XOR gate, and full adder built using pass-transistor and transmission gate logic.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    18 views12 pages

    Lecture26 - Transmission Gates: Jagannadha Naidu K

    Uploaded by

    sophieee19
    This document discusses transmission gates and pass-transistor logic. It begins by explaining the basic concept of a pass-transistor logic switch network that uses transistors as switches to implement logic functions with no static power consumption. It then discusses using only NMOS transistors which causes threshold voltage loss issues. To address this, a level restoring transistor can be added. The document goes on to explain complementary pass-transistor logic that uses both NMOS and PMOS transistors to implement common logic gates. It also discusses how transmission gates can be used as switches controlled by both true and complement inputs. Examples provided include a multiplexer, XOR gate, and full adder built using pass-transistor and transmission gate logic.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 12

    Lecture26 Transmission Gates

    Jagannadha Naidu K
    Pass-Transistor Logic
    I
    n
    p
    u
    t
    s
    Switch
    Network
    Out
    Out
    A
    B
    B
    B
    N transi stors
    No stati c consumpti on
    Example: AND Gate
    B
    B
    A
    F =AB
    0
    NMOS-Only Logic
    V
    DD
    In
    Out
    x
    0.5

    m/0.25

    m
    0.5

    m/ 0.25

    m
    1.5

    m/ 0.25

    m
    0 0.5 1 1.5 2
    0.0
    1.0
    2.0
    3.0
    Time [ns]
    V
    o
    l
    t
    a
    g
    e
    [
    V
    ]
    x
    Out
    In
    NMOS-only Switch
    A = 2.5 V
    B
    C = 2.5V
    C
    L
    A = 2.5 V
    C = 2.5 V
    B
    M
    2
    M
    1
    M
    n
    Threshold voltage loss causes
    static power consumption
    V
    B
    does not pull up to 2.5V, but 2.5V -V
    TN
    NMOS has higher threshold than PMOS (body effect)
    NMOS Only Logic:
    Level Restoring Transistor
    M
    2
    M
    1
    M
    n
    M
    r
    Out
    A
    B
    V
    DD
    V
    DD
    Level Restorer
    X
    Advantage: Full Swing
    Restorer adds capacitance, takes away pull down current at X
    Ratio problem
    Complementary Pass Transistor Logic
    A
    B
    A
    B
    B B B B
    A
    B
    A
    B
    F=AB
    F=AB
    F=A+B
    F=A+B
    B B
    A
    A
    A
    A
    F=A

    F=A

    OR/NOR
    EXOR/NEXOR AND/NAND
    F
    F
    Pass-Transistor
    Network
    Pass-Transistor
    Network
    A
    A
    B
    B
    A
    A
    B
    B
    Inverse
    (a)
    (b)
    Transmission Gate
    A
    B
    C
    C
    A B
    C
    C
    B
    C
    L
    C =0 V
    A = 2.5 V
    C = 2.5 V
    Resistance of Transmission Gate
    V
    out
    0 V
    2.5 V
    2. 5 V
    R
    n
    R
    p
    0.0 1.0 2.0
    0
    10
    20
    30
    V
    out
    , V
    R
    e
    s
    i
    s
    t
    a
    n
    c
    e
    ,

    o
    h
    m
    s
    R
    n
    R
    p
    R
    n
    || R
    p
    Pass-Transistor Based Multiplexer
    A
    M
    2
    M
    1
    B
    S
    S
    S
    F
    V
    DD
    Transmission Gate XOR
    A
    B
    F
    B
    A
    B
    B
    M1
    M2
    M3/M4
    Transmission Gate Full Adder
    A
    B
    P
    C
    i
    V
    DD
    A
    A
    A
    V
    DD
    C
    i
    A
    P
    A
    B
    V
    DD
    V
    DD
    C
    i
    C
    i
    C
    o
    S
    C
    i
    P
    P
    P
    P
    P
    Sum Generation
    Carry Generation
    Setup
    Similar delays for sum and carry

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