ME4447/6405

ME 4447/6405
Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics

Instructor: Professor Charles Ume Interrupts and Resets

George W. Woodruff School of Mechanical Engineering, Georgia Tech

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Reason for Interrupts

You might want instructions executed immediately after internal request and/or request from peripheral devices when certain condition are met . Interrupt provides way to temporarily suspend current program execution in order to execute certain set of tasks.
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Methods of Checking for Requests

There are two methods of checking when requests are made internally or from peripheral devices.
Polling Interrupts

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Polling
An iterative approach which constantly checks devices for data Inefficient method for checking when input data has come in because no other instructions can be executed during polling process

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Interrupts
Communication between CPU and I/O devices can be established with issue of interrupt request NOTE: Request can be issued at any time CPU suspends execution of main program until instructions in Interrupt Service Routine (ISR) are completely executed Returns to main program after ISR is completed

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Types of Interrupts
There are two types of interrupts.
Maskable Non-Maskable

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Maskable Interrupts
27 Maskable Interrupts
Two types of Masking

Local

Interrupt enable bit

Global

I-bit in CCR

Follows a default priority arrangement

Any one interrupt can be promoted to higher priority using HPRIO register

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27.

IRQ Real-Time Interrupt Standard Timer Channel 0 Standard Timer Channel 1 Standard Timer Channel 2 Standard Timer Channel 3 Standard Timer Channel 4 Standard Timer Channel 5 Standard Timer Channel 6 Standard Timer Channel 7 Standard Timer Overflow Pulse Accumulator A Overflow Pulse Accumulator Input Edge SPI transfer Complete SCI system ATD Port J CRG PLL Lock CRG Self Clock Mode Flash CAN Wakeup CAN Errors CAN Receive CAN Transmit Port P PWM Emergency Shutdown VREG LVI

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Maskable Interrupts: IRQ Input

IRQ pin provides additional external interrupting source IRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation
IRQE = 0 IRQ is configured for low level sensitive operation IRQE = 1 IRQ is configured for falling edge-sensitive operation

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Maskable Interrupts: Peripheral Subsystems

Interrupts from Internal Peripheral Subsystems
Flag bit, which is set after action takes place Interrupt enable bit, which enables flag to generate interrupt service

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Interrupt Priority: Maskable Maskable Interrupts Priority

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. IRQ Real-Time Interrupt Standard Timer Channel 0 Standard Timer Channel 1 Standard Timer Channel 2 Standard Timer Channel 3 Standard Timer Channel 4 Standard Timer Channel 5 Standard Timer Channel 6 Standard Timer Channel 7 Standard Timer Overflow Pulse Accumulator A Overflow Pulse Accumulator Input Edge SPI transfer Complete SCI system ATD Port J CRG PLL Lock CRG Self Clock Mode Flash CAN Wakeup CAN Errors CAN Receive CAN Transmit Port P PWM Emergency Shutdown VREG LVI

Any can be assigned the highest maskable interrupt priority...

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HPRIO Register for Maskable Interrupts

Used to elevate priority of any one maskable interrupt Default is IRQ Set by changing contents of HPRIO (Highest Priority Interrupt Register) Can only be written when I-bit is set

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HPRIO Register for Maskable Interrupts

Address: $001F

Bit 7 PSEL7

Bit 6 PSEL6

Bit 5 PSEL5

Bit 4 PSEL4

Bit 3 PSEL3

Bit 2 PSEL2

Bit 1 PSEL1

Bit 0

PSEL[7:1] Priority Select Bits

Selects one interrupts source to be elevated Can only be written while I-bit in the CCR is set

Write the low byte of the maskable interrupt vector to HPRIO to elevate that maskable interrupt to the highest priority Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1
PSEL7

1
PSEL6

0
PSEL5

1
PSEL4

1
PSEL3

1
PSEL2

1
PSEL1 -

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Non-Maskable Interrupts
6 Non-Maskable Interrupts
Follows a default priority arrangement Interrupts are not subject to global masking
1. 2. 3. 4. POR of RESET pin Clock monitor reset COP watchdog reset Unimplemented instruction trap 5. Software interrupt (SWI) 6. XIRQ interrupt

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Non-Maskable Interrupts: Unimplemented instruction trap

Generates interrupt request to Unimplemented instruction trap vector Reinitializes stack pointer once interrupt service is completed Left un-initialized, illegal opcode vector can cause infinite loop causing stack underflow

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Non-Maskable Interrupts: Software Interrupt

Software instruction, thus cannot be interrupted until completed Uninhibited by global mask bits in the CCR Similar to other interrupts, sets I-bit upon servicing

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Non-Maskable Interrupts: XIRQ

Enabled by TAP instruction by clearing X-bit upon system initialization After being cleared, software cannot set X-bit, thus XIRQ is non-maskable Higher priority than any source maskable by I-bit Both X and I bits are automatically set by Reset or recognition of XIRQ interrupt RTI restores X and I bit to pre-interrupt states
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Stacking Order when an Interrupt Occurs

Memory Location CPU Registers

SP
SP-1 SP-2 SP-3 SP-4 SP-5 SP-6 SP-7 SP-8

PCL
PCH IYL IYH IXL IXH ACCA ACCB CCR

Last value to be pulled from stack

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Interrupt Vectors
Each type of interrupt has associated vector addresses Vector addresses change depending on whether MON12 is in use With MON12 in use, user must use Monitor Interrupt Vector Table

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MON12 in Use
In this case you must write the address of your Interrupt Service Routine to the vector address found in the Monitor Interrupt Vector Table

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Interrupt Vector Table: MON12 in Use

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MON12 Not in Use

Interrupt vector addresses are usually occupied by MON12 With MON12 not in use, starting ISR address must be programmed in standard vector address

George W. Woodruff School of Mechanical Engineering, Georgia Tech

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Interrupt Vector Table: MON12 not in Use

George W. Woodruff School of Mechanical Engineering, Georgia Tech

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George W. Woodruff School of Mechanical Engineering, Georgia Tech

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Interrupt Flow
A B Analyze Priority Set (I) or (X) to prohibit another Interrupt

Interrupt condition is met

YES

Global Masking
NO YES

ISR instruction
NO

RTI
YES

Local Masking
NO

Complete Current Instruction Store all registers on the Stack Continue Program A

Standard Interrupt Table Load Address in appropriate vector

Clear I or X bit in CCR

Restore Registers w/ org. Values

Note: Local mask must be cleared prior to performing RTI

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Elapsed Time Example

Write a routine to interrupt the MC9S12C32 after 10 msec of elapsed time (Assume E= 1 Mhz, Prescaler = 1, MON12 in use)
ORG LDD STD $1000 #$FFFF TC3H OR SEI LDAA STAA STAA STAA LDAB STAB LDX STX #BIT3HI TIOS TFLG1 TIE #$C0 TCTL2 #TC3ISR TC3VEC /*Set I-bit to prevent interrupt service during set-up*/ /* BIT5HI = %0010000*/ /* Select TC3 as an output compare*/ /* Clear TC3 Interrupt Flag*/ /* Enable TC3 Interrupt */ /* PT3 will be high for a successful compare */ /* TC3ISR = $2000, 2 bytes- beginning address of interrupt service routine*/ /* TC3VEC= $0FE8, This will cause the high byte ($20) of the service routine address to be stored in location $0FE8 and the low byte ($00) to be stored in $0FE9 */ /* TCNT=$0044 */ /* DLYIOMS = $2710 = 10000 */ /* IF not done elsewhere */ /* Clear I bit */

/*Delays any TC3 compares*/ /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/

LDD ADDD STD CLI

TCNT #DLYIOMS TC3

George W. Woodruff School of Mechanical Engineering, Georgia Tech

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Elapsed Time Example

Write a routine to interrupt the MC9S12C32 after 10 msec of elapsed time (Assume E= 1 Mhz, Prescaler = 1, MON12 in use)
ORG LDD STD $1000 #$FFFF TC3H OR SEI LDAA STAA STAA STAA LDAB STAB LDD ADDD STD CLI . SWI END #BIT3HI TIOS TFLG1 TIE #$C0 TCTL2 TCNT #DLYIOMS TC3 /*Set I-bit to prevent interrupt service during set-up*/ /* BIT3HI = %0003000*/ /* Select TC3 as an output compare*/ /* Clear TC3 Interrupt Flag*/ /* Enable TC3 Interrupt */ /* PT3 will be high for a successful compare */ /* TCNT=$0044 */ /* DLYIOMS = $2710 = 10000 */ /* IF not done elsewhere */ /* Clear I bit */

/*Delays any TC3 compares*/ /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/

ORG $0FE8 George W. Woodruff School of Mechanical Engineering, Georgia Tech FDB TC3ISR

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Example: Timer Overflow Interrupt

TFLG2 TSCR2 TOFISR PROGRAM STRING OUTSTRG VECTOR EQU $004F *Timer Interrupt Flag 2 EQU $1024 *Timer Interrupt Mask 2 EQU $1500 *ISR memory location EQU $1000 EQU $2000 EQU $FF5E EQU $0FDE ORG STRING FCC 'TICK' FCB $04 LOOP BRA LOOP SWI *Software Interrupt End

ORG PROGRAM *Set I-bit to prevent interrupt service during set-up SEI Start timer, turn on TEN LDAA #$80 STAA TSCR2 *TOF Interrupt Enabled STAA TFLG2 *Clears TOF Interrupt Flag LDX #TOVISR *Loads register X with #1500 *Stores content of register X to address Vector incremented STX VECTOR CLR $0001 CLI * Clears I-bit to allow servicing of interrupt

ORG TOVISR LDAA $0001 * Loads address $0001 content INCA *Increment by 1 STAA $0001 *Stores value back to address CMPA #30 *Compares value to decimal 30 BNE A1 *Loads index register X with content of STRING LDX #STRING JSR OUTSTRG CLR $0001 *Clear address
A1 LDAA #$80 *Loads binary 10000000 STAA TFLG2 *Clears local flag RTI

Pre-interrupt service set-up

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Resets
Forces the MCU to: assume set of initial conditions begin executing instructions at predetermined starting address.

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Resets
Like interrupts, resets share concept of vector fetching to force new starting point for further CPU operations. In contrast to interrupts, resets stop completely execution of set of instructions. As well, they always rest MCU hardware.

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Sources of Resets
Power on Reset (POR) External Reset (RESET) Computer Operating Properly (COP) Reset Clock Monitor Reset

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Power-On Resets
Power-On Reset (POR) Used only for power-up conditions to initialize MCU internal circuits. Applying Vdd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit. 4064 clock cycle delay after oscillator becomes active, allows clock generator to stabilize.
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External Reset
System reset can also be forced by applying low level to RESET pin. External source must hold pin low for more than 4 cycles. If this happens, pin is further sampled 2 cycles after Low level at sampling instant indicates that reset has been caused by external device.
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Computer Operating Properly Reset

Protects against software failures When enabled, software to keep free- running watchdog timer from timing out is activated System reset is initiated when software stops executing in the intended sequence

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COP Reset continued

COP is enabled or disabled by setting NOCOP bit in CONFIG register. To change status of COP system, contents of CONFIG register are changed and system reset is initiated. COP timer rate is controlled in OPTION Register. The system E-clock is divided by 2^15 and further scaled by 1, 2 and 4.
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Clock Monitor Reset

Clock Monitor Reset circuit is based on internal resistor capacitor time delay.

If no MCU clock edges are detected within this RC time delay, clock monitor, if set by CME control bit, would generate system reset.

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How the MPU Distinguishes between Internal and External Resets

MPU senses whether reset pin rises to logic 1 within two E-clock cycles after internal device releases reset. When reset condition is sensed, RESET pin is driven low by internal device for 4 E-clock cycles, then released. Two E-clock cycles later, it is sampled.

If pin is still held low, CPU assumes that external reset has occurred. If pin is high, it indicates that reset was internally initiated.
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Occurrence of Reset Affects

CPU Memory Map Timer Real-time Interrupt Pulse Accumulator SPI ADC System COP SCI

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Process Flow out of Resets

When Reset is triggered Vector fetch (Program counter loaded with contents of specified address) S, X and I bits set in CCR MCU hardware reset Checks for interrupts

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Standby Modes
Suspends CPU operation until reset or interrupt occurs Used to reduce power consumption Two standby modes:
WAIT STOP

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Standby Modes: WAIT

Opcode (WAI) Suspends CPU processing CPU registers are stacked On-chip crystal oscillator remains active Exit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts

George W. Woodruff School of Mechanical Engineering, Georgia Tech

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Standby Modes: STOP

If S-bit in the CCR is 0, CPU goes into stop mode Else, opcode is treated as NOP All clocks stopped internal peripherals stopped Retains data in Internal RAM if VDD is maintained CPU state and I/O pin levels are static Exit STOP mode through external interrupts, pending edge-triggered IRQ or RESET pin
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Standby Modes: STOP

Recovering through XIRQ X-bit is clear Returns to stacking sequence leading to normal XIRQ request X-bit is set Returns to instruction immediately following STOP instruction

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Questions???

George W. Woodruff School of Mechanical Engineering, Georgia Tech