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Some History Invention of the transistor (BJT) Shockley, Bardeen, Brattain Bell Labs
1947 1958 1963 1970
Single-transistor integrated circuit
Jack Kilby Texas Instruments
Invention of CMOS logic gates
Wanlass & Sah Fairchild Semiconductor
First microprocessor (Intel 4004)
2,300 MOS transistors, 740 kHz clock frequency
Very Large Scale Integration
Chips with more than ~20,000 devices 2
1978
CMOS Digital Integrated Circuits 3rd Edition
More Recently Ultra Large Scale Integration System on Chip (SoC)
20 ~ 30 million transistors in 2002
The chip complexity has increased by a factor of 1000 since its first introduction, but the term VLSI remained virtually universal to denote digital integrated systems with high complexity. 3 CMOS Digital Integrated Circuits 3rd Edition
Economic Impact
As a result of the continuously increasing integration density and decreasing unit costs, the semiconductor industry has been one of the fastest growing sectors in the worldwide economy. 4 CMOS Digital Integrated Circuits 3rd Edition
Industry Trends
Large Centralized Expensive
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Small / Portable Distributed Inexpensive
CMOS Digital Integrated Circuits 3rd Edition
Industry Trends High performance Low power dissipation Wireless capability etc
More portable, wearable, and more powerful devices for ubiquitous and pervasive computing 6 CMOS Digital Integrated Circuits 3rd Edition
Some Leading-Edge Examples
CMOS Digital Integrated Circuits 3rd Edition
Some Leading-Edge Examples
IBM S/390 Microprocessor 0.13 m CMOS process 7 layers Cu interconnect 47 million transistors 1 GHz clock 180 mm2
CMOS Digital Integrated Circuits 3rd Edition
Evolution of Minimum Feature Size
CMOS Digital Integrated Circuits 3rd Edition
Evolution of Minimum Feature Size
2002: 130 nm 2003: 90 nm 2010: 35 nm (?)
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Moores Law
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Evolution of Memory Capacity
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ITRS - International Technology Roadmap for Semiconductors
YEAR TECHNOLOGY CHIP SIZE NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 2002 130 nm 400 mm 400 M 2
2005 100 nm 600 mm 1 Billion
2
2008 70 nm 750 mm 3 Billion
2
2011 50 nm 800 mm 6 Billion
2
2014 35 nm 900 mm 2
16 Billion
2 Gbits
10 Gbits
25 Gbits
70 Gbits
200 Gbits
1.6 GHz
2.0 GHz
2.5 GHz
3.0 GHz
3.5 GHz
1.5 V
1.2 V
0.9 V
0.6 V
0.6 V
130 W
160 W
170 W
175 W
180 W
2500
4000
4500
5500
6000
Predictions of the worldwide semiconductor / IC industry about its own future prospects... 13 CMOS Digital Integrated Circuits 3rd Edition
Shrinking Device Dimensions
YEAR TECHNOLOGY CHIP SIZE NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS
2002 130 nm 400 mm 400 M 2
2005 100 nm 600 mm 1 Billion 2
2008 70 nm 750 mm 3 Billion 2
2011 50 nm 800 mm 6 Billion 2
2014 35 nm 900 mm 2
16 Billion
2 Gbits
10 Gbits
25 Gbits
70 Gbits
200 Gbits
1.6 GHz
2.0 GHz
2.5 GHz
3.0 GHz
3.5 GHz
1.5 V
1.2 V
0.9 V
0.6 V
0.6 V
130 W
160 W
170 W
175 W
180 W
2500
4000
4500
5500
6000
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Increasing Function Density
YEAR TECHNOLOGY CHIP SIZE NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 2002 130 nm 400 mm 2
YEAR TECHNOLOGY CHIP SIZE NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 2002 130 nm 400 mm 400 M 2
2005 100 nm 600 mm 1 Billion
2
2008 70 nm 750 mm 3 Billion
2
2011 50 nm 800 mm 6 Billion
2
2014 35 nm 900 mm 2
16 Billion
2 Gbits
10 Gbits
25 Gbits
70 Gbits
200 Gbits
1.6 GHz 2.0 GHz
1.5 V 1.2 V
2.5 GHz 0.9 V
3.0 GHz 0.6 V
3.5 GHz 0.6 V
130 W
160 W
170 W
175 W
180 W
2500
4000
4500
5500
6000
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Decreasing Supply Voltage
YEAR TECHNOLOGY CHIP SIZE NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 2002 130 nm 400 mm 400 M 2
2005 100 nm 600 mm 1 Billion
2
2008 70 nm 750 mm 3 Billion
2
2011 50 nm 800 mm 6 Billion
2
2014 35 nm 900 mm 2
16 Billion
2 Gbits
10 Gbits
25 Gbits
70 Gbits
200 Gbits
1.6 GHz
2.0 GHz
2.5 GHz
3.0 GHz
3.5 GHz
1.5 V
1.2 V
0.9 V
0.6 V
0.6 V
130 W 2500
160 W 4000
170 W 4500
175 W 5500
180 W 6000
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5-layer cross-section of chip
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System-on-Chip Integrating all or most of the components of a hybrid system on a single substrate (silicon or MCM), rather than building a conventional printed circuit board. 1. More compact system realization 2. Higher speed / performance Better reliability Less expensive !
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New Direction: System-on-Chip (SoC)
ASIC Core
Memory
Communication
Analog Functions
Embedded Processor Core
Sensor Interface
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Products have a shorter life-cycle !
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Better strategy
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The Y-Chart
Notice: There is a need for structured design methodologies to handle the high level of complexity !
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Simplified VLSI Design Flow
Top-down
Bottom-up
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Structured Design Principles
Hierarchy: Divide and conquer technique involves dividing a module into submodules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. The hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction.
Regularity:
Modularity: The various functional blocks which make up the larger system must have well-defined functions and interfaces. Locality: Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible.
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Hierarchy of a 4-bit Carry Ripple Adder
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Hierarchy of a 16-bit Manchester Adder
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Hierarchy of a 16-bit Manchester Adder
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Hierarchy of a 16-bit Manchester Adder
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Hierarchy of a 16-bit Manchester Adder
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Regularity
2-input MUX
DFF
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VLSI Design Styles
FPGA
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Full Custom Design
Following the partitioning, the transistor level design of the building block is generated and simulated.
The example shows a 1-bit full-adder schematic and its SPICE simulation results.
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Full Custom Design
The main objective of full custom design is to ensure fine-grained regularity and modularity.
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Full Custom Design
A carefully crafted full custom block can be placed both along the X and Y axis to form an interconnected two-dimensional array.
Example:
Data-path cells
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Full Custom SRAM Cell Design
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Mapping the Design into Layout
Manual full-custom design can be very challenging and time consuming, especially if the low level regularity is not well defined !
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VLSI Design Styles
FPGA
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HDL-Based Design 1980s Hardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups. 1990s The increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design. 2000s Modern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements. 45 CMOS Digital Integrated Circuits 3rd Edition
HDL-Based Design The design is synthesized and mapped into the target technology. The logic gates have one-to-one equivalents as standard cells in the target technology.
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Standard Cells
AND 47
DFF
INV
XOR
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Standard Cells
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Standard Cells
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Standard Cells
Rows of standard cells with routing channels between them
