Layout-Dependent Proximity Effects in Deep Nanoscale CMOS
Layout-Dependent Proximity Effects in Deep Nanoscale CMOS
Layout-Dependent Proximity Effects in Deep Nanoscale CMOS
John V. Faricelli
Advanced Micro Devices, Inc., 90 Central St, Boxborough MA 01719, USA
[email protected]
I. INTRODUCTION
In the submicron regime, dimensions were large enough that
device behavior was largely independent of the neighborhood
of the device. As device scaling continued into the nanoscale
regime, the importance of modeling the device as well as its
surroundings became apparent. This paper consists of three
parts. First, it reviews the major features of modern CMOS
process technology that give rise to layout dependencies on
device behavior. Lithographic proximity effects have been
purposely omitted. Second, it discusses some practical issues
around implementation of layout-dependent models, and introduces the concept of a macro-model approach decoupled
from the underlying compact model. Finally, it provides mitigation strategies for minimizing layout-dependent effects.
active
area
island
Fig. 1. Ions implanted into the edge of the photoresist can scatter out of
the resist, increasing the implant dose of devices near the photoresist edge.
SA
SB
Stress
Stress
Position along OD
Position along OD
Fig. 6. Stress vs. position for two different lengths of OD (after [9]).
C. Stress Liners
Stress liners (also known as contact etch stop layers) are a
common method for introducing intentional uniaxial stress to
enhance device performance [10][14]. These layers are
typically silicon nitride films deposited by plasma-enhanced
chemical vapor deposition over the fabricated transistor gates.
Depending on the deposition conditions, either tensile or
compressive layers may be formed [18]. Since NMOS devices
prefer tensile stress in the channel direction while PMOS
devices prefer compressive stress, a dual-stress liner (DSL)
approach is used. TEM cross-sections of such a process are
shown in Fig. 7.
tensile
compressive
tensile
Fig 7.
compressive
DSLs with tensile layer over NMOS and compressive layer over
PMOS [12].
Material B Compressive
interface
SD m
+
p = 1 + +
L L + Lsd 2L + Lsd 1 + LSD
(1)
Fig. 12. Stress variation of eSiGe on both channel length and source/drain
lengths [28].
P _ STI = 1 +
m
WSTI
m _ STI
(2)
extraction if the reference layout minimizes the layoutdependent effects. For example, one could measure the middle
device fingers of a multi-stripe OD region, with neighboring
well, OD, and stress liner edges far away. The designer
should not assume, however, that the base device is always
one in which layout-dependent effects are minimized. After
performing parameter extraction, it is possible that the model
is re-normalized so that the nominal device resembles more
realistic layout, such as a ring oscillator used for model
validation.
Given the complex nature of layout-dependent modeling
with so many effects and parameters, the wise circuit designer
should experiment with the model by creating test layouts to
understand how important each effect is and to look for
anomalous behavior.
B. Extraction of Modeling Dimensions from Layout
The job of extracting the modeling dimensions from layout
is usually done as part of a layout-versus-schematic (LVS) run
performed before layout parasitic RC extraction. LVS tools
provide a rich set of geometric manipulation functions that can
measure the distances between the MOS device gate region
and well(s), OD edges, stress liner edges, etc. Designers
should be aware, however, that these measurements do not
come without a penalty in LVS runtime. Depending on the
size of the layout, extracting distances for layout-dependent
models can increase LVS runtime from minutes to many
hours. Often, runtime can be improved dramatically by
carefully limiting the search distance the LVS tool will use to
look for neighboring geometry. Checks on OD geometry are
particularly sensitive because of the large number of OD
shapes compared to well shapes.
C. Micro- vs. Macro-Modeling
of the layout-dependent modeling. Finally, the layoutdependent model could be implemented as a separate software
package and used in a variety of other tools, as will be
described in Section V-D.
The macro-modeling approach does have some limitations.
By using a per-instance current scale factor, we assume the
layout-proximity effects have the same quantitative effect in
the linear and saturation regions of the device. The use of a
threshold voltage shift implies that the change to the body
effect coefficient due to WPE can be ignored. For digital
circuits and many analog applications, however, this level of
accuracy has proven sufficient.
nwell
nwell
nwell
A more formal approach to layout guidelines is to incorporate them into the design rule check (DRC) deck. Transistors
are tagged with a special ID layer that triggers special rules to
reduce layout variability. While this method is satisfying because it is correct by construction, it can induce even more
layout bloat than guidelines.
B. Post-Layout Optimization
If we have a good set of layout guidelines coded as DRC
rules, it becomes possible to identify a problematic layout and
apply fixes. A simple example of this is shown in Fig. 15. Two
PMOS transistors are adjacent to an empty region. Since each
PMOS has an n-well boundary in close proximity, both
devices will be subject to WPE. A simple fix up rule would
close those gaps with n-well by merging the two n-wells.
nwell
nwell
Typical nwell
inside cell
std cell
boundary
Artificial OD
shapes
VI. CONCLUSION
A review of the sources of layout-dependent device variation has been presented: well-edge proximity, STI (LOD) effect, stress liner boundary effect, contact-induced stress variation, source/drain stressor volume effect, and adjacent OD effect. Methodologies for accounting for these effects at the
compact modeling level, given layout, have been described.
Being able to account for layout-dependent variation is not
enough, however, to ensure an efficient and timely design
process. Circuit and layout designers must work together
closely to account for these effects up front. This can be done
through layout guidelines, correct-by-construction techniques,
or by layout analysis tools that identify variation issues in the
early stages of layout. Failure to do so may result in unpleasant surprises and many cycles of revision late in the design.
ACKNOWLEDGMENTS
The author acknowledges the team of AMD and GLOBALFOUNDRIES colleagues who worked on modeling layoutdependent stress effects, in particular Akif Sultan (GF), Sushant Suryagandh (GF), Alvin Loke (AMD), Tom Daum
(AMD), and Greg Constant (AMD).
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