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    Multiprocessor Configuration

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    senthilvl
    Multiprocessor systems use multiple processors that execute instructions simultaneously. The 8086/8088 can implement three multiprocessor configurations: coprocessor, closely coupled, and loosely coupled. Closely coupled processors share memory, I/O, bus control logic, and a clock generator. Loosely coupled processors each have their own clock and memory but share a system bus, memory, and I/O. Bus arbitration schemes like daisy chaining, polling, and independent priority are used to control access to the shared bus to avoid contention.

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    Multiprocessor Configuration

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    senthilvl
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    Multiprocessor systems use multiple processors that execute instructions simultaneously. The 8086/8088 can implement three multiprocessor configurations: coprocessor, closely coupled, and loosely coupled. Closely coupled processors share memory, I/O, bus control logic, and a clock generator. Loosely coupled processors each have their own clock and memory but share a system bus, memory, and I/O. Bus arbitration schemes like daisy chaining, polling, and independent priority are used to control access to the shared bus to avoid contention.

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    Multiprocessor systems use multiple processors that execute instructions simultaneously. The 8086/8088 can implement three multiprocessor configurations: coprocessor, closely coupled, and loosely coupled. Closely coupled processors share memory, I/O, bus control logic, and a clock generator. Loosely coupled processors each have their own clock and memory but share a system bus, memory, and I/O. Bus arbitration schemes like daisy chaining, polling, and independent priority are used to control access to the shared bus to avoid contention.

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    Download as PDF, TXT or read online from Scribd
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    2K views7 pages

    Multiprocessor Configuration

    Uploaded by

    senthilvl
    Multiprocessor systems use multiple processors that execute instructions simultaneously. The 8086/8088 can implement three multiprocessor configurations: coprocessor, closely coupled, and loosely coupled. Closely coupled processors share memory, I/O, bus control logic, and a clock generator. Loosely coupled processors each have their own clock and memory but share a system bus, memory, and I/O. Bus arbitration schemes like daisy chaining, polling, and independent priority are used to control access to the shared bus to avoid contention.

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    The passage discusses different multiprocessor configurations including coprocessors, closely coupled, and loosely coupled systems and how they communicate and synchronize operations.

    Multiprocessor systems can be configured as coprocessors, closely coupled where processors share resources, or loosely coupled where each processor has its own resources and they communicate over a shared bus.

    Bus allocation schemes discussed include daisy chaining where masters pass bus access, polling where a controller grants access starting from highest priority, and independent bus access with separate request/grant lines.

    Part 5: MULTIPROCESSOR SYSTEMS

    REF: Microcomputer Systems: The 8086/8088 Family, Liu & Gibson, 1986 Multiprocessor Systems refer to the use of multiple processors that execute instructions simultaneously and communicate using mailboxes and semaphores Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations: 1. 2. 3. coprocessor (8087) closely coupled (8089) loosely coupled (Multibus)

    Coprocessors and closely coupled configurations are similar in that both the CPU and the external processor share: - Memory - I/O system - Bus & bus control logic - Clock generator Closely Coupled Configuration:

    CLOCK

    8086

    Bus C o n tro l L o g ic C op rocesso r or In d e p e n d e n t P ocesso r

    S y ste m B u s

    M em o ry

    I/O

    - Can have 8086, 8087 & 8089 running in prallel - How do we synchronize operations?

    Part 5: Multiprocessor systems 2

    Example: 8086/8087

    8086/8088

    C o p r o c e s s o r ( ie : 8 0 8 7 ) Monitor the 8086 or 8088

    ESC

    Wake up the coprocessor

    Execute 8086 instructions

    Deactivate the host's !TEST pin and execute the specified operation

    WAIT

    Wake up the 8086 or 8088

    Activate the !TEST pin

    Coprocessor cannot take control of the bus, it does everything through the CPU - 8089 shares CPU=s clock and bus control logic - communication with host CPU is by way of shared memory - host sets up a message (command) in memory - independent processor interrupts host on completion NOTE: Closely Coupled processor may take control of the bus independently Two 8086s cannot be closely coupled

    Part 5: Multiprocessor systems 3

    8086/8088

    Independent Processor (8089) Wait for request

    Set up message

    Fetch the message Wake up independent processor with OUT instruction

    Perform requested task

    Execute 8086 instructions

    Notify CPU of completion

    Wait for ready or interrupt request

    Part 5: Multiprocessor systems 4

    Loosely Coupled Configuration: (cont)


    - has shared system bus, system memory, and system I/O - each processor has its own clock as well as its own memory (in addition to access to the system resources, such as the system clock) - clocks are of similar frequency, but asynchro-nous towards each other - Used for medium to large multiprocessor systems - Each module is capable of being the bus master - Any module could be a processor capable of being a bus master, a coprocessor configuration or a closely coupled configuration. - No direct connections between the modules. Each share the system bus and communicate through shared resources. - Processor in their saeparate modules can simulateneously access their private subsystems through their local busses, and perorm their local data references and instruction fetches independandtly. This results in improved degree of concurrent processing. - Ecellent for real time applications, as separate modules can be assigned specialized tasks.

    ADVANTAGES:
    - high system throughput can be achieved by having more than one CPU. - The system can be expanded in modular form. Each bus master module is an independant unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system. - A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced - each bus master has its own local bus to access dedicated memory or IO devices so a greater degree of parallel processing can be achieved.

    PROBLEMS:
    - Bus Arbitration (contention): Make sure that only 1 processor can access the bus at any given time - must synchronize local and system clocks for synchronous transfer - requires control chips to tie into the system bus

    Processor Bus Access:


    - Needs some kind of priority allocation - Output a Bus Request >BRQ= to request the bus >> BRQ line goes to some controller - Input a Bus Grant >BGR= to gain access to bus >> BGR line from some controller - Output a Bus Busy >BBSY= signal to hold the bus

    Clocking:
    - take both clocks and derive a common clock or - take leading edge of one of the clocks >> can alternate or change for each individual operation (clock will jitter) (ie: local clock & system clock)

    Part 5: Multiprocessor systems 5

    BUS ALLOCATION SCHEMES:


    Daisy Chaining: Need a bus controller to monitor bus busy and bus request signals Sends a bus grant to a Master >> each Master either keeps the service or passes it on Controller synchronizes the clocks Master releases the Bus Busy signal when finished

    Master 1
    Bus Access Logic BGR

    Master 2
    Bus Access Logic

    ...

    Master N
    Bus Access Logic

    Bus Controller

    BRQ BBSY

    Part 5: Multiprocessor systems 6

    Polling: - Controller sends address of device to grant bus access - Can use priority resolution here: memory= highest priority - Highest priority is granted first, if it does not respond, then a lower priority is granted, and so on until someone accepts (ie: one request line, 3-bit grant line)

    Master 1
    Bus Access Logic

    Master 2
    Bus Access Logic

    ...

    Master N
    Bus Access Logic

    Bus Controller Rotating Encoder 0 to N

    BRQ BBSY

    Independent: - Each master has a request and grant line - Now just a question of priority - Could have fixed priority, rotating priority, etc. usually fixed because memory is desired to be the highest priority - Synchronization of the clocks must be performed once a Master is recognized - Master will receive a common clock from one side and pass it to the controller which will derive a clock for transfer - Can accurately predict calculations (since memory is always the highest priority)

    Part 5: Multiprocessor systems 7

    M a s te r 1
    B us A ccess L o g ic

    M a s te r 2
    B us A ccess L o g ic

    M a s te r N
    B us A ccess L o g ic

    Bus C o n tr o lle r

    Bus G r a n t1

    Bus G r a n t2

    Bus G r a n tn

    BRQ1 BRQ2 BRQn

    Bus B usy

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