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    ELEC9123 Design Tasks Week 7 9 Telecom

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    Sydney Finest
    This document outlines a telecommunications design project requiring students to design a phase-locked loop (PLL) based FM demodulator over 3 weeks. The PLL is used to track the changing input frequency of an FM signal, resulting in a fluctuating voltage output that can be tested by providing an FM radio signal input and connecting the output to a speaker circuit using MATLAB and the computer's I/O port.

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    ELEC9123 Design Tasks Week 7 9 Telecom

    Uploaded by

    Sydney Finest
    85 views1 page
    This document outlines a telecommunications design project requiring students to design a phase-locked loop (PLL) based FM demodulator over 3 weeks. The PLL is used to track the changing input frequency of an FM signal, resulting in a fluctuating voltage output that can be tested by providing an FM radio signal input and connecting the output to a speaker circuit using MATLAB and the computer's I/O port.

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    This document outlines a telecommunications design project requiring students to design a phase-locked loop (PLL) based FM demodulator over 3 weeks. The PLL is used to track the changing input frequency of an FM signal, resulting in a fluctuating voltage output that can be tested by providing an FM radio signal input and connecting the output to a speaker circuit using MATLAB and the computer's I/O port.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    85 views1 page

    ELEC9123 Design Tasks Week 7 9 Telecom

    Uploaded by

    Sydney Finest
    This document outlines a telecommunications design project requiring students to design a phase-locked loop (PLL) based FM demodulator over 3 weeks. The PLL is used to track the changing input frequency of an FM signal, resulting in a fluctuating voltage output that can be tested by providing an FM radio signal input and connecting the output to a speaker circuit using MATLAB and the computer's I/O port.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    ELEC9123: Design Proficiency (S1 2012)

    Telecommunications Design Project: Phase-locked-loop (PLL) based FM demodulator

    You are required to design the following task from Weeks 7 to 9. Design a Phase-locked-loop (PLL) based FM demodulator (see diagram below). When an FM signal is inputted to a PLL, the voltage controlled oscillator inside the PLL will track the input frequency as it changes. As a result, a fluctuating voltage will result, at the output of the PLL. Use MATLAB to provide the FM input to the PLL using the I/O port of the computer. Test your circuit with an FM radio signal and the output should be connected to a speaker circuit.

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