SONAR Systems and Underwater Signal Processing

This paper presents a recently introduced Kernel Machine, called Geometrical Kernel Machine, used to predict disruptive events in nuclear fusion reactors. The algorithm proposed to construct the Kernel Machine is able to automatically determine both the number of neurons and the synaptic weights of a Multilayer Perceptron neural network with a single hidden layer. It has been demonstrated that the resulting network is able to classify any finite set of patterns defined in a real domain. The prediction problem has been here modeled as a two classes classification problem. The geometrical interpretation of the network equations allows us both to develop the disruption predictor and to manage the so called ageing of the kernel machine. In fact, using the same kernel machine, a novelty detection system has been integrated in the predictor, increasing the overall system performance, and the reliability of the predictor.

The aim of this work is to show, to which the swings of arms are applied, is effective to perform vertical jumping movements by using a dynamometric platform. The force plate's analog to digital convector and range amplifier was electronically zeroed and calibrated prior to each subject's. In this paper two vertical jumping can be performed with and without an arm swing. The reported data and signals were obtained from an athlete who is familiar with performing a correct jump. The best jumping recording by the force platform are presented. Consequently, it is concluded that the swings of arms contribute to high-performance jumping movements.

The available instruction level parallelism allowed by current register file organizations is not always fully exploited by media processors when running a multimedia application. This paper introduces a novel register file organization, called multi-shared register file, that eliminates this superfluous instruction scheduling flexibility by reducing the number of read and write ports and partitioning the register file in a special ring structure. A parameterized generic VLIW architecture is used to explore different configurations of our proposed register file structure in terms of estimated silicon area, minimum clock period, estimated power consumption, and multimedia task processing performance. Moreover, a metric highly related to multimedia applications is introduced to study trade-offs between hardware cost and performance. The results show that by substituting a monolithic register file with an equivalent multi-shared register file, the estimated area and the power consumption are considerably reduced at the cost of a negligible performance degradation.

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation in a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and creating memory hierarchies, the off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm with a minimal increase in memory size.

Image processing is an important stage of every microarray experiment. Reliability of this stage strongly influences the results of data analysis performed on extracted gene expressions. Multiple methods related to array recognition, spot segmentation and measurement extraction have emerged in this area over past several years. Currently there are various commercial and freeware packages available, which perform microarray image analysis. This paper attempts to review microarray image analysis as a whole and to make some experimental comparison of several computational schemes for signal segmentation and measurement extraction. Also we provide a detailed discussion of automated image quality control for use with microarray images.

One of the most significant problems in many application areas is to extract the required signal from background noise.
Background noise is random, the occurrence of signal and the behaviour of signal are also random. Therefore, it is
practical to deal with the signal extraction problem using methods based on probability theory and statistical
estimation. That is to say that signal detection and parameter estimation problems are statistical hypothesis testing
problems in mathematical statistics. In this paper, signal and noise environment is encountered in active sonar system for
target detection. The optimum receiver is presented for range-Doppler-shift processing in a background-noise-limited
environment using linear frequency modulation pulse. FFT based implementation for target detection of active sonar
system using MATLAB has been shown here.

Inertial Measurement Unit (IMU) sensors are used widely in many different movable applications. Across many years, the improvements and applications of IMU have increased through various areas such as manufacturing, navigation, and robotics. This paper presents a literature review of several current IMU categories and applications. A few considerations on choosing an IMU for different applications are summarized and current methods being used to improve the accuracy of the output from IMU are also presented to avoid the errors that latest IMU is facing. Improvement methods include the control algorithms and type of filters for the sensor. Pros and cons of the types and algorithms used are also discussed in relation to different applications. 

In the course of a national research project, EADS Innovation Works has developed a waveform on a self-designed hybrid Software Defined Radio (SDR) platform, consisting of an FPGA (Xilinx Virtex 5) and a GPP (Intel Atom). The waveform realizes a video link between an Unmanned Ground Vehicle (UGV) and its Ground Control Station (GCS). This link is established indirectly with an Unmanned Aerial Vehicle (UAV) acting as a relay, in order to enable non-line-of-sight (NLOS) communication and to increase the communication range. Additionally, a direct video link from the UAV to the GCS is set up simultaneously as well as multiple low data rate control channels between the individual link partners. To cope with diverse operation areas, accompanied by a heterogeneous set of requirements, the waveform must offer outstanding adaptability and flexibility to maximize data rates in each scenario, while maintaining link robustness. The developed waveform is based on OFDM with freely customizable modulation parameters. Time Division Multiple Access (TDMA) is implemented on medium access layer to switch between the different users in the scenario (UGV, UAV, GCS). In this article, we give an overview of the waveform, its implementation on a hybrid platform and its validation for the intended field of application.

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.

Cartographie du couvert vegetal marin du golfe de gabes et mise en place d'un reseau de surveillance du de Posidonia oceanica. La cartographie a ete realise a travers 4800 stations d'observations directes par plongee au scaphandre autonome, apnee et ROV et camera sous marine, le recours au sonar a balayage lateral (swatch bathymetry) et l'imagerie satellitaire a permis de couvrir la totalite du golfe de la Chebba au nord a la frontiere Tuniso-Libyenne au sud, et du littoral a lisobathe -50m. La superfice couverte par nos travaux est estimee a 3.407.600 hectares, dont 1.152.900 ha sont occupes par la Posidonie soit 34% de cette aire prospectee, occupant ainsi la superficie la plus inportante de medietrranee. Pour assurere le suivi de cet importante biocenose marine littorale, nous avons balises 39 stations allant de -0.5 m a -36.7 m de profondeur. Sur une periode de 12 mois, ces 39 stations ont montre dans l'ensemble une regression de faible ampleur.

In this paper, a simulation framework that can be utilized during the simulation and algorithm selection phases of active sonar system development for surface and subsurface platforms, are described. HAVELSAN will have the capability to develop techniques and perform the performance analysis of
different methods that can be used in different areas like target detection sonars, torpedo sonars and mine hunting sonars with this simulation framework.

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time-through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources-and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm 2 . The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE

Цифровое формирование характеристики направленности гидроакустической антенны гидролокатора подводного робота во временной области Обработка гидроакустической информации выполняется во временной или спектральной области, причем последняя распространена очень широко. В любом случае предусматривается формирование характеристик направленности антенных устройств и моделирование алгоритмов обработки входных сигналов. Возможны два подхода к отработке алгоритмов. Первый состоит в обработке сигналов по выходам каналов антенны, и тогда необходимо вычислять и имитировать сигналы и помехи на выходах каналов антенны в соответствии с расчетными характеристиками направленности каналов и заданным распределением источников и параметров сигналов и помех. Второй состоит в генерации сигналов и помех в элементах антенной решетки, получении на выходах каналов процессов со свойствами, заданными на уровне элементов, и обработке суммарных сигналов во временной области. Приводятся формулы сигналов и помех для антенны мобильного подводного робота. направленность, гидроакустическая антенна, моделирование сигналов и помех, временная область, частотная область, формирование каналов антенны Digital forming of sonar antenna direction in time domain Hydroacoustic data processing is being performed in time or spectral domain, the spectral domain is being distributed more widely. In any case, there can be created formation characteristics of the antenna devices and modeling algorithms for processing input signals. There are two possible approaches to working out the algorithms. The first is to process the signals to the outputs of channels the antenna, and then you need to calculate and simulate the signal and interference at the antenna output channels in accordance with the calculated directional characteristics of channels and a given source distribution and the parameters of the signals and noise. The second is to generate signals and noise in the elements array, receiving the outputs of channel processes with the properties given on the item level, and the total processing of signals in time domain. The formulas of signals and interference antenna mobile underwater robot are included in this note.

The article describes a Field-Programmable Gate Array circuit for arbitrary-ratio re-sampling of signals in the Low Frequency to Very High Frequency bands, intended for Software Defined Radio applications. The proposed resampler allows the designer to control Spurious Free Dynamic Range while providing a simple, practical interface between the input and output clock domains that requires no additional clock, thus making it appropriate for FPGA clock-limited designs. Both upsampling and down-sampling variants are presented. Resource utilization for Field-Programmable Gate Array implementations is also discussed.

Recent years have witnessed an explosive growth in multimedia streaming applications over the Internet. Notably, Content Delivery Networks (CDN) and Peer-to-Peer (P2P) networks have emerged as two effective paradigms for delivering multimedia contents over the Internet. One salient feature shared between these two networks is the inherent support for path diversity streaming where a receiver receives multiple streams simultaneously on different network paths as a result of having multiple senders. In this paper, we propose a network coding framework for efficient video streaming in CDNs and P2P networks in which, multiple servers/peers are employed to simultaneously stream a video to a single receiver. We show that network coding techniques can (a) eliminate the need for tight synchronization between the senders, (b) be integrated easily with TCP, and (c) reduce server's storage in CDN settings. Importantly, we propose the Hierarchical Network Coding (HNC) technique to be used with scalable video bit stream to combat bandwidth fluctuation on the Internet. Simulations demonstrate that under certain scenarios, our proposed network coding techniques can result in bandwidth saving up to 60% over the traditional schemes.

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semiconductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits. This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 µm by 171.8 µm with average power dissipation at 815.1 µW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 µm by 139.3 µm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 µm by 171.8 µm, was designed and implemented using TSMC 0.35 µm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.

This paper deals with the problem of estimating the directions of arrival (DOA) of multiple source signals from a single
observation vector of an array data. In particular, four estimation algorithms based on the theory of compressed sensing
(CS), i.e., the classical ℓ1 minimization (or Least Absolute Shrinkage and Selection Operator, LASSO), the fast smooth ℓ0
minimization, and the Sparse Iterative Covariance-Based Estimator, SPICE and the Iterative Adaptive Approach for
Amplitude and Phase Estimation, IAA-APES algorithms, are analyzed, and their statistical properties are investigated
and compared with the classical Fourier beamformer (FB) in different simulated scenarios. We show that unlike
the classical FB, a CS-based beamformer (CSB) has some desirable properties typical of the adaptive algorithms
(e.g., Capon and MUSIC) even in the single snapshot case. Particular attention is devoted to the super-resolution
property. Theoretical arguments and simulation analysis provide evidence that a CS-based beamformer can achieve
resolution beyond the classical Rayleigh limit. Finally, the theoretical findings are validated by processing a real sonar
dataset.

The exploration of oceans and sea beds is being made increasingly possible through the development of Autonomous Underwater Vehicles (AUVs). This is an activity that concerns the marine community and it must confront the existence of notable challenges. However, an automatic detecting and tracking system is the first and foremost element for an AUV or an aqueous surveillance network. In this paper a method of Kalman filter was presented to solve the problems of objects track in sonar images. Region of object was extracted by threshold segment and morphology process, and the features of invariant moment and area were analysed. Results show that the method presented has the advantages of good robustness, high accuracy and real-time characteristic, and it is efficient in underwater target track based on sonar images and also suited for the purpose of Obstacle avoidance for the AUV to operate in the constrained underwater environment.

Recent years have witnessed an explosive growth in multimedia streaming applications over the Internet. Notably, Content Delivery Networks (CDN) and Peer-to-Peer (P2P) networks have emerged as two effective paradigms for delivering multimedia contents over the Internet. One salient feature shared between these two networks is the inherent support for path diversity streaming where a receiver receives multiple streams simultaneously on different network paths as a result of having multiple senders. In this paper, we propose a network coding framework for efficient video streaming in CDNs and P2P networks in which, multiple servers/peers are employed to simultaneously stream a video to a single receiver. We show that network coding techniques can (a) eliminate the need for tight synchronization between the senders, (b) be integrated easily with TCP, and (c) reduce server's storage in CDN settings. Importantly, we propose the Hierarchical Network Coding (HNC) technique to be used with scalable video bit stream to combat bandwidth fluctuation on the Internet. Simulations demonstrate that under certain scenarios, our proposed network coding techniques can result in bandwidth saving up to 60% over the traditional schemes.

ABSTRACT The narrow subcarrier spacing and wide bandwidth arrangement in the LTE downlink produce a vulnerability to sample clock mismatch between the transmitting and receiving data converters. Without high precision sampling clock frequencies, a high level of inter-carrier interference (ICI) is introduced, yielding undesirable performance. In this article, a method to jointly estimate and correct sampling frequency mismatch is proposed. The proposed method uses information already known to the receiver, operates strictly in the time domain and does not require the aid of pilot symbols or other frequency domain information. The method allows clocks with lower precision to be used with minimal performance degradation. Results are presented using MATLAB simulation as well as an FPGA hardware implementation.

Abstract As displays become less expensive and are incorporated into more and more devices, there has been an increased focus on image resizing techniques to fill an image to an arbitrary screen size. Traditional methods such as cropping or resampling can ...

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person's identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/ her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)-SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person's identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload com-putations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and applicationspecific requirements.

The codebook model-based approach, while ignoring any structural aspect in vision, nonetheless provides state-of-the-art performances on current datasets. The key role of a visual codebook is to provide a way to map the low-level features into a fixed-length vector in histogram space to which standard classifiers can be directly applied. The discriminative power of such a visual codebook determines the quality of the codebook model, whereas the size of the codebook controls the complexity of the model. Thus, the construction of a codebook is an important step which is usually done by cluster analysis. However, clustering is a process that retains regions of high density in a distribution and it follows that the resulting codebook need not have discriminant properties. This is also recognised as a computational bottleneck of such systems. In our recent work, we proposed a resourceallocating codebook, to constructing a discriminant codebook in a one-pass design procedure that slightly outperforms more traditional approaches at drastically reduced computing times. In this review we survey several approaches that have been proposed over the last decade with their use of feature detectors, descriptors, codebook construction schemes, choice of classifiers in recognising objects, and datasets that were used in evaluating the proposed methods.

High performance portable systems for real-time video/image analysis continue to demand high processing power and memory bandwidth. In embedded systems such as digital still cameras, camcorders, and camera phones, the expected performance must be delivered while meeting size, weight, and power constraints. A well-designed system should include analyses of its memory subsystem as well as the computation platform. This paper focuses on a streaming memory subsystem that leverages deterministic memory access patterns. We formalize the notion of stream descriptors as a means to define these stream access patterns and to improve memory access efficiencies by discovering locality between different data streams. Data movement for a real-time image analysis applications are performed, showing favorable bandwidth savings using stream descriptors.

While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {−1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.

In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical VLIW-based DSP, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors. c 2007 Kluwer Academic Publishers. Printed in the Netherlands. paper.tex; 5/10/2007; 17:06; p.1

Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.

Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence of instructions needed to emulate these complicated bit operations. As these bit manipulation operations are relevant to applications that are becoming increasingly important, we propose direct support for them in microprocessors. In particular, we propose fast bit gather (or parallel extract), bit scatter (or parallel deposit) and bit permutation instructions (including group, butterfly and inverse butterfly). We show that all these instructions can be implemented efficiently using both the fast butterfly and inverse butterfly network datapaths. Specifically, we show that parallel deposit can be mapped onto a butterfly circuit and parallel extract can be mapped onto an inverse butterfly circuit. We define static, dynamic and loop invariant versions of the instructions, with static versions utilizing a much simpler functional unit. We show how a hardware decoder can be implemented for the dynamic and loop-invariant versions to generate, dynamically, the control signals for the butterfly and inverse butterfly datapaths. The simplest functional unit we propose is smaller and faster than an ALU. We also show that these instructions yield significant speedups over a basic RISC architecture for a variety of different application kernels taken from applications domains including bioinformatics, steganography, coding, compression and random number generation.

The Joint Collaborative Team on Video Decoding is developing a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50%. In order to fulfill the computational demands of the new standard, in particular for high resolutions and at low power budgets, exploiting parallelism is no longer an option but a requirement. Therefore, HEVC includes several coding tools that allows to divide each picture into several partitions that can be processed in parallel, without degrading the quality nor the bitrate. In this paper we adapt one of these approaches, the Wavefront Parallel Processing (WPP) coding, and show how it can be implemented on multi-and many-core processors. Our approach, named Overlapped Wavefront (OWF), processes several partitions as well as several pictures in parallel. This has the advantage that the amount of (thread-level) parallelism stays constant during execution. In addition, performance and power results are provided for three platforms: a server Intel CPU with 8 cores, a laptop Intel CPU with 4 cores, and a TILE-Gx36 with 36 cores from Tilera. The results show that our parallel HEVC decoder is capable of achieving an average frame rate of 116 fps for 4k resolution on a standard multicore CPU. The results also demonstrate that exploiting more parallelism by increasing the number of cores can improve the energy efficiency measured in terms of Joules per frame substantially.

There has been much study of ASIC neurocomputers but, in comparison, relatively little for FPGA neurocomputers. Nevertheless, with current (and future) dense, high-speed FPGAs, the latter are now viable and will be more successful than the former. In this paper, we discuss a technique for low-error, high-speed implementations of the sigmoid function in such FPGAs. This function is commonly used as an activation function in artificial neural networks, but it also has applications in many other areas. Our results compare very favourably with others that have been reported in the published literature.

The music plays a vital role in the life of humans. People listen to music for fun, entertainment, relaxation and mental peace. The music can be applied for recovering from illness and physical fatigues. The Raga is considered as a basic unit of Indian Classical Music. The behavior of the Raga is recognized by Swara (notes) movement. The Raga may be sung as per environmental situations, events, and emotions at the particular time. In this paper, the properties of Indian Classical Music are listed which are useful for Raga identification. The various feature extraction techniques from Digital Signal Processing and Raga Identification techniques for classifying the Indian Classical Music are discussed. The paper provides several challenges for the future work.

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a Bsweet spot^for architectural research.

An audio fingerprint is a compact content-based signature that summarizes an audio recording. Audio Fingerprinting technologies have attracted attention since they allow the identification of audio independently of its format and without the need of meta-data or watermark embedding. Other uses of fingerprinting include: integrity verification, watermark support and content-based audio retrieval. The different approaches to fingerprinting have been described with different rationales and terminology: Pattern matching, Multimedia (Music) Information Retrieval or Cryptography (Robust Hashing). In this paper, we review different techniques describing its functional blocks as parts of a common, unified framework.

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6-based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.

Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver. To extract maximum performance from a MIMO system, a computationally intensive search based detector is needed. To meet the challenge of MIMO detection, typical suboptimal MIMO detectors are ASIC or FPGA designs. We aim to show that a MIMO detector on Graphic processor unit (GPU), a low-cost parallel programmable co-processor, can achieve high throughput and can serve as an alternative to ASIC/FPGA designs. However, careful architecture aware software design is needed to leverage the performance offered by GPU. We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGAlike performance and handle different configurations in software on GPU. The proposed design can be used to accelerate wireless physical layer simulations and to offload MIMO detection processing in wireless testbed platforms.

In this paper, we review recent developments in VLSI architectures and algorithms for efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic principle behind the lifting based scheme is to decompose the finite impulse response (FIR) filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementations have many advantages, and have recently been proposed for the JPEG2000 standard for image compression. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we provide a survey of these architectures for both 1-dimensional and 2-dimensional DWT. The architectures are representative of many design styles and range from highly parallel architectures to DSP-based architectures to folded architectures. We provide a systematic derivation of these architectures along with an analysis of their hardware and timing complexities.

A library of on-line arithmetic structures is presented. Their ability to produce and consume the most significant digit first allows subsequent computations to begin earlier, shortens the execution time of variable precision and composite operations, and simplifies interconnection networks which can help preserve high clock rates in large digit-serial designs. More importantly, designers can interconnect individual units without designing intermediate structures to reformat data, a luxury that is currently unavailable to FPGA designers wishing to use bit-serial arithmetic. The on-line structures introduced are small, and can be easily combined to yield more powerful blocks. The library's applicability to signal processing applications is demonstrated with the DFT, DCT, and FIR filter. Results indicate high area efficiency and rapid execution speed.