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Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Digital Front-End for Software Defined Radio Wideband Channelizer Adedotun O. Owojori Temidayo O. Otunniyi Erastus O. Ogunti Federal University of Technology, Akure Dept of Elect/Elect School of Eng & Eng Technology Federal University of Technology, Akure Computer Resource Center Vice Chancellor’s Office Federal University of Technology, Akure Dept of Elect/Elect School of Eng & Eng Technology ABSTRACT This paper focused on the design of a digital front end channelizer useful in most software defined radios with the aim of exploiting the vast resources of digital signal processing which helps to achieve a portable, long lasting with extraordinary computational complexity software application that is capable of running at a lower power budget. Three channelization algorithms: per-channel, pipeline frequency transform and poly-phase fast Fourier transform uniform channelization algorithms were reviewed and designed for FM receivers using Altera Digital Signal Processing tool box in MATLAB/Simulink environment. The performance evaluation of the three algorithms were carried out with the estimation of the multiplication per input samples of operation of the system, signal strength level or signal to noise ratio and the compilation time of each algorithm. The result showed that the polyphase fast Fourier transforms and pipeline frequency transform had 24% decrease in computational requirement compared to per-channel which suggest a lower power consumption. Whereas, polyphase fast Fourier transform out performs pipeline frequency transform in terms of silicon cost. General Terms Algorithms, Fast Fourier Transform, Digital Signal Processing, Software Defined Radio, Digital Front End. Keywords Channelization, Multirate Digital Filter Bank, Software Defined Radio, Digital Down Conversion. 1. INTRODUCTION The digital front end section of Software Defined Radio (SDR) receiver system is one of the recent research areas in communication engineering which as well has found application in many other fields such as smart systems in power engineering [7]. The most important reasons for such system are: ability to easily incorporate with multi- media functionalities, interface with other digital devices, compute at a reasonably fast speed depending on the system channelization architecture [1,9], support multiple protocols, prototype and fix bugs for next generation protocol implementation [14]. The practical application of the SDR, as made evident in telecommunication stations, include: Global System for Mobile Communication (GSM): 2G/ 3G/ 4G radio, IS-95, Universal Mobile Telecommunication Standard (UMTS), radio and television broadcast for commercial and military use [8,13] and are characterized with different center frequency, channel bandwidth, noise level, interference requirements, and transmit spectral mask. The most important aspect of the SDR architecture is the software part which handles the digital signal processing of the digital front end which so far has incorporated different channelization algorithms both uniform and non-uniform to achieve an optimum system in terms of computation and efficiency. The wideband channelizer decomposes the digital Intermediate Frequency (IF) input signals into separate baseband output signals. Examples of major uniform channelization algorithms used are per-channel, pipeline frequency transform and poly-phase fast Fourier transform, while farrow structure filter bank is used for non-uniform algorithm. More specifically, the channelization technique is composed of the downconversion and filtering of every communication channels followed by sample rate conversion (SRC) of each channel from a high sampling rate to a lower rate so that the baseband signal can be extracted at less computational complexity. The multirate multistage technique was also adopted to achieve an optimized channelization algorithm. The digital section of SDR receiver receives IF wideband digital signal bandwidth from the ADC for complex baseband signals channelization. To reduce the high sample rate of the digital signal, an intermediate SRC is applied to extract channels up to the baseband signal bandwidth according to Nyquist criterion. These three (3) algorithms were simulated using Altera Digital Signal Processing (DSP) tool box in MATLAB/ Simulink environment for a proposed FPGA processor. 2. RESEARCH METHOD The whole system is analogous to that of superheterodyne receiver architecture as shown in Fig 1. Based on this architecture, the RF analogue signal is been modelled based on available real FM channels by the use of MATLAB/ Simulink software. This RF signal enters the receiver through the antenna which is either incorporated into the FPGA board or designed on an expandable circuit before its incorporation into the FPGA board. Instead of dealing with high dynamic ranges or requirements and sampling frequency required for the simulation of the RF signals based on Nyquist criterion in the radio frequency (RF) section of the radio receiver, the intermediate frequency (IF) is used which is derived from mixing the signal RF with a local oscillator signal of a given fixed/ variable frequency. 25 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 1: The block diagram of the super- heterodyne radio receiver The IF obtained allows easy digitization of the signals by using an analogue to digital converter (ADC) capable of running at a sampling time of greater or twice the IF with maximum dynamic range of 100 MHz [7]. This is contrary to the direct down conversion of multiband RF to band pass signals as described by [3] where under sampling is used. 2.1 Signal Generation and Modelling The communication signals are modelled to mimic real life radio systems, simulated in preparation for real life implementation. Considering an analogue passband FM signal, x(t), obtained when an audio signal input, u(t), mixes with a carrier signal, v(t), generated by a local oscillator (LO) at the transmitting end. An outcome is obtained which is a varied frequency of the carrier wave, fc, about a mean value as a function of the magnitude of the baseband audio frequency, fa, as shown in Figure 2. x(t) = Kc cos(2π t + kf sin2π t) ∆f = kf * Kɑ µ= where fc is the carrier frequency. kf is the modulation constant or index. ∆f is the frequency deviation, representing frequency variation from the carrier frequency. µ is the phase deviation of the FM signal or the modulation index which has values from 1 to 5 [12] The sample time for the audio signal or RF front end signal is taken as greater or equal to the inverse of twice maximum frequency of the FM range or the carrier frequency. The modulating signal specification as illustrated in the Table 1 is allowed to pass through frequency modulation scheme which shifts the baseband signal and centers it at passband (carrier frequency). Although in communication receiver application, the RF input at the antenna involves several channels of different carrier frequencies and amplitude in the presence of channel noise which are summed together. Table 1: Modulating signal specification Source sine wave Maximum audio frequency 15 kHz Signal amplitude 1 (+27 dB) Sampling time 2.5e-9 The requirements of sound quality for commercial radio stations require a bandwidth of about 15 kHz (Table 1). The Carson’s rule was used to estimate the available channel bandwidth needed to avoid channel interference as expressed below which shows that for FM radio broadcasting, the allocated channel band-width is approximately 200 kHz. Channel spacing bandwidth = 2 (fdev + fmax) …… where fdev is the maximum frequency deviation (75 kHz) fmax is the highest base band signal frequency (15 kHz) Gaussian noise channel added to the sum of FM signals obtained a signal to noise ratio (SNR) of approximately 20 dBm. The gaussian noise used generates discrete-time white noise which is random over the passband frequency spectrum. This normalizes the noise level about a mean of zero dBm point over the passband frequency. 2.2 Analogue Front End Design The analogue front end section of a radio receiver also called the RF section describes the operation of the low noise amplifier (LNA), and the demodulation section. The signal incident to the antenna is of small magnitude (i.e. weak signal strength) because of the presence of noise in the channel which will be compensated for with the RF amplifier but in any case it will be received by the receiver. The RF amplifier forms one of the analogue front end components which provides initial gain and selectivity and minimizes radiation of 26 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 2: Internal structure of a Frequency Modulator in MATLAB/ Simulink the local oscillator and also helps to eliminate image and noise frequencies. The LNA block in the MATLAB/ Simulink environment is obtained from the Simscape library which requires input, output port and the RF configuration block as illustrated in Fig 3. These ports are used to specify the input and output impedance matching from the antenna to the LNA and from the LNA to the mixer, which is usually 50 ohms. The other requirements for LNA in most communication system is that the noise figure must be less than 3 dB and also the gain must have at least noise figure plus 10 for the device to pick up the signal over its internal generated noise [5]. In the design the following requirements were used as shown in Table 2. Table 2: LNA design requirements Input and output impedance 50 Ω Max input carrier frequency 108.1 MHz LNA gain 20 dB Noise figure 2 IP2 and IP3 Infinity Output signal Real passband (88.1 MHz to 108.1 MHz) The incoming carrier signal frequency components of FM are observed to be high compared to the speed/sampling frequency of most ADCs used. Therefore, analogue signal frequency shift to a lower frequency band is required. The local oscillator signal is represented with real cosine wave having sampling time as the RF signal. fLO = fRF ± fIF The presence of image frequency which has signal frequency greater than the LO frequency mixes with the LO frequency to give a mixer output equal to the IF. fimage = fRF + 2fIF …………………… The intermediate frequency (IF) design stage is characterized with multi- harmonics obtained by the frequency sum and difference between the received signal and the local oscillator signal [2]. The difference frequency IF is one important output frequency used in the design process, which is the frequency ranging from 10.7 MHz to 30.7 MHz. The purpose of the design is to replace all analogue components with digital components. Therefore, the low pass filter required at the IF end is preferably a digital low pass filter which must convolve with a discrete IF signal. Besides, all channelization tasks are performed digitally; in other words, there must be a signal conversion from analogue to digital which requires a rate converter from the initial sampling rate of 400 MHz to 64 MHz which is placed immediately after the mixer output. 2.3 Digital Front End Design The analogue to digital conversion procedure involves the conversion of continuous time signals into a discrete time signal at instant multiples of the sampling interval Ts and can be expressed in three steps a. Sampling b. Quantization c. Coding Quantization step of the ADC can be expressed as: α= …………………………… where Vfs is the full scale peak voltage α is the quantization step or resolution B is the bit of the ADC Therefore the Quantization signal to noise power ratio is given as: S/N = ……………… In decibel, the ideal form of signal to noise ratio is given as SQNR (dB) = 1.76 + 6.02B …… According to [4], the quality of the output of the ADC is usually measured by the signal to quantization noise ratio, which is the ratio of the signal power to the noise power. The ADC for receiver requires 100 dB or more for the dynamic range characteristics and the higher the bit (B) of the ADC, the better the resolution of the signal been digitized. 27 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 3: Block diagram illustrating LNA design This digitized signal has a frequency of 10.7 MHz corresponding to the IF of commercial FM broadcast station. It is important that the ADC be sampled based on Nyquist criterion fs ≥ 2*fm which helps to remove aliasing or signal distortion. This justifies the use of sampling rate of 64 MHz for the simulation. The discrete data is obtained by multiplying the input signal, xc(t), with a Dirac delta function δ(t-nTs) at specific intervals as shown in Figure 4 [15]. As δ(t-nTs) is 1 at t-nTs = 0 and otherwise 0, the attained signal is: x[n] = xc(t - nTs) The output of the ADC (discrete IF signals) is then convolved with the low pass digital filter frequency response to eliminate the sum IF. The response of the system to is the corresponding sum of weighted outputs, y(n), therefore This illustrates a finite causal system with finite numbers of delays which connotes a finite number of storage locations to be practically implemented. The MATLAB/Simulink implementation of the FIR filter involves using the digital filter design and analysis toolbox (FDATool) characterized with a linear phase in the pass band region with the aim of suppressing or attenuating all other possible signals in the stop band region. Based on the design specifications, two different filter configurations were observed. The first having a bandpass equiripple filter of minimum order which allows only digital signals of 10.7 MHz to pass while it attenuates the other frequency. This convention allows system control of individual channels from the local oscillator in the analogue front end. At the output of this filter only a single NCO is required which mixes the signal to baseband. The multirate multistage down sampling filters helps to filter out the high frequency while retaining the baseband signal as well as reduce the sampling rate. Fig 4: The Discrete Data Representation of the Continuous Signal [15]. The second configuration utilizes also a bandpass equiripple filter of minimum order which allows signals within the range of 10.7 MHz and 30.7 MHz to be selected while attenuating all other frequencies. This configuration was adopted in the channelization algorithm design since multiple channels are needed to be extracted within the frequency range therefore, a digital control NCO is needed for such implementation. The sampling frequency of the filter is 64 MHz with a stop band attenuation of 60dB. The digital down converter (DDC) is an important section in any digital radio which performs frequency translation from 10.7 MHz to baseband at a high input sample rates. The convolved output of the input digital signal and the digital 28 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org filter mixes with a numerical controlled oscillator (NCO) signal having a frequency fLO of 10.7 MHz and sampling rate of 64 MHz to generate a sine, cosine or complex wave. fNCO = fBB ± fIF …………………… The NCO is capable of generating a multichannel real or complex sinusoidal signal depending on a real input IF signal. These NCO signals have independent frequency and phase in each output channel with amplitude equal to 1. The output NCO block allows the adder’s numeric values to overflow and wrap as shown in Fig 5. The lookup table is constructed from a double precision floating point values with maximum amount of precision output of 53 bits. Fig 6 illustrates a 10.7 MHz NCO signal generated. At the output of the mixer two frequencies were generated but, the one that interest the designer is that centered at 0 Hz. The presence of a low pass filter at the output of the mixer helps to eliminate frequency at 21.4 MHz and above. 2.4 Digital Rate Conversion Design Based on the fact that the transition bandwidth (∆F) of the baseband signal is small compared to the sample rate fs (64 MHz) therefore to realize a filter to this precision, the order of the filter or number of coefficients is increased. In order to process this large number of coefficients with considerable word length processing and clock rate for a single channel filtering in a direct implementation by means of a conventional FIR filter, a lot of effort and high cost of multipliers would be required. To overcome this, a lowpass filter which does channel filtering on the baseband signal is combined with a down sampler (decimation) in a multi-stage pattern [11]. The multi stage decimation factor is such that it is not a prime number that is, it can be written as a product of individual decimation factors (M=Π mi =m1 *m2*….mk). The total decimation factor can be calculated as: M= The cascaded integrator comb filter (CIC filter) transfer function is expressed below: ……………………… where fsinp is the input sampling frequency from the ADC (64 MHz) fsout is the desired sampling frequency for the output signal (250 kHz). The desired sampling frequency (250 kHz) is a function of the channel spacing of the FM spectrum (0.1 MHz) in which according to Nyquist criterion should be twice the channel spacing. The total decimation factor equals 256. The oversampling ratio (OSR) of the signal, which is the ratio between the sample rate, fs, of the signal and the band width (∆F) of the signal of interest, is typically high in the first few stages of the multirate filter as a result of a large transition band and narrow stop band. A comb filter which is sufficient enough to attenuate the narrow stop band is employed. where M is the sample rate reduction factor and R is the order of the CIC filter. The CIC is the first decimation block with flexible multiplier free filter suitable for hardware implementation that can handle arbitrary large rate changes. This CIC is made from a cascade or chain of an integrator and comb filter. The comb filter requires no multipliers, but uses adders, subtractors and registers. The filter is also known for performing high decimation sufficient to 4-times of the Nyquist rate according to Hogenauer [6]. A single stage integrator is expressed as: y[n] = y[n-1] + x[n] The comb filter runs at the same high sampling rate for a given rate change M which is an odd symmetric FIR filter and a single stage comb is expressed as: y[n] = x[n] - x[n-RM] where R is called a differential delay which can be any positive integer, but it is usually limited to 1 or 2 still at the sampling rate fs. When R and M equals unity, the power response depicts a high pass function with 20 dB per decade which is an inverse of an integrator. When RM ≠ 1, the power response show similarities with the raised cosine form which has its RM cycle from 0 to 2 . In MATLAB/Simulink implementation, the CIC filter block was selected from the DSP system Toolbox. The CIC decimation factor (m1) was calculated to be 64 by using the formula below: m1= 2M where ∆F = transition frequency and M is the overall decimation factor. The differential delay was set to 1 and the passband frequency as 0.1 MHz at a stopband attenuation of 60 dB. In all the three algorithms studied, the CIC filter is common to all. The per-channel algorithm, after the CIC utilizes a direct form inverse sinc FIR lowpass single rate filter after which it is down sampled by a factor of 4. This low pass filter helps to compensate for the pass band drop caused by the sinc-like response of the CIC. The polyphase concept is used in the pipeline frequency transform channelization algorithm, only that it is in an hierarchical form which uses the inverse sinc and the final lowpass filter each decimated by 2 as in polyphase fast Fourier transform channelization algorithm 29 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 5: Internal structure of NCO in MATLAB/Simulink Fig 6: Spectrum illustrating a 10.7 MHz output NCO signal 2.5 Polyphase Decimation The polyphase decimation approach introduces a more efficient way of representing the multistage rate conversion filters. This allows filter output samples that are necessary to be retained where others are discarded. In order words, a signal that is down sampled by a factor M will have M different phasing alignments between the filter output samples with respect to the filter coefficient [10]. Given an M -1 decimator, with a filter response of h(n). The filter only computes the outputs: y[0], y[M], y[2M], … where we observe that y(n) is a product of x(n) and h(n). Therefore, it follows that the input signal can be split into M separate sequences x0(n) = {x[0], x[M], x[2M]…} x1(n) = {x[1], x[M+1], x[2M+1]…} … The same is applicable to h(n) h0(n) = {h[0], h [M], h [2M]…} h1(n) = { h [1], h [M+1], h [2M+1]…} … If the filter has n-length, then the Z- transform of its transfer function is H(z) = h(0) + h(1)z-1 + h(2)z-2 + h(3) z-3 + … + h(n) z-n This can be rearranged in the polyphase realization form as shown in Fig 7; assuming M = 2 30 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org H(z) = (h(0) + h(2) z-2 + h(4) z-4 + h(6) z-6 + … ) +(h(1) z-1 + h(3) z-3 + h(5) z-5 + h(7) z-7 + … ) H(z) = E(z2) + z-1E(z2) H(z) = (h(0) + h(2) z-2 + h(4) z-4 + h(6) z-6 + … ) +z-1 (h(1) + h(3) z-2 + h(5) z-4 + h(7) z-6 + … ) Fig 7: decimation by 2 polyphase decomposition In MATLAB/Simulink implementation, the polyphase decimation concepts were used with pipeline frequency transform channelization algorithm and polyphase fast Fourier transform channelization algorithm within the inverse sinc lowpass filter and the final lowpass filter. 2.6 Computational Complexity Estimation The computational complexity estimates of the three channelization algorithms are obtained by using the multiplications per input sample of operation of the system. This requires a correct estimation of the filter order or length. The filter order (N) for an FIR lowpass (Equiripple) digital filter is expressed using the developed optimized Kaiser’s formula expressed as: N= The peak passband ripple and stopband ripple are expressed as and with the passband edge and stop band edge normalized with the sampling. The filter length therefore is expressed as the filter order plus one (N+1); this is used to express the computational burden or complexity of the system. Multiplication per input sample = (N + 1) * multiplications per second in 3. RESULTS AND ANALYSIS In order to obtain all these results certain settings are observed on the MATLAB/ Simulink environment: a. b. First, a DSP Builder 12.1 was installed on MATLAB R2013a In the Simulink environment, the data import/ export which was saved on the workspace must have a structure with time format The output spectrum of the two filter configurations for perchannel algorithm is given in Fig 8. Fig 8(a) shows that the digital filter signal passes 10.7 MHz intermediate frequency signal while other signals at fractions or harmonics of the individual intermediate frequencies at different sample rates are attenuated to a level approximately equal to -40 dBm; therefore, the difference between the noise floor and the signal strength at 10.7 MHz gives an SNR of 70 dBm. Fig 8(b) shows that the spectrum from 10.7 MHz to 30.7 MHz which corresponds to 20 MHz FM spectrum passed through the filter. The spectrum shows signal attenuation equal to -40 dBm with an SNR of 70 dBm. 3.1 Per-Channel This model gives output for 5 different channels with signal strength of about 120 dBm range on decimation by 128 within a frequency band of 100 kHz and when down sampled further by 2, the signal strength reduces to 100 dBm for a frequency range of 100 kHz as illustrated in Fig 9. This gives an estimate of the power consumption of the system. Since the CIC is common to the three algorithms, the computational complexity is estimated based on the inverse sinc final lowpass filter. 31 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 8: double sided spectrum of the two digital filter configurations for per-channel algorithm The algorithm for the 5 different channels has the fastest compilation time compared to pipeline frequency transform and polyphase fast Fourier transform algorithm. A delay time of 3 seconds was observed before the start of the main compilation, then completely acquires the data needed within 12 to 19 seconds and ends the simulation at 36 seconds. The inverse sinc filter has a multiplication per input sample, addition per input sample, number of adders and multiplier of 29M multiplications/sec (mps), 28M multiplications/ sec (mps), 28, 29 respectively. This is because a down sampler is introduced after a single rate type minimum order filter. If the filter computation had undergone polyphase multi-stage decimation the multiplication per input sample would have been 7,250, 000 mps therefore saving about 21,750,000 mps and causing a reduction in computation of almost 4: 1. decimation at the output stage, achieved a reduced computation algorithm for pipeline frequency transform channelization model. The outputs of each channel are as described in Fig 10, 11 and 12. The signal strength of about 100 dBm range was obtained for the decimation by 128 within a frequency band of 100 kHz on the first, fourth and fifth channel while for the second and third channel, the signal strength is about 80 dBm. Further down sampling by 2 reduces the signal strength of the first, fourth and fifth channel to approximately 80 dBm for a frequency range of 100 kHz while, the second and third channel has its signal strength reduced to approximately 60 dBm. Pipeline frequency transform for 5 different channels has the longest compilation time compared to per-channel and polyphase fast Fourier transform algorithm. 3.2 Pipelined Frequency Transform (PFT) The NCO configuration with the polyphase multi-stage Fig 9: per-channel output after the decimation by 128 and 256 At the start of the simulation, a delay time of 10 seconds was observed before the start of the main compilation; this completely acquires the data needed after 6 minutes 43 seconds and finally ends the simulation at 7 minutes 10 seconds. The inverse sinc filter has a multiplication per input sample, addition per input sample, number of adders and 32 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org multiplier of 14.5M multiplications/sec (mps), 14M multiplications/sec (mps), 28, 29 respectively. The lowpass filter as well has a multiplication per input sample, addition per input sample, number of adders and multiplier of 7.5M multiplications sec (mps), 7M multiplications/sec (mps), 14, 15 respectively. Fig 10: pipeline output after the decimation by 128 for channel 1- 4 3.3 Polyphase Fast Fourier Transform (Polyphase FFT) The polyphase fast Fourier transform channelization algorithm has outputs of each channel as described in Fig 13. The signal strength of about 120 dBm range was observed for the decimation by 128 within a frequency band of 100 kHz and when down sampled further by 2, the signal strength reduces to 110 dBm for a frequency range of 100 kHz. The compilation time for the 5 different channels was observed to have a minimal time which falls between the time for perchannel channelization method and pipeline frequency transform method. A delay time of 16 seconds was observed before the start of the main compilation, then completely acquires the data needed within 24 to 34 seconds and ends the simulation at 51 seconds. PFT and PFFT at the rate conversion end, have the same inverse sinc and lowpass output estimation. 33 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 11: pipeline output after the decimation by 256 for channel 1- 4 Fig 12: pipeline output after the decimation by 128 and 256 for channel 5 34 Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 1 – No.6, April 2015 – www.caeaccess.org Fig 13: polyphase output after the decimation by 128 and 256 4. CONCLUSION The total estimation of the computational burden for PFT and PFFT can be given as the sum of the individual multi stage. Therefore, the computational burden for the two stages is given as: Overall multiplication per input sample = 14,500,000 + 7,500,000 = 22,000,000 multiplications/sec (mps). This value shows a reduction of 7,000,000 multiplications per input sample which is equivalent to 24% decrease when compared to per-channel. In comparison, the PFT and PFFT having similar designs at the sample rate conversion end differ from each other in that the PFT divides the input spectrum into high pass and low pass frequencies and forms an hierarchical structure therefore increasing the silicon cost of PFT over PFFT. The signal strength of each algorithm shows that the perchannel and PFFT have similar power spectrum characteristics and the resulting signal strength over a 250 kHz bandwidth varies about 100-110 dBm. Whereas, the signal strength for PFT varies between 40–90dBm characterized with numerous spikes between the 250 kHz bandwidth. 5. REFERENCES [1] Arkesteijn V. J, Klumperink E. A. M and Nauta B. (2001), An analog front end Architecture for Software Defined Radio. MESA Research Institute, IC design group, University of Twente, Netherlands [2] Carsten, Kristensen J. T, Gustav, Kingo, and Boye O. (2005), FM Radio Receiver: Real-Time Systems. P5 projekt, AAU, Elektronik og Elektroteknik, Aalborg Universitet [3] Ching-Hsiang, T. and Sun-Chung, C. (2006), Direct Down Conversion of Multiband RF Signals using Band Pass Sampling, IEEE Transactions on Wireless Communications, Vol. 5, No.1, pp. 72-76 [4] Dawoud, D. S. and Phakathi, S. E. (2004), Advanced Filter Bank Based ADC for Software Defined Radio Applications. AFRICON 7th Conference in Africa, Vol.1, pp. 61-66 for Wireless Communications. Artech House MicroElectromechnical System (MEMS) Series Boston, London, pp. 7-16 [6] Donadio M. P. (2000), CIC Filter Introduction. [email protected];:free publication by Iowegian. [7] Hentschel, T., Henker M., and Fettweis G. (1999), The Digital Front- End of Software Radio Terminals, IEEE Personal Communications, pp 6-12. [8] Jan C. (2011), Transceiver Concepts and Design: Software Defined Radio Front Ends. IMEC, Leuven, Belgium, Multi-mode/ Multi-band RF Transceiver for Wireless Communication, John Wiley & sons, Inc. pp 15 [9] Lin Y. (2008), Realizing Software Defined Radio- A Study in Designing Mobile Supercomputers. PhD. Dissertation, Computer Science and Engineering, University of Michigan [10] Milic L. (2009), Multirate Filtering for Digital Signal Processing Matlab Applications (A Premier Reference Source), University of Belgrade Serbia. Information Science Reference, Hershey, New York [11] Mohammed, R. (2002), Multi- Rate Processing and Sample Rate Conversion. EE Times Home [12] Rouphael T. J. (2009), RF and Digital Signal Processing for Software- Defined Radio: A Multi-Standard MultiMode Approach [13] Savir, G. (2006), Scalable and Reconfigurable Digital Front- End for SDR Wideband Channelizer, Msc. Thesis Delft [14] Shetye, K. A. (2007), Design and Implementation of a Software Defined Radio Receiver for AM Band, M.Sc Thesis Auburn University, pp 19-22 [15] Soudan, M. and Farrell, R. (2009), On Time-Interleaved Analog-to-Digital Converter for Wideband Reconfigurable Radios. Proceedings of The SDR'09 Technical Conference and Product Exposition [5] De Los Santos H. J. (2002), RF MEMS Circuit Design 35