IEEE Transactions on Circuits and Systems Ii-express Briefs, 2011
This brief presents a novel approach for improving the accuracy of rotations implemented by compl... more This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2011
This paper presents novel circuits for calculating the bit reversal on a series of data. The circ... more This paper presents novel circuits for calculating the bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have the minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware FFT architectures.
Complex rotations find use in common transforms such as the Discrete Cosine Transform (DCT) and t... more Complex rotations find use in common transforms such as the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT). In this work we consider low-complexity realization of constant angle rotators based on shifts, adders, and subtracters. The results show that redundant CORDIC and scaled constant multiplication are providing the best results, depending on which angle is considered. It is also shown that the precision can vary several bits using the same number of adders and subtracters, and, hence, the correct choice of rotator architecture is crucial for a low-complexity realization.
IEEE Transactions on Aerospace and Electronic Systems, 2008
study of the implementation and characterization of fast Fourier transform (FFT) pipelined archit... more study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.
This paper presents a 512-point feedforward FFT architecture for wireless personal area network (... more This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides,
IEEE Transactions on Circuits and Systems I-regular Papers, 2009
This paper presents a new pipelined hardware architecture for the computation of the real-valued ... more This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm
This paper presents several implementations of digital channelised receivers on field-programmabl... more This paper presents several implementations of digital channelised receivers on field-programmable gate array (FPGA) platforms for electronic warfare (EW) applications. All implementations are based on the fast Fourier transform (FFT) but they are intended for different applications. We have studied in detail and implemented different parallel architectures for the FFT algorithm in order to maximise speed processing and throughput, and to optimise area. On the other hand, monobit implementations of the FFT have been carried out in order to get real time in broadband digital receivers. Finally, in order to improve the detection of non-stationary signals, time-frequency analysis based on the short time Fourier transform (STFT) has also been implemented.
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2011
This brief presents a novel approach for improving the accuracy of rotations implemented by compl... more This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2011
This paper presents novel circuits for calculating the bit reversal on a series of data. The circ... more This paper presents novel circuits for calculating the bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have the minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware FFT architectures.
Complex rotations find use in common transforms such as the Discrete Cosine Transform (DCT) and t... more Complex rotations find use in common transforms such as the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT). In this work we consider low-complexity realization of constant angle rotators based on shifts, adders, and subtracters. The results show that redundant CORDIC and scaled constant multiplication are providing the best results, depending on which angle is considered. It is also shown that the precision can vary several bits using the same number of adders and subtracters, and, hence, the correct choice of rotator architecture is crucial for a low-complexity realization.
IEEE Transactions on Aerospace and Electronic Systems, 2008
study of the implementation and characterization of fast Fourier transform (FFT) pipelined archit... more study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.
This paper presents a 512-point feedforward FFT architecture for wireless personal area network (... more This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides,
IEEE Transactions on Circuits and Systems I-regular Papers, 2009
This paper presents a new pipelined hardware architecture for the computation of the real-valued ... more This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm
This paper presents several implementations of digital channelised receivers on field-programmabl... more This paper presents several implementations of digital channelised receivers on field-programmable gate array (FPGA) platforms for electronic warfare (EW) applications. All implementations are based on the fast Fourier transform (FFT) but they are intended for different applications. We have studied in detail and implemented different parallel architectures for the FFT algorithm in order to maximise speed processing and throughput, and to optimise area. On the other hand, monobit implementations of the FFT have been carried out in order to get real time in broadband digital receivers. Finally, in order to improve the detection of non-stationary signals, time-frequency analysis based on the short time Fourier transform (STFT) has also been implemented.
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Papers by Mario Garrido