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Nowadays memory forms an important and necessary part of every system. In order to make the system more compact and faster, optimization of memory in terms of area, power and speed is to be made. In this paper column decoder has been implemented to minimize the power and area. The memory architecture is simulated using Laker-ADP schematic tool. The number of sense amplifiers required for MxN memory is reduced in ratio 4:1.
International Journal of Engineering & Technology
The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transistors to design any MxN decoders using CMOS technology .In order to configure the parameters and to make it more portable we are using different types of logic styles this usage of technologies more than one technologies on each circuit is a mixed logic styles .In this concept we observe the results as per required .The technologies we use in this is TGL/DVL. The suggested framework “Design abou...
This paper discusses the design of an Integrated Circuit (IC) layout for a decoder. The layout was designed by using an open source software namely Electric VLSI Design System as the Electronic Design Automation (EDA) tool. In order to produce the layout, the basic knowledge of fabrication process and IC design rules are expounded. The complete layout of the decoder was designed based on its schematic circuit, which consists of NOT gates, 2
An easily-extendable 12-transistor 2-4 line decoder core is presented for the random-access memory interface such as translation lookaside buffer and the first level data cache in this brief. The core idea is to design the line decoder based on the truth table straightforwardly without assistant of the basic gate circuits. The 3-8 line decoder and 4-16 line decoder can be constructed with three and seven of the proposed 2-4 decoder core, respectively, resulting in a low transistor count and high power-delay performance. Simulation results shows that the proposed decoder topologies have the minimum area overhand compared with the state of the art in 65nm CMOS process. Meanwhile, the delay of the 2-4 line decoder is reduced to 120.7 ps, 57.5 ps, and 37 ps at 0.8 V, 1 V and 1.2 V, respectively, resulting in a better PNPD performance. Besides, the PNPD of the proposed 2-4 and 4-16 topology is optimized by 1.7%, and 10.94% compared with that of the HP topologies, while the PNPD of the 3-...
The image data compression has been an active research area for image processing over the last decade [1] and has been used in a variety of applications. This paper investigates the implementation of Low Power VLSI architecture for image compression, which uses Variable Length Coding method to compress JPEG signals [1]. The architecture is proposed for the quantized DCT output [5]. The proposed architecture consists of three optimized blocks, viz, Zigzag scanning, Run-length coding and Huffman coding [17]. In the proposed architecture, Zigzag scanner uses two RAM memories in parallel to make the scanning faster. The Run-length coder in the architecture, counts the number of intermediate zeros in between the successive non-zero DCT coefficients unlike the traditional run- length coder which counts the repeating string of coefficients to compress data [20]. The complexity of the Huffman coder is reduced by making use of a lookup table formed by arranging the {run, value} combinations in the order of decreasing probabilities with associated variable length codes [14]. The VLSI architecture of the design is implemented [12] using Verilog HDL with Low Power approches . The proposed hardware architecture for image compression was synthesized using RTL complier and it was mapped using 90nm standard cells. The Simulation is done using Modelsim. The synthesis is done using RTL compiler from CADENCE. The back end design like Layout is done using IC Compiler. Power consumptions of variable length encoder and decoder are limited to 0.798mW and 0.884mW with minimum area. The Experimental results confirms that 53% power saving is achieved in the dynamic power of huffman decoding [6] by including the lookup table approach and also a 27% of power saving is achieved in the RL-Huffman encoder [8].
Mantech Publications , 2019
This paper presents comparison of semiconductor memory circuits such as volatile memories like SRAM, DRAM and non-volatile memories like ROM, PROM, EPROM, EEPROM, FLASH (NOR based & NAND based). This comparison is on the basis of some parameters including read speed, write speed, volatility, bits/cell, cell structure, cell density, power consumption, etc. In this paper we also focused on applications of those memory cells based on their characteristics. This paper presents the appropriate choice for selecting memory circuit with the read-write speed, capacity, power consumption.
This paper discusses the design of an Integrated Circuit (IC) layout for a decoder. The layout was designed by using an open source software namely Electric VLSI Design System as the Electronic Design Automation (EDA) tool. In order to produce the layout, the basic knowledge of fabrication process and IC design rules are expounded. The complete layout of the decoder was designed based on its schematic circuit, which consists of NOT gates, 2-input NAND gates, 3-input NAND gates, 4-input NAND gates, 2-input AND gates and 3-input AND gates. The layout had undergone Design Rule Check (DRC) set by the Electric VLSI Design System to check for any design rule error. Both layout and schematic circuit of the decoder were then simulated through Layout versus Schematic (LVS) to ensure they were identical. LT spice is used as simulator to carry out the simulation work and verify the validity of the function. The simulation output indicated that results of the layout and schematic circuit for decoder were essentially identical and matches the theoretical results.
Sensors
Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the...
In any Micro-Controller Embedded System the whole memory is accessed by a single Micro-Controller. It uses only a fraction of memory and rest of the memory is wasted. In addition to this the only one Micro-Controller is executing all the given set of instructions or program. In our work we have designed a Multi-Block external memory & Binary-Tree-Decoder for a Multi-Micro-Controller Embedded System so that the complete memory is divided into more than one block (in our case it is 4) and it can be accessed independently by more than one Micro-Controller. This can be done in two ways one is static memory mapping mechanisim and dynamic memory mechanisim. In static memory mapping, the Micro-Controller is able to access only a particular block of memory to which it is mapped. While in the Dynamic memory mapping, any Micro-Controller can access any block of memory. Also, the different part program is executed by different Micro-Controller parallely, which results in to speed up the execution speed of the Multi-Microcontroller system. Current embedded applications are migrating from single processor-based systems to intensive data communication requiring multi-processing systems to fulfill the real time application demands. The performance demanded by these applications requires the use of multiprocessor architecture. For these types of multiprocessor systems there is a need for developing such memory mapping mechanism which can support high speed. For selected memory mapping mechanism what should be the decoding mechanism and the controller design that gives low-power consumption, high-speed, low-area system. Our alorithtim of Binary-Tree-Decoder improves the MMSOPC embedded system design. However the designing of Binary-Tree-Decoder alorithim (for 256K memory) has not been designed by any of researcher which is presented in this work.
In VLSI, there is integration of hundreds and thousands of transistors to form a chip (or) microchip. SRAM is utilized for computer cache memory and a chunk of random access memory digital to analog converter on a video card. SRAM keeps data constant, without the need of memory module to be refreshed periodically. SRAM takes main role in very large scale integrated circuit (VLSI) due to its storage capacity and small access time. In this work the simulation study of different SRAM cells 4+2T SRAM, 4TSRAM, 5T SRAM and 6T SRAM are done. Also a 4byte SRAM architecture with row decoder, column decoder, SRAM cell, pre-charge circuit, sense amplifier and write driver circuit are simulated using EDA tool in 45nm technology. The average power delay and area various SRAMs are calculated and compared. SRAM-5T is showing better results for Average power consumption and delay while SRAM-4T is better in terms area.
International Journal for Research in Applied Science & Engineering Technology (IJRASET), 2022
Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances.
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