Unit1 1.7 Instr Cycle

Unit-1_1.
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INSTRUCTION CYCLE AND INSTRUCTION PIPELINE
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Outline
• Computer Organization and Architecture

• Structure and Function
• Evolution (a brief history) of computers
• Von Neumann Architecture
• Interpretation of instructions
• Interconnection Structures
• Instruction Cycle and Instruction Pipeline
• RAM Model Evolution of Intel processor architecture- 4 bit to 64 bit
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Computer Components
• All contemporary computer designs are based on concepts developed by John von
Neumann at the Institute for Advanced Studies, Princeton U.
• Such a design is referred to as the von Neumann architecture and based on 3
concepts:
– Data and instructions are stored in a single read-write memory
– The contents of this memory are addressable by location, without regard to
type of data contained there
– Execution occurs in a sequential fashion from one instruction to the next.
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Components
• The Control Unit and the Arithmetic and Logic Unit constitute the
Central Processing Unit
• Data and instructions need to get into the system and results out
– Input/output
• Temporary storage of code and results is needed
– Main memory
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Top Level View
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CPU Functions and Organization
• The requirements that a CPU must fulfill are:

– Fetch instructions
– Interpret instructions
– Fetch data
– Process data
– Write data
• Organizational requirements that are derived from these functions:
– Arithmetic and Logic Unit ALU
– Control logic 6
– Temporary storage
– Means to move data and instructions in and around the CPU
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Registers
• CPU must have some working space (temporary storage)

• Called registers
• Number and function vary between processor designs
• It is one of the major design decisions
• Top level of memory hierarchy
– Faster, smaller, more expensive
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Register Organization
• Registers form the highest level of the memory hierarchy

• Two types of registers
– User-visible
– Control and status registers
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User Visible Registers
• General Purpose
• Data
• Address
• Condition Codes
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General Purpose Registers
• The issues to consider in the design include

– Should there be true general purpose or specialized for data or addressing
• Data –Accumulator
• Addressing –Segment registers
• Make them general purpose
– Increase flexibility and programmer options
– Increase instruction size & complexity
• Make them specialized
– Smaller (faster) instructions
– Less flexibility
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General Purpose Registers (2)
• How many general purpose registers?

– Number affects the instruction set design
– Typically between 8 - 32
• Fewer = more memory references
• More does not reduce memory references and takes up processor real estate
(space)
• Register Length?
– Large enough to hold full address
– Large enough to hold full word
– Often possible to combine two data registers
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Condition Code Registers
• Sets of individual bits

– e.g. result of last operation was zero
• Can be read (implicitly) by programs
– e.g. Jump if zero
• Can not (usually) be set by programs
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Control and Status Register
• Used by the control unit to control the operations of the CPU and by the
privileged operating systems programs to control program execution
• The four essential registers for instruction execution:
1. Program Counter (PC)
2. Instruction Decoding Register (IR)
3. Memory Address Register (MAR)
4. Memory Buffer Register (MBR)
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Program Status Word
• All CPU design include a set of registers (PSW) that contain status
information
• Common fields or flags include:
– Sign of last result
– Zero
– Carry
– Equal
– Overflow
– Interrupt enable/disable
– Supervisor
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Example Register Organization
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Example Register Organization (2)
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Instruction Cycle
• The processing of instructions by the CPU can be viewed as consisting of

two steps (sub cycles)
– Fetch
– Execute
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Fetch Cycle
• In typical processor, Program Counter (PC) register holds address of next instruction to be
fetched next
• Processor fetches instruction from memory location pointed to by PC
• Increment PC
– Unless told otherwise
• The fetched instruction is loaded into Instruction Register (IR) register
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Execute Cycle
• The processor interprets the instruction and performs required actions. In general, these actions fall into
four categories:
– Processor-memory
• data transfer between CPU and main memory
– Processor I/O
• Data transfer between CPU and I/O module
– Data processing
• Some arithmetic or logical operation on data
– Control
• Alteration of sequence of operations
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• e.g. jump
– Combination of above
Example of Program Execution
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Data Flow
• The exact sequence of events during the instruction cycle depends on

the CPU design
• We will describe the general set of events
• Consider a CPU with
– Program Counter (PC)
– Instruction Decoding Register (IR)
– Memory Address Register (MAR)
– Memory Buffer Register22
(MBR)
Fetch Cycle - Data Flow
1. PC contains address of next instruction

2. Address moved to MAR 23
3. Address placed on address bus

4. Control unit requests memory read
5. Result placed on data bus, copied to MBR, then to IR (Meanwhile PC incremented by 1)
Data Fetch - Data Flow
1. IR is examined
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2. If indirect addressing, indirect cycle is performed
– Right most N bits of MBR transferred to MAR
– Control unit requests memory read
– Result (address of operand) moved to MBR
Execute Cycle – Data Flow
• The execute cycle may take many forms, depending on the instruction being
executed
• May include
– Memory Read/Write
– Input/Output
– Register transfer
– ALU operations
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Pre-Fetch
• The Fetch cycle involves accessing main memory

• The Execution cycle usually does not access memory
• It is thus possible to fetch the next instruction during execution of current
instruction
– Called instruction pre-fetch
• Can lead to improved performance
– But does not lead to double speed improvement since fetch cycle is shorter than
execution 26
– Fetch more than instruction?

• Any jump or branch means that pre-fetched instructions are not the required
instructions
Pipelining Overview
• Strict sequential instruction execution does not permit high levels of H/W efficiency
– Solution is to operate the instruction execution cycle like an assembly line:
• Perform all tasks concurrently, but on different (sequential) instructions
– The result is temporal parallelism: the instruction pipeline
• We have considered an instruction execution consisting of two stages
– Fetch Instruction
– Execute Instruction
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4 stage pipeline
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Non Pipelined Vs Pipelined
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Pipelining Overview
• To improve performance, we can add more stages to the instruction cycle

• Consider the following decomposition of instruction execution
– Fetch instruction (FI)
– Decode instruction (DI)
– Calculate operands (CO)
– Fetch operands (FO)
– Execute instructions (EI)
– Write operand (WO)
• These operations can be overlapped as depicted in the next diagram
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Advantages of Instruction Pipeline
• Increased Throughput: Pipelining enhance the throughput capacity of a CPU and enables
a number of instruction to be processed at the same time at different stages. This leads to the
improvement of the amount of instructions accomplished in a given period of time, thus
improving the efficiency of the processor.
• Improved CPU Utilization: From superimposing of instructions, pipelining helps to ensure

that different sections of the CPU are useful. This gives no time for idling of the various
segments of the pipeline and optimally utilizes hardware resources.
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• Higher Instruction Throughput: Pipelining occurring because when one particular
instruction is in the execution stage it is possible for other instructions to be at varying
stages of fetch, decode, execute, memory access, and write-back. In this manner there
is concurrent processing going on and the CPU is able to process more number of
instructions in a given time frame than in non pipelined processors.
• Better Performance for Repeated Tasks: Pipelining is particularly effective when all
the tasks are accompanied by repetitive instructions, because the use of the pipeline
shortens the amount of time each task takes to complete.
• Scalability: Pipelining is RSVP implemented in different types of processors hence it

is scalable from simple CPU’s to an advanced multi-core processor
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Drawbacks …..
• Several factors limit the performance, such as conditional branch instructions,

which can invalidate several instruction fetches
• If a branch is taken, the pipeline is cleared of instructions that are not needed
– Resulting into performance degradation
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THANK YOU
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Vishwakarma Institute of Technology, Pune

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Unit-1_1.

• Computer Organization and Architecture

• The requirements that a CPU must fulfill are:

• CPU must have some working space (temporary storage)

• Registers form the highest level of the memory hierarchy

• The issues to consider in the design include

• How many general purpose registers?

• Sets of individual bits

• The processing of instructions by the CPU can be viewed as consisting of

• The exact sequence of events during the instruction cycle depends on

1. PC contains address of next instruction

3. Address placed on address bus

• The Fetch cycle involves accessing main memory

– Fetch more than instruction?

• To improve performance, we can add more stages to the instruction cycle

• Improved CPU Utilization: From superimposing of instructions, pipelining helps to ensure

• Scalability: Pipelining is RSVP implemented in different types of processors hence it

• Several factors limit the performance, such as conditional branch instructions,

Vishwakarma Institute of Technology, Pune

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