Chapter 3: Top Level View of Computer

Function and Interconnection

Computer Architecture
and Organization

Department of Computer Engineering

 Program Concept
• Logic Components can combined in various way to store
binary data and perform logical operation on that data
• Logical components need to be configured or rewired for
each particular computation.
• Hardwired program
• Hardwired systems are inflexible
• Solution …
• General purpose hardware can do different tasks, given
correct control signals
• Instead of re-wiring, supply a new set of control signals
• How shall control signal be supplied?

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 What is a program?

• A sequence of steps
• For each step, an arithmetic or logical operation is done
• For each operation, a different set of control signals is
needed
• Lets add the general purpose hardware segment that
can accept a code and generate control signals.
• Program is now much easier. In stead of rewiring the
hardware for each new program, all we need to do is
provide a new sequence of code.
• This new sequence of code or instruction is called
software.

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Program Concept …

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 Function of Control Unit
• For each operation a unique code is provided
• e.g. ADD, MOVE
• A hardware segment accepts the code and issues the
control signals

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 Computer components
• Contemporary computer designs are based on the Von
Neumann architecture
• Data and Instruction are stored in a single read-write
memory
• The content of this memory are addressable by location
• Execution occurs in a sequential fashion from one
instruction to the next (unless explicitly modified)

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 Components
• The Control Unit and the Arithmetic and Logic Unit
constitute the Central Processing Unit.
• CPU
• Data and instructions need to get into the system and
results out
• Input/output
• Temporary storage of code and results is needed
• Main memory
• Data, Instruction and Control Signals need a pathway
• System Bus

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Computer Components: Top Level View

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 Instruction Cycle
• Two steps:
• Fetch
• Execute

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 Fetch Cycle
• Program Counter (PC) holds address of next instruction to
fetch
• Processor fetches instruction from memory location pointed
to by PC
• Increment PC hold address of next instruction in sequence.
• Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor use MAR in between

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 Execute Cycle
• Processor interprets instruction and performs required
actions
• Processor-memory
• data transfer between CPU and main memory
• Processor I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above

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Example of a Simple Machine

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Example of Program Execution

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 Instruction Cycle State Diagram

For example, the PDP-11 instruction ADD A,B results in the following
sequence of states: iac, if, iod, oac, of, oac, of, do, oac, os.

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 Interrupts

• Mechanism by which other modules (e.g. I/O) may

interrupt normal sequence of processing
• Common Class of Interrupts:
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller
• Hardware failure
• e.g. power failure

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 Interrupts

• Improves Processing efficiency

• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context- content of PC & other registers value.
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program

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Transfer of Control via Interrupts

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 Multiple Interrupts

• Two approaches can be taken to dealing with multiple interrupts.

The first is to disable interrupts while an interrupt is being
processed.
• A disabled interrupt simply means that the processor can and will
ignore that interrupt request signal. If an interrupt occurs during this
time, it generally remains pending and will be checked by the
processor after the processor has enabled interrupts.
• The drawback to the preceding approach is that it does not take into
account relative priority or time-critical needs.
• A second approach is to define priorities for interrupts and to allow
an interrupt of higher priority to cause a lower-priority interrupt
handler to be itself interrupted

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Multiple Interrupts …

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Multiple Interrupts …

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Multiple Interrupts …

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Instruction Cycle with Interrupts

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Instruction Cycle (with Interrupts) - State Diagram

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 Connecting
• All the units must be connected
• Different type of connection for different type of unit
• Memory
• Input / Output
• CPU

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 Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
• Read
• Write

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 Input/Output Connection(1)
• Similar to memory from Processor's viewpoint
• Output
• Receive data from computer
• Send data to peripheral
• Input
• Receive data from peripheral
• Send data to computer

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 Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
• e.g. spin disk
• Receive addresses from computer
• e.g. port number to identify peripheral
• Send interrupt signals

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 CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts

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Computer Modules

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 Bus Interconnection
• Bus is a shared communication pathway connecting two or
more devices
• Shared transmission media - it broadcast
• Consists multiple lines
• e.g. 32 bit data bus is 32 separate single lines

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 System Bus
• A bus that connect major computer components
• CPU, Memory and I/O
• Consist typically 50 to hundreds of separate lines
• Each line assigned a particular meaning or function
• Lines can be grouped into three functional groups
• Data, address and control
• There may be a power distribution lines that supply power
to the attached modules

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 Data Lines
• Carries data
• Remember that there is no difference between “data” and
“instruction” at this level
• These lines collectively are called data bus
• Width is a key determinant of performance
• 8, 16, 32, 64 bit
• If data bus is 32bit and each instruction is 64 bit
the processor must access the memory twice during
each instruction cycle

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 Address Lines
• Identify the source or destination of data on the data bus
• e.g. CPU needs to read an instruction (data) from a given location in
memory
• Bus width determines maximum memory capacity of
system
• e.g. 8080 has 16 bit address bus giving 64k address space
• Also used to address I/o ports
• higher-order bits used to select a particular module
• Lower-order bits select I/O port within the module

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 Control Lines
• Used to control the access to and the use of data and
address lines as they are shared by all components.
• Control signals transmit both command and timing
information
• Control signals specify operation to be performed
• Timing signals indicate the validity of data and address
information

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 Typical control lines
• Memory write: causes data on the bus to be written into the addressed
location
• Memory read: causes data from the addressed location to be placed on the
bus
• I/O write: causes data on the bus to be output to the addressed I/O port
• I/O read: causes data from the addressed I/O port to be placed on the bus
• Transfer ACK: indicates that data have been accepted from or placed on the
bus
• Bus request: indicates that a module needs to gain control of the bus
• Bus grant: indicates that a requesting module has been granted control of the
bus
• Interrupt request: indicates that an interrupt is pending
• Interrupt ACK: acknowledges that the pending interrupt has been recognized
• Clock: is used to synchronize operations
• Reset: initializes all modules.

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Bus Interconnection Scheme

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Physical Realization of Bus Architecture

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 Single Bus Problems
• Lots of devices on one bus leads to:
• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely
affect performance
• If aggregate data transfer demand approaches bus capacity
• Use wider buses or increase data rate
• But data rate are growing rapidly by attached devices - graphics
• Most systems use multiple buses to overcome these
problems

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Traditional (with cache)

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High Performance Bus

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 Bus Types

• Dedicated
• Separate data & address lines
• Common on many buses
• Multiplexed
• Shared lines
• Time multiplexing
• Address valid or data valid control line
• Advantage - fewer lines
• Disadvantages
• More complex control
• Reduction performance

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 Bus Arbitration
• More than one module may need control of the bus
• e.g. CPU and DMA controller
• Only one unit a time can successfully transmit over the bus
• Some method of arbitration is needed
• Arbitration may be centralised or distributed

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 Centralised or Distributed Arbitration
• Centralised
• Single hardware device controlling bus access
• Bus Controller /Arbiter
• Responsible for allocating time on the bus
• May be part of CPU or separate
• Distributed
• Each module contains access control logic
• The modules act together to share the bus

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 End of Chapter 3

Computer Architecture
and Organization

Department of Computer Engineering