BECE204L – MICROPROCESSOR &

MICROCONTROLLERS

Chanthini Baskar
Assistant Professor Gr-2/SENSE
Mail id: [email protected]
Module – 2:
MICROPROCESSOR ARCHITECTURE
& INTERFACING : INTEL x86
 Introduction to 8086
• Backward compatible with 8085
• Memory interfacing technique is similar, though
memory addressing is different
• 40-pin DIP, 5V supply
• 29,000 transistors
• 20 bit address to access memory
• (memory space = 220 = 1MB)
 8086 Registers
• “General Purpose” & “Special Purpose”
• 16 bit registers
• GP Registers:
– Can be used as 8 bit or 16 bit
– Used for holding data, variables, and intermediate
results temporarily
• SP Registers:
– Used as segment registers, pointers, index registers or
as offset storage registers for some addressing modes
 Register Groups
• General data registers
• Segment registers
• Pointers & index registers
• Flag registers
 General Data Registers

• X, H, L ?
• AX - Accumulator
• CX – Default counter in string
and loop operations
• BX – Offset storage for forming
physical address
• DX – Implicit operand/
destination in few instructions
 Segment Registers
• 8086 addresses segmented memory
• Total 1MB is divided into 16 logical
segments; each segment having 64KB
memory
• 4 segment registers
• CS – used for addressing a memory location
in the code segment of the memory
• DS – points to the data segment of the
memory
• ES – Another data segment used along with
DS
• SS – used to address stack segment,
memory to store stack data, main
operations are Push & Pop
 Segment Registers

• While addressing any location in the memory bank, address

is calculated from two parts:
– Segment address
– Offset
• SR contains the 16-bit segment base address, related to
different segments
• Any of the pointers/index registers/ BX may contain the
offset of the location to be addressed
• This scheme is advantageous, as address bits are 20 and
machine operates at 16 bits.
 Pointers & Index Registers
• Pointers contain offsets within the particular segments
• Instruction Pointer (IP):
The instruction pointer usually stores the address of the
next instruction that is to be executed.
• Base Pointer (BP):
The Base pointer stores the base address of the memory.
Also, it acts as an offset for Stack Segment (SS).
• Stack Pointer (SP):
The Stack Pointer Points at the current top value of the
Stack. Like the BP, it also acts as an offset to the Stack
Segment (SS).
• Source Index (SI):
It stores the offset address of the source.
• Destination Index (DI):
It stores the offset address of the Destination.
 Flag Registers

• The Flag or Status register is a 16-bit register which

contains 9 flags, and the remaining 7 bits are idle in this
register.
• These flags tell about the status of the processor after
any arithmetic or logical operation. IF the flag value is 1,
the flag is set, and if it is 0, it is said to be reset.
• Indicates the results of computations in the ALU.
• Also contains some flag bits to control CPU operations.
 8086 Architecture
• Supports 16-bit ALU, set of 16-bit registers
• 8086 is a 16-bit Integer processor in a 40 pin, Dual Inline
Packaged IC
• 8086 provides the programmer with 14 internal registers,
each 16 bits or 2 Bytes wide.
• To increase execution speed and fetching speed, 8086
segments the memory.
• It’s 20 bit address bus can address 1MB of memory, it
segments it into 16 64kB segments.
• 8086 works only with four 64KB segments within the whole
1MB memory.
• Powerful interrupt structure
• Fetched instruction queue
 8086 Architecture

BIU
Contains circuit for phy add calculation
and a precoding instruction byte queue.
It makes the system’s bus signals
available for external interfacing of
devices

Execution Unit (EU)

EU contains the register set except SRs and

IP. It has a 16-bit ALU. EU tells BIU where to
fetch the instructions/data from, decodes
instructions and executes instructions that
have already been fetched by the BIU.

BIU and EU functions separately.

Execution Unit
 Execution Unit
• Contains control circuitry which directs internal operations.
• The main components of the EU are General purpose
registers, the ALU, Special purpose registers, Instruction
Register and Instruction Decoder and the Flag/Status
Register.
• Fetches instructions from the Queue in BIU, decodes and
executes arithmetic and logic operations using the ALU.
• Sends control signals for internal data transfer operations
within the microprocessor.
• Sends request signals to the BIU to access the external
module.
 Special Purpose Register
• Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during
instructions like PUSH, POP, CALL, RET etc.
• Base Pointer:
BP can hold offset address of any location in the stack
segment. It is used to access random locations of the stack.
• Source Index:
It holds offset address in Data Segment during string
operations.
• Destination Index:
It holds offset address in Extra Segment during string
operations.
 Flag Register
• A flag is a FF that indicates some condition produced by the
execution of an instruction or controls certain operations of the EU.
• 16-bit flag register contains 9 active flags, out of which 6 are used
to indicate some condition produced by an instruction

Condition Flags

Control Flags
 Execution Unit (EU)

Auxiliary Carry Flag

Carry Flag
This is set, if there is a carry from the lowest
nibble, i.e, bit three during addition, or borrow This flag is set, when there is a
for the lowest nibble, i.e, bit three, during carry out of MSB in case of addition
subtraction. or a borrow in case of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the result This flag is set, if the result of the This flag is set to 1, if the lower byte of
of any computation is negative computation or comparison performed the result contains even number of 1’s ;
by an instruction is zero for odd number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor enters
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
the single step execution mode by
large enough to accommodate in a destination register. The result is of more
than 7-bits in size in case of 8-bit signed operation and more than 15-bits in
generating internal interrupts after the
size in case of 16-bit sign operations, then the overflow will be set. execution of each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the
string is processed beginning from the lowest address to the highest Causes the 8086 to recognize external mask
address, i.e., auto incrementing mode. Otherwise, the string is processed interrupts; clearing IF disables these
from the highest address towards the lowest address, i.e., auto interrupts.
incrementing mode. 17
 GP Register
• Temporary storage of data, allows quick access
• Base Register (BX)
– This is the only general purpose register whose contents can be
used for addressing the 8086 memory.
• Counter Register (CX)
– Instructions such as SHIFT, ROTATE and LOOP use
the contents of CX as a counter.
• Data Register (DX)
– Used to hold the high 16-bit result (data) in
16 X 16 multiplication or the high
16-bit dividend (data) before a 32 16
division and the 16-bit reminder after division.
Bus Interface Unit
 Bus Interface Unit
• It provides the interface of 8086 to external memory and I/O
devices via the System Bus. It performs various machine
cycles such as memory read, I/O read etc. to transfer data
between memory and I/O devices.
BIU performs the following functions
• It generates the 20 bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6 byte prefetch instruction queue(supports
pipelining).
BIU mainly contains the 4 Segment registers, the Instruction
Pointer, a prefetch queue and an Address Generation Circuit.
 Segment Register
• Out of the available 1MB memory, at any given time, 8086
works only with four 64KB segments (total 16 segments).
• SR holds the first 16 bits of the starting address of the four
memory segments.
Address Generation Circuit:
• The BIU has a Physical Address Generation Circuit.
• It generates the 20 bit physical address using Segment and
Offset addresses using the formula:

• Physical Address = Segment Address x 10H + Offset

Address
 Instruction Pointer
• It is a 16 bit register. It holds offset of the next instructions
in the Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20 bit physical address
of the Code Segment.
• Address of the next instruction is calculated as CS x 10H +
IP.
 SS & SP
• Stack is a section of memory set aside to store addresses
and data while a subprogram is executing.
• 8086 allows an entire 64KB segment as a stack.
• SS holds the upper 16-bit of the starting address of this
segment.
• SP in the EU holds the 16-bit offset from the start of the
segment to the memory location where a word was
recently stored on the stack.
• Memory location where a word was most recently stored is
called the top of stack.
 Basics of Addressing Mode
• An instruction is a basic command given to a microprocessor to perform a
specified operation with given data.
• Each instruction has two groups of bits.
• One group of bits is known as operation code (Opcode), which defines what
operation will be performed by the instruction.
• The other field is called operand, which specifies data that will be used in
arithmetic and logical operations.
• The operand can specify a register or a memory location in any one of the memory
segments or I/O ports.
• The addressing mode is used to locate the operand or data.
• There are different types of addressing modes depending upon the location of data
in the 8086 processor.
 Basics of Addressing Mode
• Most 8086 instructions can operate on the 8086’s general purpose register set.

• By specifying the name of the register as an operand to the instruction, you may

access the contents of that register.

• Consider the 8086 mov (move) instruction:

mov destination, source

• This instruction copies the data from the source operand to the destination

operand.

• The eight and 16 bit registers are certainly valid operands for this instruction.

• The only restriction is that both operands must be the same size.
 Basics of Addressing Mode
mov ax, bx ;Copies the value from BX into AX

mov dl, al ;Copies the value from AL into DL

mov si, dx ;Copies the value from DX into SI

mov sp, bp ;Copies the value from BP into SP

mov dh, cl ;Copies the value from CL into DH

 Basics of Addressing Mode
• In addition to the general purpose registers, many 8086 instructions (including the
mov instruction) allow you to specify one of the segment registers as an operand.
• There are two restrictions on the use of the segment registers with the mov
instruction.
• First of all, you may not specify cs as the destination operand,
• second, only one of the operands can be a segment register.
• You cannot move data from one segment register to another with a single mov
instruction.
• To copy the value of cs to ds, you’d have to use some sequence like:
mov ax, cs
mov ds, ax
• You should never use the segment registers as data registers to hold arbitrary
 Types of Addressing Mode
• Sequential Control Flow Instructions
• Instructions that transfer control to the next instruction appearing immediately
after it in the program.
• Eg. Arithmetic, logical, data transfer and processor control instructions.
• Control Transfer Instructions
• Transfer the control to some predefined address in the instruction
• Eg.: INT, CALL, RET, JUMP
 Immediate Addressing
• Immediate addressing transfers the source, an immediate byte or word data, into
the destination register.
• Immediate data means constant data, whereas data transferred from a register or
memory location are variable data.
• Immediate date may be 8-bit or 16 bit.
• Example: MOV BL, 44 ; Copies 44 decimal (2CH) into BL
MOV AX, 44H ; Copies 0044H into AX
MOV AL, ‘A’ ; Copies ASCII of the letter A into AL
 Direct or Displacement
Addressing
• A 16-bit memory address (offset) or an IO address is specified directly in the
instruction.
• Eg. MOV AX, [5000H]; Data resides in a memory location in the data segment,
whose effective address is computed using 5000H as offset and the content of DS
as segment address
• IN 80H; 80H is an IO address
 Register Addressing
• In the Register addressing mode, the data is stored in a register and it is referred
using a particular register.
• All registers except IP may be used in this mode.
• 8-bit register names with register addressing: AH, AL, BH, BL, CH, CL, DH, DL.
• 16-bit register names: AX, BX, CX, DX, SP, BP, SI ,DI, CS, SS, DS and ES.
• Never mix an 8-bit register with 16-bit, it is not allowed in microprocessor.
• Code segment register (CS) is never used as destination.
• Segment to segment MOV instruction is not allowed.

• Example: MOV AL, BL ; Copies 8-bit content of BL into AL

MOV AX, CX ; Copies 16-bit content of CX into AX
MOV ES, DS ; Not allowed (segment to segment)
MOV BL, DX ; Not allowed (mixed size)
MOV CS, AX ; Not allowed (Code segment register
may not be destination register)
 Register Indirect Addressing

• The address of the memory location which contains data is determined in an

indirect way, using the offset registers.
• The offset address of data is stored in BX, DI and SI.
• The data segment or extra segment is used by default
• The [ ] symbol denote indirect addressing in assembly language.
Example:
• MOV CX, [BX] ; Copies the word contents of the data segment memory location
addressed by BX into CX.
• MOV [DI], [BX] ; Memory to memory transfers are not allowed except with string
inst.
 Base Addressing Mode
• In this addressing mode, the offset address of the operand is given by the sum of
contents of the BX/BP registers and 8-bit/16-bit displacement.
Example:
• MOV DX, [BX+04]
• ADD CL, [BX+08]
• MOV AX, 50H[BX] ; Effective address is given as DS*10H + 50H + [BX] .
• MOV 10H[SI], DX ; Content of DX is transferred to address DS*10H + 10H + [SI]
 Indexed Addressing Mode

• Offset of the operand is stored in one of the index registers.

• DS is the default segment register for DI and SI.
• In case of string instruction, DS and ES are default segment registers for SI & DI
respectively.
• This is a special case of register indirect addressing mode.
• Example: MOV AX, [SI] ; Data is available in data segment, at an
offset address stored in SI
.
MOV CX, [DI] ; Content of address DS*10H + [DI] will be
transferred to CX
 Base Indexed Addressing
Mode
• In this addressing mode, data is available at an effective address formed by adding
the content of any one of the base registers (BP or BX) to the content of an index
register (SI or DI).
• The default segment may be DS or ES.
• Example:
• MOV AX, [BX] [SI] ; Effective address is given as DS*10H + [BX] + [SI].
• MOV [BX] [DI], AX ; Content of AX is transferred to address DS*10H + [BX] + [DI]
 Base Indexed displacement
Addressing
• The effective address is formed by adding an 8-bit or 16-bit displacement with the
sum of contents of any one of the base registers (BP or BX) and any one of the
index registers (SI or DI).
• The default segment may be DS or ES.
• Example:
• MOV AX, 50H [BX] [SI] ; Effective address is given as DS*10H + 50H + [BX] + [SI].
• ADD 50H [BX] [SI], BP ; Content of BP is added with that in the memory location
whose offset is given by DS*10H + 50H + [BX] + [SI], result is stored in this
memory location.
 Physical Address Calculation

• The content of the segment register is shifted left bit-wise four times (Multiply the
16-bit hex value by 10H).
• To this result, the content of an offset register is added, to produce 20-bit physical
address.
• Offset registers for the different segments are indicated below:
• BX/ SI/ DI – Data Segment
• IP – Code Segment
• BP/SP– Stack segment
• DI – Extra segment
 Example
The value of Code Segment (CS) Register is 4042H and the value of
different offsets is as follows: BX: 2025H , IP: 0580H , DI: 4247H.
Calculate the effective address of the memory location pointed by
the CS register.
• The offset of the CS Register is the IP register.
• Shift base address 4-bits and Add offset address

= (469A0)H
 Practice Problem

• The value of the DS register is 3032H. And the BX register

contains 3040H. Find the physical address.

 33360H
 Practice Problem
• You are provided with the following values:
DS: 3056H, IP: 1023H, BP: 2322H and SP: 3029H.
Can you calculate the effective address of the memory location as per
the DS register?
 Example

i. Direct Addressing: MOV AX, [5000H]

ii. Register Indirect: MOV AX, [BX]
iii. Register Relative: MOV AX, 5000H [BX]
iv. Based Indexed: MOV AX, [BX] [SI]
v. Relative Based Indexed: MOV AX, 5000H [BX] [SI]
Answer
Answer
Answer
Answer
Types of Instructions
1.Data Transfer Instructions

2.Arithmetic Instructions

3.Logical Instructions

4.String manipulation Instructions

5.Process Control Instructions

6.Control Transfer Instructions

 Data Transfer/Copy Instructions

• Transfer data from source operand to destination operand

• Instruction to transfer a word
– MOV − Transfer data from one register/memory
locations to another register/memory location
• MOV DS, 5000H //Invalid - segment register cannot be
destination register in immediate addressing mode
• MOV AX, 5000h Immediate
• MOV DS, AX Register
• MOV AX, BX
• MOV AX, [SI] Indirect
• MOV AX, [2000H] Direct
• MOV AX, 50H[BX] Base
 Data Transfer/Copy Instructions
PUSH
• This instruction pushes the contents of specified register/
memory location on to the stack.
• SP is decremented by 2 after each execution of the
instruction.
• The actual current stack top is always occupied by the
previously pushed data.
• Hence, the push operation decrements SP by two and then
stores the two byte contents of the operand onto the stack.
• The higher byte is pushed first and then the lower byte.
• Thus, the higher byte occupies the higher address.
 PUSH
• PUSH: Push to Stack
• Pushes the content of specified register/memory location on to the stack
• PUSH AX
• PUSH DS
• PUSH [5000H]

SP decremented by 2
PPUSH − Put a word at
the top of the stack
PUSHA − Used to put
all the registers into
the stack
Pushing data to Stack Memory
 Data Transfer/Copy Instructions
POP

This instruction loads the specified register/ memory location with the
contents of the memory location of which the address is formed by the SS
& SP.
• SP is incremented by 2, with each execution of the instruction.
• Sequence of operation:
1. Contents of stack top memory location is stored in AL & SP is
incremented by 1.
2. The contents of the memory location pointed now by SP is
copied to AH & SP is again incremented by 1.
 POP
• Used to get a word from top of the stack
• POP AX
• POP DS
• POP [5000H]

SP incremented by 2

POPA − Used to get

words from the stack
to all registers
Popping register contents from Stack Memory
 Data Transfer/Copy Instructions Cont’d
• XCHG
– Exchange the content of specified source and destination
operands
– Register - memory
– Memory – Memory (Not allowed)
– Immediate data (Not allowed)
– XCHG [5000H], AX // AX and memory location 5000H in
DS
– XCHG BX, AX
• XLAT
- This instruction is used for finding out the codes in case of code
conversion problems, using lookup table technique.
Instructions to Transfer the Address
• Load Effective Address (LEA)
– Loads the effective address formed by destination operands
– LEA BX, ADR //EA of Label ADR transferred to BX
– LEA SI, ADR[BX] // Offset of ADR added with content of BX
and loaded in SI
• LDS/LES: Loads DS/ES register and the specified destination
register with the content of memory location given as source
• LDS BX, 5000H
• LES BX, 5000H
 Instructions to transfer flag registers

• LAHF: Load AH from lower Byte of Flag

– Used to observe the status of all the condition code flags
(except overflow) at a time
• SAHF: Store AH from lower Byte of Flag
• PUSHF: Push flags to stack
• POPF: Loads the flag register completely form the word
contents of the memory location currently addressed by SP
and SS
 Instructions for Input and Output Port Transfer

• IN: Input the port

– Used for reading an input port
– Address of the input port may be specified in the instruction
directly or indirectly
– AL and AX allowed destination for 8-bit and 16-bit input
operations
– DX – only register allowed to carry the port address
• IN AL, 03H // Reads data from an 8-bit port with address 03H
and stores it in AL
• IN AX, DX // Reads data from a 16-bit port whose address is in
DX and stores it in AX
• MOV DX, 0800H // 16-bit address taken in DX
• IN AX, DX
 Instructions for Input and Output Port Transfer

• OUT: Output to the port

• Write content of AL or AX to an output port
• Address of the output port may be specified in the
instruction directly or implicitly in DX
• OUT 03H, AL // Send data available in AL to port whose
address is 03H
• MOV DX, 0300H
• OUT DX, AX
Arithmetic Instructions
 Arithmetic Instructions
• Addition
• Subtraction
• Multiplication
• Division
• ASCII
• Decimal adjust instructions
• Increment
• Decrement

• Affect all the condition code flags

• Operand – Register, Memory location or immediate data
 ADD

• Memory to memory addition not possible

• Contents of segment registers cannot be added
• ADD AX, 0100H // Immediate
• ADD 0100H // Immediate
• ADD AX, BX // Register
• ADD AX, [SI] // Register Indirect
• ADD AX, [5000H] // Direct
• ADD [5000H], 0100H // Immediate
 ADC

• Add with carry

• Same as ADD but adds carry flag bit
• ADC AX, 0100H // Immediate
• ADC 0100H // Immediate
• ADC AX, BX // Register
• ADC AX, [SI] // Register Indirect
• ADC AX, [5000H] // Direct
• ADC [5000H], 0100H // Immediate
 INC, DEC

• INC
– Increase the content of specified register or memory
location by 1
– INC AX
– INC [BX]
– INC [5000H]
– Affect all condition code flags except carry flag (CF)
• DEC
– Subtract 1 from the contents of specified register or
memory location
– DEC AX
– DEC [BX]
– DEC[5000H]
 SUB, SBB
• Subtract source from destination operand
• Result left in destination operand
• Source operand – Register, memory location or immediate
data
• Destination operand – Register/memory location
• Source and destination both must not be memory operands
• Destination cannot be an immediate data
• SUB AX, 0100H
• SUB AX, BX
• SUB AX, [5000H]
• SUB [5000H], 0100H
 SBB
• Subtract the source operand and borrow flag
from the destination operand
• SBB AX, 0100H
• SBB AX, BX
• SBB AX, [5000H]
• SBB [5000H], 0100H
 CMP
• Compares the source operand with destination operand
• Source operand
– Register/immediate data/memory location
• Destination operand
– Register/memory location
• Does not store the result anywhere
• Zero flag set – If both the operands are equal
• Carry flag is set – If the source operand > destination
operand
• Carry flag is reset - If the source operand < destination
operand
• CMP
 DAA
• Decimal Adjust Accumulator
• Convert the result of the addition of two packed BCD
numbers to a valid BCD number
• The result has to be only in AL
• AL = 53 CL = 29
• ADD AL, CL ;
• AL (AL) + (CL) ;
• AL  53 + 29 ;
• AL  7C
• DAA ;
• AL  7C + 06 (as C>9) ;
• AL  82
DAA
 DAS
• Decimal Adjust after Subtraction
• Converts the result of the subtraction of two packed BCD
numbers to a valid BCD number
• The subtraction has to be in AL only
• AL = 75, BH = 46
• SUB AL, BH ;
• AL  (AL) - (BH) ;
• AL  2 F ;
• DAS ;
• AL 2 9 (as F>9, F - 6 = 9); CF = 1
 Logical Instructions
• AND : Logical AND
• Bit by bit ANDs source operand to the destination operand
• Source operand – immediate, register or a memory location
• Destination operand a register or a memory location
• The result is stored in the destination operand
• AND AX, 0008H
• AND AX, BX
• AND AX, [5000H]
• AND [5000H], AX
 Logical Instructions
• OR : Logical OR
– Bit by bit ORs the source operand to the destination
operand
– Result is stored in the destination operand
– OR AX, 0008H
– OR AX, BX
– OR AX, [5000H]
– OR [5000H], AX

• NOT : Logical Invert

– Complements the contents of an operand register or a
memory location, bit by bit
– NOT AX
– NOT [5000H]
 Logical Instructions
• XOR : Logical Exclusive OR
– Bit by bit XORs the source operand to the destination
operand
– The result is stored in the destination operand.
– XOR AX, 0098H; XOR AX, BX; XOR AX, [5000H]
• TEST : Logical Compare Instruction
– Bit by bit logical AND operation on the two operands
– Each bit of the result is set to 1 if corresponding bits of
both the operands are 1 else result bit is reset to 0
– The result of this ANDing operation is not available for
further use, but flags are affected
– TEST AX, BX; TEST [0500], 06H ; TEST [BX] [SI], CX
 Logical and Arithmetic Left Shift
• SAL/SHL : Shift Logical/Arithmetic Left
• Shifts each bit in the specified destination to the left and 0
is stored at LSB position
• The MSB is shifted into the carry flag
• The number of shifts is indicated by count
• SAL / SHL destination, count
• SAL CX, 1
• SAL AX, CL
 Logical Right Shift
• SHR : Shifty Logical Right
• Shifts each bit in the specified destination to the right and 0
is stored at MSB position
• The LSB is shifted into the carry flag
• The number of shifts is indicated by count
• SHR destination, count
• SHR CX, 1; MOV CL, 05H; SHR AX, CL
 Arithmetic Right Shift
• SAR : Shift Arithmetic Right
• Shifts each bit in the specified destination some number of
bit positions to the right
• As a bit is shifted out of the MSB position, a copy of the old
MSB is put in the MSB position
• The LSB will be shifted into CF
• SAR destination, count
• SAR BL, 1 ; MOV CL, 05H; SAR DX, CL
 Rotate Instructions
• ROR Instruction : ROR destination, count
– Rotates all bits in a specified byte or word to the right
some number of bit positions
– LSB is placed as a new MSB and a new CF.
– ROR CX, 1; MOV CL, 05H; ROR BL, CL
 ROL
• ROL Instruction : Rotate Left without Carry
• Rotates all bits in a specified byte or word to the left some
number of bit positions
– MSB is placed as a new LSB and a new CF
– ROL destination, count
– ROL CX, 1 MOV CL, 05H; ROL BL, CL
 RCL
• RCL Instruction :
– Rotates all bits in a specified byte or word some number
of bit positions to the left along with the carry flag
– MSB is placed as a new carry and previous carry is place
as new LSB
– RCL destination, count
– RCL CX, 1 ; MOV CL, 04H ; RCL AL, CL
 RCR
• RCR Instruction : RCR destination, count
– Rotates all bits in a specified byte or word some number
of bit positions to the right along with the carry flag
– LSB is placed as a new carry and previous carry is place
as new MSB.
– RCR CX, 1; MOV CL, 04H; RCR AL, CL
STRING MANIPULATION
INSTRUCTIONS
 String Manipulation Instructions

REP
 Used as a prefix to other instructions.
 The instruction to which the prefix is provided, is
executed repeatedly
until the CX becomes zero.
 When CX=0, the execution proceeds to next
instruction in sequence.
 String Manipulation Instructions
MOVSB/MOVSW
 Source string starting byte  SI + DS
 Destination string starting byte  DI + ES.
 Use REP as prefix to MOVS & length of the byte/ word string
in CX.
 String Manipulation Instructions
CMPSB/CMPSW
 Used to compare two strings of bytes or words.
 Length of the byte/ word string in CX.
 If both bytes/ words are equal, ZF is set.
 Strings are stored in DS:SI & ES:DI
 REP is used to repeat the comparison operation till CX=0 or
condition specified by REP fails.
CMPSB/CMPSW - Example
String Manipulation Instructions
Process Control & Branch
Transfer
Instructions
 Branch Instructions
• Transfers the flow of execution of the program to a new
address specified in the instruction directly or indirectly
• CS and IP registers get loaded with new values of CS and IP
corresponding to the location to be transferred

• Unconditional Branch Instructions

• Conditional Branch Instructions
 Unconditional Branch Instructions

• Execution control is transferred to the specified location

independent of any status or condition
• The CS and IP unconditionally modified to the new CS and
IP

• CALL : Unconditional Call

– Call a Subroutine (Procedure) from a main program
– Address of procedure may be specified directly or
indirectly
– NEAR CALL i.e., ±32K displacement
– FAR CALL i.e., anywhere outside the segment
– Stores the incremented IP & CS onto the stack and loads
the CS & IP registers with segment and offset addresses
of the procedure to be called
 Unconditional Branch Instructions

• RET: Return from the Procedure

– At the end of the procedure, the RET instruction must be
executed
– Previously stored content of IP and CS along with Flags
are retrieved into the CS, IP and Flag registers from the
stack
– Execution of the main program continues further
• INT N: Interrupt Type N
– In the interrupt structure of 8086, 256 interrupts are
defined corresponding to the types from 00H to FFH
– Type byte N is multiplied by 4 and the contents of IP and
CS of the interrupt service routine will be taken from
memory block in 0000 segment
• INTO: Interrupt on Overflow
– Executed, when the overflow flag OF is set.
– This is equivalent to a Type 4 Interrupt instruction
• JMP: Unconditional Jump
– Unconditionally transfers the control of execution to the
specified address using an 8-bit or 16-bit displacement
– No Flags are affected by this instruction
• IRET: Return from ISR
– Values of IP, CS and Flags are retrieved from the stack to
continue the execution of the main program.
• LOOP : LOOP Unconditionally
• This instruction executes the part of the program from the
Label or address specified in the instruction upto the LOOP
instruction CX number of times
• At each iteration, CX is decremented automatically and
JUMP IF NOT ZERO structure.
• MOV CX, 0004H
• MOV BX, 7526H
• Label 1 MOV AX, CODE1
• OR BX, AX
• AND BX, AX
• LOOP Label 1
 Conditional Branch Instructions
• Execution control is transferred to the address specified
relatively in the instruction, provided the condition implicit
in the Opcode is satisfied
• Otherwise execution continues sequentially.
Conditional Loop Instruction
Flag Manipulation Instructions
Machine Control Instructions
• https://www.youtube.com/watch?v=PlI5MLA4a48
MIN & MAX MODEL
Pin Diagram
 Common signals
8086 Microprocessor
AD0-AD15 (Bidirectional)
Address/Data bus

Low order address bus; these are multiplexed

with data.

When AD lines are used to transmit memory

address the symbol A is used instead of AD,
for example A0-A15.

When data are transmitted over AD lines the

symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
Bit S 4 and S 3 together from a 2 bit
binary code that identifies which of S 4S 3
the 8086 internal segment registers 0 0 Extra Segment
are used to generate the physical 0 1 Stack Segment
address that was output on the 1 0 code or No segment
address bus during the current bus 1 1 Data Segment 98
cycle.
 Common signals
8086 Microprocessor

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to indicate the transfer of data
using data bus D8-D15. It is multiplexed with
status signal S7.
It is low during T1 for read, write and INTA
cycles, whenever a byte is to be transferred
on the higher byte of the data bus

MN/

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

The signal is used indicate the peripherals

that the processor is performing memory or
I/O read operation. It is active low and shows
the state for T2, T3, Tw of any read cycle.

99
8086 Microprocessor Common signals

TEST

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after execution of

the WAIT instruction and will resume execution
only when the is made low by an active
hardware.

This is used to synchronize an external activity

to the processor’s internal operation.

READY

This is the acknowledgement from the slow I/O

device or memory that they have completed the
data transfer.

The signal made available by the devices is

synchronized by the 8284A clock generator to
provide ready input to the 8086.

The signal is active high.

100
 Common signals
8086 Microprocessor

RESET (Input)

Causes the processor to immediately terminate

its present activity and start execution from
FFFF0H.

The signal must be active HIGH for at least four

clock cycles.

101
8086 Microprocessor Common signals

CLK

The clock input provides the basic timing for

processor operation and bus control activity. Its
an asymmetric square wave with 33% duty
cycle.

102
8086 Microprocessor Common signals

INTR Interrupt Request

This is a level triggered input. This is sampled

during the last clock cycles of each instruction
to determine the availability of the request. If
any interrupt request is pending, the processor
enters the interrupt acknowledge cycle.

This signal is active high and internally

synchronized.

103
MIN & MAX MODEL
 Minimum mode signals
8086 Microprocessor Pins 24 -31

For minimum mode operation, the MN/ is tied to VCC (logic

high)

8086 itself generates all the bus control signals

DT/ (Data Transmit/ Receive) Output signal from the processor to

control the direction of data flow through the data transceivers

(Data Enable) indicates the availability of valid data over the

address/ data lines. It is used to enable the transceivers to separate
the data from the muxed address/data signal. It is active from the
middle of T2 until the middle of T4.

ALE (Address Latch Enable) Indicates the availability of valid address on

the address/data lines

M/ Used to differentiate memory access and I/O access. For memory

reference instructions, it is high. For IN and OUT instructions, it is
low.

Write control signal; asserted low Whenever processor writes data

to memory or I/O port

(Interrupt Acknowledge) When the interrupt request is accepted by

the processor, the output is low on this line.

105
 Minimum mode signals
8086 Microprocessor

HOLD Indicates to the processor that another master is requesting the

bus access. Processor issues HLDA in the middle of next clock
cycle, after completing the current bus instruction cycle.

Usually used by the DMA controller to get the control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the processor to the

bus master requesting the control of the bus through HOLD.

The acknowledge is asserted high, when the processor accepts

HOLD.

RD signal remains tristated

106
 Maximum mode signals
8086 Microprocessor
During maximum mode operation, the MN/ is grounded
(logic low)

Pins 24 -31 are reassigned

,, Status signals which indicate the type of operation being carried

out by the processor. These become active during T4 of the
previous cycle and remain active during T1 & T2 of the current bus
cycle. Status lines return to passive during T3 so that they may
again become active for the next bus cycle during T4.

107
 Maximum mode signals
8086 Microprocessor
During maximum mode operation, the MN/ is grounded
(logic low)

Pins 24 -31 are reassigned

, (Queue Status) The processor provides the status of queue in these

lines.

The queue status can be used by external device to track the

internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as shown in the

table.

108
 Maximum mode signals
8086 Microprocessor
During maximum mode operation, the MN/ is grounded
(logic low)

Pins 24 -31 are reassigned

, (Bus Request/ Bus Grant) These requests are used by other local
bus masters to force the processor to release the local bus at the
end of the processor’s current bus cycle.

These pins are bidirectional.

The request on will have higher priority than

An output signal activated by the LOCK prefix instruction.

Remains active until the completion of the instruction prefixed by

LOCK.

The 8086 output low on the pin while executing an instruction

prefixed by LOCK to prevent other bus masters from gaining control
of the system bus.

109
 Peripheral Interfacing
• Microprocessor based system design involves interfacing of the
processor with one or more peripheral devices for the purpose of
communication with various input and output devices connected to it.

• During the early days of the microprocessor revolution, these

techniques required complex hardware making the design highly
complex and time consuming.

• INTEL have developed a large number of general and special

purpose peripheral devices, most of them being single chip circuits.
They are also programmable devices.

• Hence these peripheral devices are found to be of tremendous use to

a system designer.
 Types of Devices

• General purpose peripherals and

• Special purpose peripherals

 General Purpose Peripheral
•
Devices
Perform a task but may be used for interfacing a variety
of I/O devices to microprocessor.

• The general purpose devices are given below:

• Simple I/O -- (Non-programmable)
• Programmable peripheral Interface (PPI) – (8255)
• Programmable Interrupt Controller – (8259)
• Programmable DMA Controller – (8237/8257)
• Programmable Communication Interface – (8251)
• Programmable Interval Timer – (8253/8254)
 Special Purpose Peripheral
•
Devices
These peripherals are more complex and more
expensive than general purpose peripherals.

• The special function peripherals are

• Programmable CRT Controller
• Programmable Floppy Disc Controller
• Programmable Hard Disc Controller
• Programmable Keyboard and display interface.

• The functioning of these devices varies depending on

the type of I/O device they are controlling.
 Programmable peripheral
interface-8255
• 8255 is a widely used, programmable, parallel I/O
device.

• The PPI has three programmable I/O ports viz.,

Port A, Port B and Port C each of 8 bit width.

• Port C can be treated as two ports – Port C upper

(PC7-4) and Port lower (PC3– 0) and these two can
be independently programmed as INPUT or
OUTPUT ports.
 Programmable peripheral
interface-8255
• It is a general purpose programmable I/O device which is
compatible with all INTEL processors and also most other
processors.

• It provides 24 I/O pins which may be individually

programmed in two groups. The two groups of I/O pins are
named as Group A and Group B.

• It is available in 40 pin DIP.

• 8255 is mainly programmed in two modes (a) I/O mode and

(b) bit set/reset mode (BSR) mode. The I/O mode is further
divided into three modes: Mode 0, Mode 1, and Mode 2.
Block Diagram - 8255
 8255 - Architecture
• The 8-bit data bus buffer is controlled by R/W Control
logic.
• The R/W control logic manages all of the internal/
external transfers of both data and control words.
• Inputs to R/W : A1, A0 and RESET
• The 8-bit, tri-state, bidirectional buffer is used to
interface the internal data bus with the external
system data bus.
• This buffer receives or transmits data upon execution
of input or output instructions by 8086.
• The control word or status information is also
transferred through this buffer.
 8255 - Architecture
Group A Control and Group B Control
• Group A control block controls - PortA and PC7-PC4.
• Group B controls block controls - Port B and PC3- PC0

Data Bus buffer :

• 8 bit, 3-state bidirectional used to interface the internal data bus of 8255 to
the external system data bus.
• Output data from the MPU to the ports or control register and the input data
to the MPU from the ports or status register are all pushed through the buffer.
• It is controlled by the read/write control logic.

Control Logic
• Manage all internal and external transfer of data and control words.
• RD’, WR’, A1, A0 and RESET are inputs provided by MPU
• It issues commands to the individual group control blocks (Group A Control
and Group B Control)
Pin diagram -8255
 Modes of Operation
• Bit Set-Reset Mode (BSR) – used to set or reset its
individual port bits.

• I/O mode – 8255 ports works as programmable I/O ports

 Mode 0: Simple I/O mode
 Mode 1 : I/O with Handshaking mode
 Mode 2: Bidirectional data transfer mode
 BSR Mode
• To know in which mode the interface
is working we need to know the value
of Control word.
• Control word is a part of control
register in 8255 which specify an I/O
function for each port.
• This mode is used to set or reset the
bits of the Port-C only.
• For BSR mode always D7 will be 0.
• The (D3, D2, D1) will be 000 to 111.
• In this mode it affects only one bit of
Port C at a time.
• When user set the bit, it remains set
until user unset it.
• The user needs to load the bit pattern
in control register to change the bit.
 I/O Mode
Mode 0 : Basic Input/output
• provides simple input and output
operations for each of the three
ports.

• There are two 8-bitports (A and B)

and two 4-bit ports [C (lower)] and [C
(upper)].

• Any port can be an input port or an

output port.
Features:
• Outputs are latched and Inputs are
not latched.
• Ports do not have handshake or
interrupt capability
 Mode 1- Strobed I/O
• It provides means for transferring I/O data to or from a
specified port in conjunction with strobes or hand-shaking
signals.
• Port A and port B use the lines on port C for handshaking
signals.
Features,
 Two ports A and B function as 8 bit I/O ports.
 Each port uses three lines from port C as handshake
signals and remaining signals used for I/O functions
 Input and output data are latched
 Interrupt logic is supported
 Mode 1- 1
• When CPU wants to send data to slow peripheral device
like printer, it will send handshaking signal to printer to
tell whether it is ready or not to transfer the data.
• When printer will be ready, it will send one
acknowledgement to CPU then there will be transfer of
data through data bus.
 Mode 2
• In this mode only port A works, and port B can work
either in mode 0 or mode 1.

• Port A is used as bi-directional port with simultaneous

input and output capability.

• 6 bits port C are used as handshake signals.

• It also has interrupt handling capacity.

 Steps to Communicate with 8255
• Determine the addresses of Port A, B, C and Control
register according to Chip Select Logic and the Address
lines A0 and A1.

• Write a control word in control register.

• Write I/O instructions to communicate with peripherals

through port A, B, C.
 Steps to Communicate with 8255

CWR

Port Address
Steps to Communicate with 8255
ALP
 ROL
• ROL Instruction : Rotate Left without Carry
• Rotates all bits in a specified byte or word to the left some
number of bit positions
– MSB is placed as a new LSB and a new CF
– ROL destination, count
– ROL CX, 1 MOV CL, 05H; ROL BL, CL
ALP
ALP
 What is a Timer?

• Timer is a specialized type of device that is used to

measure timing intervals.
• Timers can be categorized into two main types:
– A timer which counts upwards from zero for measuring
elapsed time is often called a stopwatch
– a device which counts down from a specified time
interval is more usually called a timer.
• Timers may be designed in software or in hardware.
• When the microprocessor needs to generate a time delay,
the processor can elapse time simply using a delay routine.
 Why dedicated timer IC is
required?
• When a specialized IC is used for the generation of delays
and waveforms of different frequencies, microprocessor
becomes free from these tasks and this minimizes the
software overhead of the processor.
• Computer systems usually have at least one hardware
timer.
• These are typically digital counters that either increment or
decrement at a fixed frequency, which is often
configurable, and which interrupt the processor on reaching
zero.
• 8253 is one such hardware timer.
 What is 8253
What is 8253Timer?
Timer?
• Intel 8253 programmable Timer/ counter is a specially designed
chip for Intel microcomputer applications which require timing
and counting operations.
• Designed for being compatible with INTEL microprocessors like
8085,8086, 80X86..
• 8254 is an advanced version of 8253.
• 8253/8254 are programmable using three 16-bit counters.
• Each counter has 2 input pins, Clock & Gate, and 1 pin for “OUT”
output.
• To operate a counter, a 16-bit count is loaded in its register.
• On command, it begins to decrement the count until it reaches 0,
then it generates a pulse that can be used to interrupt the CPU.
 Features of 8253/54
• It has three independent 16-bit down counters.
• It can handle inputs clocks upto 10 MHz.
• These three counters can be programmed for either
hexadecimal or BCD count.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK
command, which allows the user to check the count value,
the programmed mode, the current mode, and the current
status of the counter.
 8253
8253
• The timers are basically 16 - bit down counters that counts
at HIGH to LOW transition of the CLK input.
• Each timer may be programmed to operate in one of the
six modes, independent of the mode of operation of the
other two timers.
• The timers are software programmable.
• Each counter can be programmed separately to divide the
input frequency by a number from 1 to 65536 (216)
Functional Block Diagram of
Functional Block
8253
diagram of 8253
 Pin diagram & Address
Pin DiagramDecoding
and Address Decoding
 Data Bus Buffer
• Data Bus buffer is a tri-state bidirectional buffer that
communicates with CPU whenever (Chip Select) is low.
• Data is transmitted or received by executing the OUT PORT
and IN PORT instructions.
• The functions of Data bus buffer are
1. Programming the counters through the control words
2. Writing count to the counters
3. Reading the count value from timers.
 ControlRegister
Control Register
• The control word register is used to program the timers in
different modes and control their operations.
• It is selected when A0 and A1 pins are 1,1. If are low, it
accepts information from the data bus buffer and stores it
in control word register.
• The word stored in CR controls the operation mode of each
counter, selection of hexadecimal or BCD counting and
loading of each count register.
• This register can be written into only no read operation of
this content is available
 Counters
Counters
• Each of the timers has three pins associated with it. Clock
(CLK) input, gate (GATE) control input and output (OUT).
• CLK - This clock input causes the timer to decrement.
Counters operate at HIGH to LOW transition (the negative
edge) of this clock input.
• GATE - The gate input pin is used to initiate or enable
counting. The exact effect of the gate signal depends on
which of the six modes of operation is chosen.
• OUTPUT- The output pin provides an output from the
timer. Its actual use depends on the mode of operation of
the timer. The counter can be read “on the fly” without
inhibiting gate pulse or clock input.
Operations of Various Control
Operations forInput
Various Control Inputs
 ControlWord
Control Word Format
Formate
 Modes of
Modes of 8253
8253
1. Mode 0 – Interrupt on Terminal Count
2. Mode 1 – Programmable Mono shot
3. Mode 2 – Rate Generator
4. Mode 3 – Square wave Generator
5. Mode 4 – S/w triggered Strobe
6. Mode 5 – H/w triggered Strobe
 Modes 0 – Interrupt on terminal
•
count
Output is initially low after the mode is set.
• Output remains low even after the count value is loaded in the
counter.
• Counter starts decrementing after the falling edge of the clock, if
the GATE input is high.
• Output will remain low until the Counter reaches zero.
• OUT then goes high and remains high until a new count or a new
Mode 0 Control Word is written into the Counter.
 Mode 1-Programmable Mono-
shot
• OUT is high until the count is loaded and the trigger is applied.
• OUT will go low on the CLK pulse following a trigger and will
remain low until the Counter reaches zero.
• OUT will then go high and remain high until the next count is
loaded or a trigger is applied.
 Mode 2 – Rate Generator
• This Mode functions like a divide-by-N counter.
• OUT will initially be high. When the initial count has decremented to 1,
OUT goes low for one CLK pulse.
• OUT then goes high again, the Counter reloads the initial count and the
process is repeated.
• Mode 2 is periodic; the same sequence is repeated indefinitely. For an
initial count of N, the sequence repeats every N CLK cycles.
 Mode 3 – Square Wave
Generator
• Mode 3 is similar to Mode 2 except for the duty cycle of OUT signal.
• OUT will initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count.
• Mode 3 is periodic; the sequence above is repeated indefinitely. An
initial count of N results in a square wave with a period of N CLK cycles.
• If the loaded count value N is odd, for (N+1)/2 pulses, OUT remains
high and for (N-1)/2 pulses, it is low.
 Mode 4 – Software Triggered

• OUT will be initially high. When the initial count expires, OUT will
go low for one CLK pulse and then go high again.
• Similar to Mode 2, except that the counter is not reloaded
automatically, count has to be reloaded.
 Mode 5 – Hardware Triggered
• OUT will initially be high.
• Counting is triggered by a rising edge of GATE.
• When the initial count has expired, OUT will go low for one CLK
pulse and then go high again.
• After writing the Control Word and initial count, the counter will
not be loaded until the CLK pulse after a trigger.
Example 1

Engr 4862 Microprocessors

 Example 2
• What instructions are needed to program Counter 0 for BCD counting
in mode 4? Initial count is 4788H.
• Solution :
Control Word = 00 11 100 1 = 39H
• Counter 0 LSB & MSB Mode 4 BCD
• MOV AL,39H
• OUT CWR,AL
• MOV AL,88
• OUT Counter0,AL ; Counter0 =8-bit address of counter0
• MOV AL,47
• OUT Counter0,AL
 Example 3
• What instructions are needed to program Counter 2 for binary
counting in mode1, with an initial count of A0H?
• Solution
• Control Word = 10 01 001 0 (92H)
• Program
• MOV AL, 92H
• OUT CWR,AL ; CWR= Address of Control Register
• MOV AL,0A0H
• OUT Counter2,AL ; Counter2 = 8-bit address of counter2
Port Address mapping
i. Square Wave – Mode 3
Count = Clock frequency / Square wave frequency
Clock frequency = 1.5 MHz
Square wave frequency = 1/time period = 1/1ms = 1 kHz
\ Count = 1.5 M/ 1 k = 1500
Control word for Counter 0:
0 0 1 1 0 1 1 1
ii. Generate Interrupt – Mode 0
Count = Clock frequency / Counter frequency
Clock frequency = 1.5 MHz
Counter frequency = 1/time period = 1/10ms = 0.1 kHz
\ Count = 1.5 M/ 0.1 k = 15000 = 3A98H
Control word for Counter 1:
0 1 1 1 0 0 0 0
iii. Generate Mono shot – Mode 1
Count = Clock frequency / Counter frequency
Clock frequency = 1.5 MHz
Counter frequency = 1/time period = 1/5ms = 0.2 kHz
\ Count = 1.5 M/ 0.2 k = 7500 =1D4CH
Control word for Counter 2:
1 0 1 1 0 0 1 0
 Memory Interfacing with 8086
• Memory is device used to store the information or
data

• Most of the memories used are semiconductor

memories because of their small size, high speed,
reliability and low cost

• It consist of mostly flip flops and some other

additional circuits for buffers
 Memory Interfacing with 8086
• Memory capacity
• The no of bits that a memory can store is called its capacity

• Memory organization
– Each memory chip contains 2N memory locations, where
N is the no of address pin on the chip

– Each location contains M bits, where M is the no of data

pins on the chip
– The entire chip will contain 2N X M bits
 Memory Interfacing with 8086
Address pins
• Address Lines: The input lines that select a
memory location within the memory device.
• Decoders are used, inside the memory chip, to
select a specific location
• The number of address pins on a memory chip
specifies the number of memory locations.
 Memory Interfacing with 8086
Address pins
 Memory Interfacing with 8086
Data pins
• The data pins are typically bi- directional in read-
write memories.
• The number of data pins is related to the size of
the memory location .
• For example, an 8-bit wide (byte-wide) memory
device has 8 data pins
• The number of data lines (m-bits) determines the
size of each location in the memory.
 Memory Interfacing with 8086
Enable Lines:
• All memory devices have at least one Chip Select () or
Chip Enable () input, used to select or enable the
memory device.
• If a device is not selected or enabled then no data can
be read from, or written into it.
• The or input is usually controlled by the
microprocessor through the higher address lines via an
address decoding circuit.
 Memory Interfacing with 8086
Control Lines:

• RAM chips have two control input signals that specify

the type of memory operation: the Read () and the
Write () signals.

• Some RAM chips have a common Read/ Write (R/)

signal.

• ROM chips can perform only memory read operations

Memory Interfacing with 8086
 Memory Interfacing with 8086
• If the microprocessor has ‘n’ address lines, then it is
possible to address 2n =N memory locations.

• If only P memory locations are to be interfaced, then

least significant p address lines out of n lines are
required

• The remaining (n-p) higher order address lines may be

used to generate chip select signal using decoding
circuit
 Memory Interfacing with 8086
Address decoding
• In general all the address lines are not used by the
memory devices to select particular memory location

• The remaining lines are used to generate chip select

logic

• Two commonly used techniques for decoding address are

1) Absolute or full decoding
2) Partial or linear decoding
 Memory Interfacing with 8086
Full Decoding
• All of the higher address lines are decoded to select
memory chip, and the chip is selected only for the specified

Partial Decoding
• All the address lines are not used to generate chip select,
basically used in small systems
• Individual high order address lines are used to decode the
chip select for the memory chips using less hardware
• Disadvantages: Each memory location has more than one
address called roll-over addresses (fold back or shading)
 DOS & BIOS Interrupt

• Used to perform some very useful functions, such as

displaying data to monitor, reading data from keyboard.

• Used by identifying the interrupt option type, which is the

value stored in register AH.
 DOS & BIOS Interrupt

MS-DOS and the PC’s BIOS provide

a software connection between Application program
application program and the
underlying hardware
DOS Support
One can access the IBM PC
system hardware at one of three
general levels from assembly BIOS Support
language
1. Program the hardware directly
I/O peripheral Devices
2. Use ROM BIOS routines
3. Use MS-DOS calls
 DOS Function Calls
• MS-DOS provides all of the basic file manager and device
manager functions (required by most application programs)
• MS-DOS handles
– file I/O,
– character I/0,
– memory management, and other miscellaneous function

• MS-DOS is called via the int 21h instruction

• To select an appropriate DOS function, load ah register with a
function number before issuing the int 21h instruction
• Most DOS calls require other parameters as well
• Other parameters are passed in the CPU’s register set
 DOS Interrupt 21H

• When MS-DOS is loaded in the computer INT 21H is used to provide an

interrupt to perform some important functions.
• These are called DOS INT 21H function calls.
• Main function calls are data input/output through keyboard
• Example:

1. Option 1- Input a single character from keyboard

Register used:
AH=1
AL= the character inputted from keyboard
Ex:
MOV AH, 01 – option to input one character
INT 21H -invoke interrupt
 DOS Interrupt 21H

• Option 2- output a single character to the monitor

• Register used:
AH =2
DL = character to be displayed

EX:
MOV AH, 2
MOV DL, ‘A’
INT 21H
 DOS Interrupt 21H

• Option 9: output a string of data terminated by $ to

the monitor.
• Register used:
• AH=9
• DX = offset address of data to be displayed
Ex:
• MOV AH,09 ;option 9 to display string of data
• MOV DX, OFFSET mess1
• INT 21H ; invoke the interrupt
 DOS Interrupt 21H

• Option 0AH: Input a string of data from the keyboard

• Register used:
• AH=0AH
• DX = offset address of location where string will be stored
Ex:
• .DATA
• BUFFER1 DB 15,? 15 DUP(FF)
• MOV AH,0AH ;
• MOV DX, OFFSET Buffer1
• INT 21H ;
 DOS Interrupt 21H

• Option 4CH: Terminate a process, by returning control

to a parent process or to DOS.
• Register used:
• AH=4CH
• AL= binary return code
Ex:
• MOV AH,4CH ;
• INT 21H ;
 BIOS Interrupt

• To call a BIOS routine, one use one of the80x86’s int software

interrupt instructions
• The int instruction uses the following syntax: int value
• Value is some number in the range 0..255.
• Execution will cause the 80x86 to transfer control to one of 256
different interrupt handlers
• The interrupt vector table, starting at physical memory location
0:0, holds the addresses of these interrupt handlers
• Each address is a full segmented address, requiring four bytes
 BIOS Interrupt

• int 0 transfers control to the routine whose address is at

location 0:0
• int 1 transfers control to the routine whose address is at 0:4
• int 2 via 0:8
• int 3via 0:C, and
• int 4 via 0:10

• The IBM PC BIOS uses software interrupts 5 and 10h..1Ah to

accomplish various operations
• Therefore, the int 5, and int 10h.. int 1ah instructions provide
the interface to BIOS
 BIOS Interrupt

INT Function
• 5h Print Screen operation
• 10h Video display services
• 11h Equipment determination
• 12h Memory size determination
• 13h Diskette and hard disk services
• 14h Serial I/O services
• 15h Miscellaneous services
• 16h Keyboard services
• 17h Printer services
• 18h BASIC
• 19h Reboot
• 1Ah Real time clock services.
 BIOS Interrupt

• The INT 10H BIOS of the 8086 are used to communicate with
the user through the screen.

• Manipulation of screen text is done through INT 10H

• Example  changing colors of characters, background,

changing cursor locations, clearing screen.
 BIOS Interrupt 10H

• It Controls The Video Display

• Function Call 00: Select Video Mode

• Input Parameter:
• AH = 00H
• AL = Mode Number

• Function: It Changes The Display Mode And Clears The Screen

• AL = 00 40 X 25 Black And White
• AL = 04 320 X 200 Color
• AL= 10 640 X 350 X 16 Color