PIC (Peripheral Interface Controller) PIC Is A Family of Harvard Architecture Microcontrollers Made by

PIC (Peripheral interface controller)
INTRODUCTION
PIC is a family of Harvard architecture microcontrollers made by
Microchip Technology, derived from the PIC1640 originally developed
by General Instrument's Microelectronics Division. The name PIC
initially referred to "Peripheral Interface Controller"
PICs are popular with both industrial developers and hobbyists alike
due to their low cost, wide availability, large user base, extensive
collection of application notes, availability of low cost or free
development tools, and serial programming (and re-programming
with flash memory) capability.
CORE ARCHITECTURE
The PIC architecture is characterized by its multiple attributes:
 Separate code and data spaces (Harvard architecture) for

devices other than PIC32, which has a Von Neumann architecture.
 A small number of fixed length instructions
 Most instructions are single cycle execution (2 clock cycles),
with one delay cycle on branches and skips
 One accumulator (W0), the use of which (as source operand) is
implied (i.e. is not encoded in the opcode)
 All RAM locations function as registers as both source and/or
destination of math and other functions.
 A hardware stack for storing return addresses
 A fairly small amount of addressable data space (typically 256
bytes), extended through banking
 Data space mapped CPU, port, and peripheral registers
 The program counter is also mapped into the data space and
writable (this is used to implement indirect jumps).
There is no distinction between memory space and register space

because the RAM serves the job of both memory and registers, and
the RAM is usually just referred to as the register file or simply as the
registers.
Data space (RAM)

PICs have a set of registers that function as general purpose RAM.
Special purpose control registers for on-chip hardware resources are
also mapped into the data space. The addressability of memory
varies depending on device series, and all PIC devices have some
banking mechanism to extend addressing to additional memory. Later
series of devices feature move instructions which can cover the
whole addressable space, independent of the selected bank. In
earlier devices, any register move had to be achieved via the
accumulator.
To implement indirect addressing, a "file select register" (FSR) and
"indirect register" (INDF) are used. A register number is written to the
FSR, after which reads from or writes to INDF will actually be to or
from the register pointed to by FSR. Later devices extended this
concept with post- and pre- increment/decrement for greater
efficiency in accessing sequentially stored data. This also allows FSR
to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some high
pin count PIC18 devices.
Code space
The code space is generally implemented as ROM, EPROM or flash
ROM. In general, external code memory is not directly addressable
due to the lack of an external memory interface. The exceptions are
PIC17 and select high pin count PIC18 devices.
Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit
of addressability of the code space is not generally the same as the
data space. For example, PICs in the baseline and mid-range families
have program memory addressable in the same wordsize as the
instruction width, i.e. 12 or 14 bits respectively. In contrast, in the
PIC18 series, the program memory is addressed in 8-bit increments
(bytes), which differs from the instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in
number of (single word) instructions, rather than in bytes.
Stacks
PICs have a hardware call stack, which is used to save return
addresses. The hardware stack is not software accessible on earlier
devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking
in early series, but this greatly improved in the 18 series, making the
18 series architecture more friendly to high level language compilers.
Instruction set
A PIC's instructions vary from about 35 instructions for the low-end
PICs to over 80 instructions for the high-end PICs. The instruction set
includes instructions to perform a variety of operations on registers
directly, the accumulator and a literal constant or the accumulator and
a register, as well as for conditional execution, and program
branching.
Some operations, such as bit setting and testing, can be performed
on any numbered register, but bi-operand arithmetic operations
always involve W (the accumulator), writing the result back to either
W or the other operand register. To load a constant, it is necessary to
load it into W before it can be moved into another register. On the
older cores, all register moves needed to pass through W, but this
changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional
execution and branching. The skip instructions are 'skip if bit set' and
'skip if bit not set'. Because cores before PIC18 had only
unconditional branch instructions, conditional jumps are implemented
by a conditional skip (with the opposite condition) followed by an
unconditional branch. Skips are also of utility for conditional execution
of any immediate single following instruction.
The 18 series implemented shadow registers which save several
important registers during an interrupt, providing hardware support for
automatically saving processor state when servicing interrupts.
In general, PIC instructions fall into 5 classes:
1. Operation on working register (WREG) with 8-bit

immediate ("literal") operand. E.g. movlw (move literal to
WREG), andlw (AND literal with WREG). One instruction
peculiar to the PIC is retlw, load immediate into WREG and
return, which is used with computed branches to produce
lookup tables.
2. Operation with WREG and indexed register. The result
can be written to either the Working register (e.g. addwf reg,w).
or the selected register (e.g. addwf reg,f).
3. Bit operations. These take a register number and a bit
number, and perform one of 4 actions: set or clear a bit, and
test and skip on set/clear. The latter are used to perform
conditional branches. The usual ALU status flags are available
in a numbered register so operations such as "branch on carry
clear" are possible.
4. Control transfers. Other than the skip instructions
previously mentioned, there are only two: goto and call.
5. A few miscellaneous zero-operand instructions, such as
return from subroutine, and sleep to enter low-power mode.
PERFORMANCE
The architectural decisions are directed at the maximization of speed-
to-cost ratio. The PIC architecture was among the first scalar CPU
designs,[ and is still among the simplest and cheapest. The Harvard
architecture—in which instructions and data come from separate
sources—simplifies timing and microcircuit design greatly, and this
benefits clock speed, price, and power consumption.
The PIC instruction set is suited to implementation of fast lookup
tables in the program space. Such lookups take one instruction and
two instruction cycles. Many functions can be modeled in this way.
Optimization is facilitated by the relatively large program space of the
PIC (e.g. 4096 x 14-bit words on the 16F690) and by the design of
the instruction set, which allows for embedded constants. For
example, a branch instruction's target may be indexed by W, and
execute a "RETLW" which does as it is named - return with literal in
W.
Execution time can be accurately estimated by multiplying the
number of instructions by two cycles; this simplifies design of real-
time code. Similarly, interrupt latency is constant at three instruction
cycles. External interrupts have to be synchronized with the four clock
instruction cycle, otherwise there can be a one instruction cycle jitter.
Internal interrupts are already synchronized. The constant interrupt
latency allows PICs to achieve interrupt driven low jitter timing
sequences. An example of this is a video sync pulse generator. This
is no longer true in the newest PIC models, because they have a
synchronous interrupt latency of three or four cycles.
ADVANTAGES
The PIC architectures have these advantages:
 Small instruction set to learn

 RISC architecture
 Built in oscillator with selectable speeds
 Inexpensive microcontrollers
 Wide range of interfaces including I2C, SPI, USB, USART, A/D,
programmable Comparators, PWM, LIN, CAN, PSP, and Ethernet
LIMITATIONS
The PIC architectures have these limitations:
 One accumulator
 Register-bank switching is required to access the entire RAM of
many devices
 Operations and registers are not orthogonal; some instructions
can address RAM and/or immediate constants, while others can
only use the accumulator

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PIC (Peripheral interface controller)

 Separate code and data spaces (Harvard architecture) for

There is no distinction between memory space and register space

Data space (RAM)

1. Operation on working register (WREG) with 8-bit

 Small instruction set to learn

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