Seminar: 8255A PPI

Seminar
On
8255A PPI
Submitted by
Name – Ankit Anand

Roll no. – 16/ECE/122
University Roll – 10300316122
Department of Electronics and communication Engineering
Haldia Institute of Technology, Haldia
8255A PPI
It is a general purpose programmable Input-Output device designed to
interface the CPU(Microprocessor) with its outside world such as ADC,
DAC, Keyboard .
It is a 40 pin IC having total 24 I/O pins consisting of three 8-bit parallel
I/O ports (i.e. PORT A, PORT B, PORT C). The ports can be programmed to
function either as input port or as an output port in different operating
modes. It requires 4 internal addresses and has one logic low chip select
pin. Its main function is to interface peripheral devices to microprocessor.
It is basically used for parallel data transfer which operates in mainly two
modes. They are-
1. BSR Mode
2. I/O Mode
Block Diagram of 8255A PPI Pin Diagram of 8255A PPI
Function of Pins
PIN Function
D0-D7 (Data Bus) These are bi-directional data bus lines which are connected to the system bus which are
used to transfer data and control word from microprocessor to 8255 or vice-versa.
PA0-PA7 (Port A) These are 8 Bit bidirectional I/O pins used to send data to output device and to receive
data from input device. It functions as an 8 Bit data output latch/buffer when used in
output mode and as an 8 Bit data input latch/buffer when used in input mode.
PB0-PB7 (Port B) These are 8 Bit bidirectional I/O pins used to send data to output device and to receive
data from input device. It functions as an 8 Bit data output latch/buffer when used in
output mode and as an 8 Bit data input latch/buffer when used in input mode.
PC0-PC7 (Port C) These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC0) and PCU
(PC7-PC4).these groups can individually transfer data in or out when programmed for
simple I/O, and used as handshake signals when programmed for handshake or
bidirectional modes.
RD When this pin is low, the CPU can read data in the ports or the status word through the
data bus buffer.
WR When this pin is low, the CPU can write data on the ports or in the control register
through the data bus buffer.
CS This pin can be enabled for data transfer operation between the CPU and 8255.
RESET This pin is used to reset 8255.i.e control register gets cleared and all the ports are set
to the input mode .
A0-A1 The selection of input port and control word register is done by using A0 and A1 pins
In conjunction with RD and WR pins.
Interfacing
Interfacing a microprocessor is to connect it with various peripherals to
perform various operations to obtain a desired output.
It can be done in two ways:-

 Memory Interfacing (Memory Mapped I/O)
 I/O interfacing (I/O Mapped I/O)
Memory Mapped I/O
Memory mapped I/O is a scheme where an I/O device is mapped into the
address space of the system, as if it were RAM. This allows regular memory
reads and writes to control a device.
Device address is of 16 bit that means A0 to A15 lines are used to generate
device address.
 MEMR and MEMW control signals are used to control read and write I/O
operations.
 Maximum number of I/O devices are 65536.
 Data transfer is between any register and I/O device.
Examples:- MOV R M, ADD M, etc.
Interfacing In Memory Mapped I/O
To get absolute address, all remaining address lines are used to decode the
address for 8255.
I/O Mapped I/O
I/O mapped I/O(also known as port mapped I/O) uses a separate, dedicated
address space and is accessed via a dedicated set of microprocessor instructions.
Device address is of 8 Bit which means A0 to A7 or A8 to A15 lines are used to
generate device address.
 IOR and IOW control signals are used to control read and write I/O operations.
 Data transfer is between Accumulator and I/O device.
 Maximum number of I/O devices are 256.
 Decoding 16 bit address may requires less hardware.
Examples:- IN, OUT
Interfacing In I/O Mapped I/O
Ports A7 A6 A5 A4 A3 A2 A1 A0 Address
Port A 0 0 0 0 0 0 0 0 00H
Port B 0 0 0 0 0 0 0 1 01H
Port c 0 0 0 0 0 0 1 0 02H
Control 0 0 0 0 0 0 1 1 03H
register
Operating Modes of 8255
There are two main operational modes of 8255:
Input/output mode
Bit set/Reset mode(BSR Mode)
I/O mode is again classified into three types-

• Mode 0
• Mode 1
• Mode 2
MODE 0
In this mode, the ports can be used for simple input/output operations without handshaking. If
both port A and B are initialized in mode 0, the two halves of port c can be either used together
as an additional 8-bit port, or they can be used as individual 4-bit port.
Since the two halves of port C are independent, they may be used such that one-half is initialized
as an input port while the other one as an output port.
Mode 0 has the following features :
• O/p are latched.
• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.
MODE 1
When we wish to use port A or port B for handshake input or output operation, we initialize that
port in mode 1. For port B in this mode (irrespective of whether is acting as an input port or
output port), PC0, PC1 and PC2 pins function as handshake lines.
The mode 1 has following features:
• Two ports i.e. port A and B can be use as 8-bit i/o port.
• Each port uses three lines of port c as handshake signal and remaining two signals can be function as i/o port.
• Interrupt logic is supported.
• Input and Output data are latched.
MODE 2
Only group A can be initialized in this mode. Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins
PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can be
used as input/output lines if group B is initialized in mode 0. In this mode, the 8255 may be used
to extend the system bus to a slave microprocessor.
Control Word Format in I/O Mode
D7
Control Word Format in BSR Mode
D7
D1
D2
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

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Seminar

Name – Ankit Anand

It can be done in two ways:-

I/O mode is again classified into three types-

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

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