CprE 281:

Digital Logic

Instructor: Alexander Stoytchev

http://www.ece.iastate.edu/~alexs/classes/
Counters & Solved Problems

CprE 281: Digital Logic

Iowa State University, Ames, IA
Copyright © 2013
 Administrative Stuff
• Homework 9 is out

• It is due on Monday Nov 7, 2016

Counters
 T Flip-Flop
(circuit and graphical symbol)

[ Figure 5.15a,c from the textbook ]

 The output of the T Flip-Flop
divides the frequency of the clock by 2
A three-bit up-counter

[ Figure 5.19 from the textbook ]

 A three-bit up-counter

The first flip-flop changes

on the positive edge of the clock

[ Figure 5.19 from the textbook ]

 A three-bit up-counter

The first flip-flop changes The second flip-flop changes

on the positive edge of the clock on the positive edge of Q0

[ Figure 5.19 from the textbook ]

 A three-bit up-counter

The first flip-flop changes The second flip-flop changes The third flip-flop changes
on the positive edge of the clock on the positive edge of Q0 on the positive edge of Q1

[ Figure 5.19 from the textbook ]

 A three-bit up-counter

1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

[ Figure 5.19 from the textbook ]
 A three-bit up-counter

1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit The propagation delays get longer

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

[ Figure 5.19 from the textbook ]
A three-bit down-counter

[ Figure 5.20 from the textbook ]

 A three-bit down-counter

1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram [ Figure 5.20 from the textbook ]

Synchronous Counters
A four-bit synchronous up-counter

[ Figure 5.21 from the textbook ]

 A four-bit synchronous up-counter

The propagation delay through all AND gates combined must

not exceed the clock period minus the setup time for the flip-flops

[ Figure 5.21 from the textbook ]

A four-bit synchronous up-counter

1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram [ Figure 5.21 from the textbook ]

Derivation of the synchronous up-counter
Clock cycle Q2 Q1 Q0
Q1 changes
0 0 0 0
1 0 0 1 Q2 changes
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

[ Table 5.1 from the textbook ]

Derivation of the synchronous up-counter
Clock cycle Q2 Q1 Q0
Q1 changes
0 0 0 0
1 0 0 1 Q2 changes
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

T0= 1
T1 = Q0
T2 = Q0 Q1
[ Table 5.1 from the textbook ]
A four-bit synchronous up-counter

T0= 1
T1 = Q0
T2 = Q0 Q1
[ Figure 5.21 from the textbook ]
In general we have

T0= 1
T1 = Q 0
T2 = Q 0 Q 1
T3 = Q0 Q1 Q2
…
Tn = Q0 Q1 Q2 …Qn-1
Adding Enable and Clear Capability
Inclusion of Enable and Clear capability

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear_n

[ Figure 5.22 from the textbook ]

Inclusion of Enable and Clear capability

This is the new thing relative to

the previous figure, plus the clear_n line

Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear_n

[ Figure 5.22 from the textbook ]

Providing an enable input for a D flip-flop

[ Figure 5.56 from the textbook ]

Synchronous Counter with D Flip-Flops
A four-bit counter with D flip-flops

[ Figure 5.23 from the textbook ]

Counters with Parallel Load
A counter with parallel-load capability

[ Figure 5.24 from the textbook ]

Reset Synchronization
 Motivation
• An n-bit counter counts from 0, 1, …, 2n-1

• For example a 3-bit counter counts up as follow

 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …

• What if we want it to count like this

 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, …

• In other words, what is the cycle is not a power of 2?

What does this circuit do?

[ Figure 5.25a from the textbook ]

A modulo-6 counter with synchronous reset

1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

(b) Timing diagram

[ Figure 5.25 from the textbook ]
A modulo-6 counter with asynchronous reset

1 T Q T Q T Q
Q0 Q1 Q2

Clock Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

[ Figure 5.26 from the textbook ]
A modulo-6 counter with asynchronous reset

1 T Q T Q T Q
Q0 Q1 Q2

Clock Q Q Q

(a) Circuit The number 5 is displayed

for a very short amount of time
Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

[ Figure 5.26 from the textbook ]
Other Types of Counters
(Section 5.11)
 A two-digit BCD counter
• 2: Parallel-load four-bit counter
 Figure 5.24
• Each counts in binary
 0-9
• Resets generated on 9
 Reset by loading 0’s
• Second digit enabled by a 9 on first counter
A two-digit BCD counter

[ Figure 5.27 from the textbook ]

 A two-digit BCD counter

What is this?

[ Figure 5.27 from the textbook ]

It is a counter with parallel-load capability

[ Figure 5.24 from the textbook ]

A two-digit BCD counter
 Zeroing the BCD counter

1
1

1
1

Setting "Clear" to 1,
zeroes both counters.
[ Figure 5.27 from the textbook ]
 Zeroing the BCD counter

0
0
0
0
0
1
1

0
0
0
0
0
1
1

Setting "Clear" to 1,
zeroes both counters.
[ Figure 5.27 from the textbook ]
 How to zero a counter
0

Set all parallel load

input lines to zero.
[ Figure 5.24 from the textbook ]
 How to zero a counter
0
0

0
0

0
0

0
0

Set "Load" to 1, to open the

"1" line of the multiplexers. 1
[ Figure 5.24 from the textbook ]
 How to zero a counter
0 0
0

0 0
0

0 0
0

0 0
0

When the positive edge of the

clock arrives, all outputs 1
are set to zero together. [ Figure 5.24 from the textbook ]
 When Clear = 0

When "Clear" is equal to 0,

the two OR gates depend only
on the feedback connections. [ Figure 5.27 from the textbook ]
Enabling the second counter

[ Figure 5.27 from the textbook ]

 Enabling the second counter

0
0
0
0
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

1
1
0
0
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

2
0
1
0
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

3
1
1
0
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

4
0
0
1
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

5
1
0
1
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

6
0
1
1
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

7
1
1
1
0

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

8
0
0
0
1

0
0
0
0
0

The counter for the most

significant digit is disabled
most of the time.
 Enabling the second counter

9
1
0
0
1

0
0
0
0
0

It is enabled only when

the first counter is at 9.
 Enabling the second counter

9
1
0
0
1
1

0
0
0
0
0

At the same time the first

counter is reset.
 Enabling the second counter

0
0
0
0
0
0

1
1
0
0
0

At the same time the first

counter is reset.
Enabling the second counter

1
1
0
0
0
0

1
1
0
0
0
Enabling the second counter

2
0
1
0
0
0

1
1
0
0
0
...
Enabling the second counter

8
0
0
0
1
0

1
1
0
0
0
Enabling the second counter

9
1
0
0
1
1

1
1
0
0
0
Enabling the second counter

0
0
0
0
0
0

2
0
1
0
0
Enabling the second counter

1
1
0
0
0
0

2
0
1
0
0
...
Enabling the second counter

8
0
0
0
1
0

9
1
0
0
1
Enabling the second counter

9
1
0
0
1
1

9
1
0
0
1
Enabling the second counter

9
1
0
0
1
1

9
1
0
0
1
1

1
Enabling the second counter

0
0
0
0
0
0

0
0
0
0
0
0

0
Enabling the second counter

1
1
0
0
0
0

0
0
0
0
0
0

0
 N-bit ring counter
 1000, 0100, 0010, 0001, 1000…….
 Reset
• Set start to 1
• Sets output to 1000
N-bit ring counter

[ Figure 5.28a from the textbook ]

 4-bit ring counter
 Use a 2-bit counter
• 00, 01, 10, 11, 00……..
 2-4 Decoder
• 1000, 0100, 0010, 0001, 1000……..
4-bit ring counter

[ Figure 5.28b from the textbook ]

 Johnson Counter
 1-bit changes at a time
 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
 Begin with a reset of all flip-flops

 An n-bit Johnson counter has a counting

sequence of length 2n
Johnson counter

[ Figure 5.29 from the textbook ]

Timing Analysis of Flip-Flop Circuits
(Section 5.15)
 Timing Review
• tsu: setup time
• th: hold time
• tcQ: propogation delay
 Timing Example
• tsu: 0.6ns
• th: 0.4ns
• tcQ: 0.8ns to 1.0ns
 Which value to use?
• Logic gate delay: 1+0.1k
 k is equal to the number of inputs
• Tmin = tsu + tcQ + tnot = 0.6 + 1.0 + 1.1 = 2.7ns
• Fmax = 1/Tmin = 370.37MHz

• Check for hold violations

 Fastest Q can change = tcQ + tnot = 0.8 + 1.1 = 1.9ns
 1.9ns > 0.4ns therefore no hold violations
Timing Example: 4-bit counter

[ Figure 5.67 from the textbook ]

 Timing Example: 4-bit counter
• Look for longest path
 Q0 to Q3
• Propagation delay of Q0
• 3 AND propagation delays
• 1 XOR propagation delay
• Setup delay for Q3

• Tmin = 1.0 + 3(1.2) + 1.2 + 0.6 = 6.4ns

• Fmax = 1/6.4ns = 156.25MHz

• Check for hold violations

 Fastest Q can change = tcQ + tXOR = 0.8 + 1.2 = 2ns
 2.0ns > 0.4ns therefore no hold violations
Timing Example: Clock Skew

Figure 5.68. A general example of clock skew.

Skew Timing Example: 4-bit counter
• Q3 now has a clock slew delay: 1.5ns
 T = 1.0 + 3(1.2) + 1.2 + 0.6 - 1.5 = 4.9ns
• Now might not be the longest path
• Check Q0 to Q2
 T = 1.0 + 2(1.2) + 1.2 + 0.6 = 5.2ns
• Fmax = 1/5.2ns = 192.31MHz
Example 5.22
 Faster 4-bit Counter
• Want to increase the speed of the 4-bit counter
• Use similar method as used in 4-bit adder
• Remove series AND gates
A faster 4-bit counter

[ Figure 5.75 from the textbook ]

 Faster 4-bit Counter
• Longest path: Q0 to Q3
• Tmin = tcQ0 + tAND + tXOR + tsu
• =1.0 + 1.4 + 1.2 + 0.6 = 4.2ns
• Fmax = 1/4.2ns = 238.1MHz > 156.25MHz
Reaction Timer Circuit
(Section 5.14)
 Problem Statement
• Want to design a reaction timer
• Circuit turns on light (LED)
• Person then presses switch
• Measures time from LED on until the switch is
pressed
 Clock Divider
• Input: 102.4kHz
• Output: 100Hz
• 10-bit Counter to divide

• Output Frequency = 102.4k / 2^10 = 100Hz

A reaction-timer circuit

[ Figure 5.61 from the textbook ]

 Functionality of circuit
 Push switch
• Nominally 1
 DFF to keep track of the state
 Two-digit BCD counter
• Output goes to converters to a 7-segment display
 Start-up
• Assert the Reset signal
– Clears counter
– Clears flip-flop
• Assert w=1 for one cycle
• Once switch is hit
– Clears flip-flop
– Stops counting
Push-button switch, LED, and 7-segment displays

[ Figure 5.61c from the textbook ]

Examples of Solved Problems
(Section 5.17)
Example 5.18
Figure 5.70. Circuit for Example 5.18.
Example 5.19
Figure 5.71. Circuit for Example 5.19.
Figure 5.72. Summary of the behavior of the circuit in Figure 5.71.
Example 5.20
 Vending machine example
• Inputs N, D, Q, Coin, Resetn
 N, D, Q: nickel, dime, quarter
 Coin: pulsed when a coin is entered
• Used to store values into register
 Resetn: resets the register value to zero
• Add up new coin with old value
 Store new sum into old value register
• See if total is above thirty cents
 If so output Z goes high
Circuit for Example 5.20

[ Figure 5.73 from the textbook ]

Questions?
THE END