Nov Dec 2023

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Total No. of Questions : 8] SEAT No.

8
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P9102 [Total No. of Pages : 2

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S.E. (Electronics / E & TC / Computer)

5s
DIGITAL CIRCUITS

7:0
02 91
(2019 Pattern) (Semester-III) (204182)

9:3
0
40
Time : 2½ Hours] 1/0 13 [Max. Marks : 70
0
Instructions to the candidates:
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1) Solve Q.No.1 or Q.No.2, Q.No.3 or Q.No.4, Q.No.5 or Q.No.6, Q.No.7 or Q.No.8.


2) Neat diagrams must be drawn wherever necessary.
E
80

3) Figures to the right indicate full marks.

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C

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4) Use of Calculator is allowed.

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5) Assume suitable data, if necessary.
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Q1) a) Explain binary subtraction using l’s compliment and two’s compliment
8.2

5s
method with example. [6]
.24

7:0
91
b) Design and explain 3-bit parity generator circuit. [6]
49

9:3
30

c) Implement 1:8 demux using 1:4 demux. [6]


40
01
02

OR
1/2
GP

Q2) a) Design and explain 2-bit comparator circuit using logic gates. [6]
1/0
CE

b) Implement 16:1 Mux using 4:1 Mux. [6]


80

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c) Explain Look ahead carry generator circuit. [6]


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8.2

5s

Q3) a) Explain working of SR Flip flop with neat Block diagram and truth table.
.24

7:0
91

[6]
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9:3
30

b) Convert JK flip flop into D flip flop. [6]


40
01
02

c) Design and implement 2-bit synchronous counter using T flip flop. [5]
1/2
GP

OR
1/0

Q4) a) Explain working of JK Flip flop with neat Block diagram and truth table.
CE
80

[6]
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b) Convert SR flip flop into T flip flop. [6]


16
8.2

c) Write short note on Shift registers. [5]


.24

P.T.O.
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Q5) a) Design the sequential circuit for the given state diagram using T flip flop.

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[9]

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5s
7:0
02 91
9:3
0
40
1/0 13
0
1/2
.23 GP

b) Design and implement circuit using D flip flop to detect the following
E

binary sequence 110. [8]


80

8
C

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Q6) a) Draw ASM chart for 2 bit binary counter having enable line E such that:
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E=1, Count Enable and E=0, Count Disable. [9]
8.2

5s
b) Write short note on state reduction with suitable example. [8]
.24

7:0
91
49

Q7) a) Explain the block diagram of memory unit? [9]


9:3
30

b) Explain FPGA architecture. [9]


40

OR
01
02

Q8) a) Design and implement Full Subtractor using PAL? [9]


1/2
GP

b) Explain CPLD architecture. [9]


1/0
CE
80

8
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.23

   ic-
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tat
8.2

5s
.24

7:0
91
49

9:3
30
40
01
02
1/2
GP
1/0
CE
80
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16
8.2
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