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P9102 [Total No. of Pages : 2
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S.E. (Electronics / E & TC / Computer)
5s
DIGITAL CIRCUITS
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(2019 Pattern) (Semester-III) (204182)
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Time : 2½ Hours] 1/0 13 [Max. Marks : 70
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Instructions to the candidates:
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4) Use of Calculator is allowed.
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5) Assume suitable data, if necessary.
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Q1) a) Explain binary subtraction using l’s compliment and two’s compliment
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method with example. [6]
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b) Design and explain 3-bit parity generator circuit. [6]
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OR
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Q2) a) Design and explain 2-bit comparator circuit using logic gates. [6]
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CE
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Q3) a) Explain working of SR Flip flop with neat Block diagram and truth table.
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[6]
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c) Design and implement 2-bit synchronous counter using T flip flop. [5]
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OR
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Q4) a) Explain working of JK Flip flop with neat Block diagram and truth table.
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[6]
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Q5) a) Design the sequential circuit for the given state diagram using T flip flop.
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b) Design and implement circuit using D flip flop to detect the following
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Q6) a) Draw ASM chart for 2 bit binary counter having enable line E such that:
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E=1, Count Enable and E=0, Count Disable. [9]
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b) Write short note on state reduction with suitable example. [8]
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OR
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