CMOS Basics

A R Abhishek 23/07/2012

Outline - MOSFET
What is a MOSFET Why MOSFETs Why the name MOSFETs How does a MOSFET operate Symbols for different types of a MOSFET MOSFET curves Channel length modulation Early effect Body effect

Outline - CMOS
What is CMOS Why CMOS Composition Duality Logic Cross section Power Efficiency Power Dissipation Static and Dynamic Latch up Sizing Inverter and its VTC Logic levels Noise Margins

What is a MOSFET ?
The metaloxidesemiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a transistor used for amplifying or switching electronic signals. It is a FOUR terminal device( Drain, Gate, Source and Bulk/Body).But generally Source and Bulk are shorted. Basic principle is to use the voltage between two terminals to control the current in the third terminal.

Why MOSFETs?
Compared to BJTs, MOSFETs can be quite small and their manufacturing process is relatively simple. Also, their operation requires comparatively lower power. Circuit designers have found ingenious ways to implement digital and analog functions utilizing MOSFETs exclusively.

Why the name MOSFET ? / Explain the structure of a MOSFET

Why the name MOSFET ? / Explain the structure of a MOSFET

How does a MOSFET operate?

MOSFET is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. With sufficient gate voltage, majority carriers from the body are driven away from the gate, forming an inversion layer at the interface between body and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between source and drain. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain.

What are the symbols used for MOSFETs ?

MOSFET Curves
There are two curves the can be drawn(1) ID-VDS (2) ID-VGS ID-VDS is the most common curve drawn.

Output curve(ID-VDS)
0 A A B

Beyond B

IDS VDS curve

What is channel-length modulation ?

The linear dependence of iD on vDS (while operating in saturation) is represented by the factor (1 + vDS), where is a device parameter factor (units of Volts inverse).

IDS VGS curve

The transconductance(gm) parameter can be derived from the slope of this plot. gm is transfer function of output current to input voltage.

Body Effect
The body effect describes the changes in the threshold voltage by the change in VSB, the source-bulk voltage. Since the body influences the threshold voltage (when it is not tied to the source), it can be thought of as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".

A simple IC layout of a MOSFET

CMOS

What is CMOS?
Complementary metaloxide semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors , microcontrollers ,static RAM ,other digital logic circuits and several analog circuits such as image sensors data converters , and highly integrated transceivers for many types of communications. CMOS was patented by Frank Wanlass in 1967 (US patent 3,356,858).

Why CMOS? / Characteristics of CMOS

Two important characteristics of CMOS devices are high noise immunity and low static power consumption(with resistive loads). Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.

Composition
The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal-oxide-semiconductor field effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. (Pull Up Network - PUN) The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential. (Pull Down Network - PDN)

Composition
The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.

Duality
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgans laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Logic
If there is a parallel combination in the PUN, then by duality PDN must have its transistors connected serially.

Cross section of two transistors in a CMOS gate, in an N-well CMOS process

Power Efficiency
Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Power Dissipation
Power dissipation in CMOS circuits occur because of two components :

Static Dissipation a) Sub threshold condition when the transistors are off. b) Tunnelling current through gate oxide. c) Leakage current through reverse biased diodes.
Dynamic Dissipation a) Charging and discharging of load capacitances. b) Short circuit power dissipation.

Dynamic Dissipation Charging and discharging of load capacitances.

In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance to ground during discharge. Therefore in one complete charge/discharge cycle the characteristic switching power dissipated by a CMOS device: p=CV2f Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written as P=CV2f

Dynamic Dissipation Short Circuit power Dissipation

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD to ground, hence creating a short circuit current. Short circuit power dissipation increases with rise and fall time of the transistors.

Improve characteristics
To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi Threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low Vth transistors are used in speed sensitive paths.

What is Latch Up?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) .

In CMOS technology(digital design), why do we design the size of pmos to be higher than the nmos?
In PMOS the carriers are holes whose mobility is less[ aprrox. half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground and PMOS helps in pulling up the output to VDD.

In CMOS technology(digital design), why do we design the size of pmos to be higher than the nmos?
If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node.

Inverter VTC

Inverter VTC
Starting at point (1), where the input voltage is equal to 0 V,the output voltage is equal to VDD As input voltage is increased point (2),the nchannel transistor operates in its constant current region while the p channel is in the triode region At point (3),both n- and p- channel transistors are in their constant current region.(high gain region of inverter) Increasing the voltage to point (4) puts the n channel transistor in the triode region and p channel in its constant current region. Finally at point (5) p channel is cutoff and the nchannel has 0V corresponding to an output voltage equal to 0V.

Inverter VTC

Logic Levels
VIL (voltage input low) lower input voltage where the slope of the transfer characteristic is equal to -1. VIH(voltage input high) higher input voltage where the slope is equal to -1. VOH() output voltage given an input voltage of VIL. VOL() output voltage give an input voltage of VIH. VM(voltage midpoint) input voltage at which the inverter yields an output voltage equal to the input voltage.

Logic Levels

Noise Margins
Noise Margin high(NMH) margin defined which ensures that a logic 1 output from the first inverter is interpreted as a logic 1 input to the second inverter. NMH = VOH -VIH Noise Margin low(NML) - margin defined which ensures that a logic 0 output from the first inverter is interpreted as a logic 0 input to the second inverter. NML = VIL - VOL

Further

Reading

http://tams-www.informatik.unihamburg.de/applets/cmos/ http://www.prenhall.com/howe3/microelectroni cs/pdf_folder/lectures/tth/lecture11.fm5.pdf http://www.vlsiinterviewquestion.com/category /cmos-theory/page/2/