BECE303L VLSI System Design

Dr. Sandeep Moparthi

Assistant Professor
School of Electronics Engineering
Cabin : CBMR block -102F

CMOS VLSI Design 4th Ed.

Module-5
CMOS
Logic
Families
Module 5: CMOS Logic Families
Pass Transistor Logic, Transmission Gates based Logic Design, pseudo NMOS,
Cascode Voltage Switch Logic Dynamic and domino logic, clocked CMOS
(C2MOS) logic and np –CMOS logic.
Text Books:
•Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System
Perspective, 2015, 4th Edition, Pearson Education, Noida, India.
Reference Books:
 Digital IC Design, Prof. Janakiraman Viraraghavan, NPTEL, IIT MADRAS
https://www.youtube.com/watch?v=u7lZPCFzKPs
 Design and Analysis of VLSI Subsystems, Prof. Madhav Rao, NPTEL, IIIT
BANGALORE
https://www.youtube.com/watch?v=wfTNMMi8-kQ&list=PL5PDqJ5saHRIrtX-
rhGiAZzNrjX1MiU3q&index=46
Course Objective:
Describe the fundamental principles underlying digital design using CMOS logic and
analyze the performance characteristics of these digital circuits.
Course Outcome: 2

CO4: Analyse the various logic families and efficient techniques at circuit level for
improving power and speed of combinational
CMOS VLSIand sequential
Design 4th Ed. logic.
 Pass-Transistor Logic
 The advantages of pass-transistor logic are the simple design, the
reuse of already available signals, and the low contribution to static
power.
 Unfortunately, a NMOS device is effective at passing a 0 but is poor
at pulling a node to VDD. (Vice Vera for PMOS)
 In pass transistor logic, the pass transistors are used to pass the input
to output based on gate control.
 Therefore, when the NMOS based pass transistor pulls a node high,
the output only charges up to VDD -VTn.
 In fact, the situation is worsened in big circuits where with increase
in number of pass transistors logic high will reduce.
 It will limit the number of additional stages and will also reduce the
logic swing and noise margins

CMOS VLSI Design 4th Ed.

 Pass-Transistor Logic

VGS= Vt
VG – VS = Vt
VSmax = VG-Vt
VD = min (VSmax , VG-Vt )

CMOS VLSI Design 4th Ed.

Pass-Transistor: Example Problem 1
 Find out voltage at P,Q and R Vtn = 1V

P = 4V
Q= 3V
R= 2V

VGS= Vt
VG – VS = Vt
VSmax = VG-Vt
VD = min (VSmax , VG-Vt )

CMOS VLSI Design 4th Ed.

Pass-Transistor: Example Problem 2

Vtn = 1V

CMOS VLSI Design 4th Ed.

Pass-Transistor: Example Problem 3
Vtn = 1V

CMOS VLSI Design 4th Ed.

 Pass-Transistor Logic
 A popular and widely used alternative to complementary CMOS is pass
transistor logic.
 Pass transistor logic attempts to reduce the number of transistors required to
implement logic by allowing the primary inputs to drive gate terminals as
well as source/drain terminals.
 Pass transistor logic uses fewer devices and therefore has lower physical
capacitance.
 Pass transistor circuits can be designed using either NMOS or PMOS.

AND Gate
CMOS VLSI Design 4th Ed.
Pass-Transistor - Logic Gates

CMOS VLSI Design 4th Ed.

Pass-Transistor Logic - Multiplexer (MUX)
2:1 MUX
S Z

0 A

1 B

4:1 MUX

CMOS VLSI Design 4th Ed.

Pass-Transistor Logic - Multiplexer (MUX)
Problem – Self test
Can you design 8:1 and 16:1 multiplexers using pass
transistor logic ? Try with NMOS as well as PMOS
designs.

Pass transistor circuits can be designed using either

NMOS or PMOS.

CMOS VLSI Design 4th Ed.

 Transmission Gate Logic
 The most widely used solution to deal with the voltage drops induced by pass
transistors is the use of transmission gates.
 The primary limitation of NMOS or PMOS only pass gate is the threshold drop
(NMOS pass device pass a strong 0 while passing a weak 1 and PMOS pass
devices pass a strong 1 while passing a weak 0).
 The ideal approach is to use the NMOS device to pull-down and the PMOS device
to pull-up.
 The transmission gate combines the best of both device flavors by placing a NMOS
device in parallel with a PMOS device.

AND gate

CMOS VLSI Design 4th Ed.

 Transmission Gate MUX
2:1 MUX 4:1 MUX

S Z
S1 S0 O/P

0 B 0 0 D
0 1 B
1 A 1 0 C

CMOS VLSI Design 4th Ed. 1 1 A

 Drawback of CMOS Design – Advantages of
Psudo-NMOS logic
 The CMOS logic style described in the previous
section is highly robust and scalabe with
technology, but requires 2N transistors to
implement a N-input logic gate.
 The purpose of the PUN in complementary CMOS is
to provide a conditional path between VDD and the
output when the PDN is turned off.
 With the increase in number of inputs the series and
parallel combination of transistors will increase.
 Due to this, the size of PUN will become very large
which in turn results in higher input capacitance
and hence higher logical effort.
 In ratioed logic or pseudo NMOS, the entire PUN is
replaced with a single load device that pulls up the Pseudo NMOS
output when the PDN is turned off. Design
 In this logic, a grounded PMOS load is used instead of
a combination of active PDN and PUN.
CMOS VLSI Design 4th Ed.
 Pseudo-NMOS
• The nominal high output voltage
(VOH) for this gate is VDD since the
pull-down devices are turned off
when the output is pulled high.
• On the other hand, the nominal low
output voltage (VOL) is not 0 V
since there is a fight between the
devices in the PDN and the
grounded PMOS load device.
• This results in reduced noise
margins and more importantly
static power dissipation.

CMOS VLSI Design 4th Ed.

 Pseudo-NMOS
• In order to make VOL as small as possible, the PMOS device
should be sized much smaller than the NMOS pull-down
devices.
• Unfortunately, this has a negative impact on the
propagation delay for charging up the output node since
the current provided by the PMOS device is limited.

CMOS VLSI Design 4th Ed.

 Pseudo-NMOS

• To make the psudo NMOS logic to work, the α

should be <1 (that is, size of PMOS < size of
NMOS)
• Lets define/design a psudo NMOS unit
inverter. This can be used as a reference for
sizing the other psudo NMOS gates.

CMOS VLSI Design

Let Wp/Wn=α and Wn=β
4th Ed.

Then, Wp=α β
 Pseudo-NMOS – Sizing of unit inverter

Let Wp/Wn=α and Wn=β

Then, Wp=α β

Since, I is
considered as
the current in = αβ
unit NMOS
FET, PMOS =β
current is half If
of it, that is I/2 Ip=β
due to its poor Unit psudo
mobility.
CMOS VLSI Design 4th Ed.
NMOS inverter
 Pseudo-NMOS – Sizing of unit inverter

In = βI = 4I/3 Ip = αβ(I/2) = I/3

• For the considered α and widths, the nMOS transistor

produce I/3 and the pMOS transistor produce I/3 current.
• The load current (IL) is estimated as the pull-down current
minus the pull-up current.

• The pMOS transistor widths are selected to be about 1/4 the

strength (i.e., 1/2 the effective width) of the nMOS pull-
down network as a compromise between noise margin and
speed;
• This best size is process-dependent, but is usually in the
range of 1/3 to 1/6.
CMOS VLSI Design 4th Ed.
 Pseudo-NMOS unit inverter :
Logical effort (g)
• The logical effort of a psudo-NMOS gate for each transition
is computed as the ratio of the input capacitance of the psudo-
NMOS gate to that of a complementary CMOS inverter with
equal current for that transition.
Pull-up logical effort Pull-down logical effort
IL=In-Ip= I

gpd= 4/9

CMOS VLSI Design 4th Ed.

 Pseudo-NMOS unit inverter :
Parasitic delay (p)
• The parasitic delay of a psudo-NMOS gate for each transition
is computed as the ratio of the input capacitance of the psudo-
NMOS gate to that of a complementary CMOS inverter with
equal current for that transition.
Pull-up parasitic delay Pull-down parasitic delay

Cout= (2/3)+(4/3) =2 Cout= (2/3)+(1/3) =1 Cout= (2/3)+(4/3) =2 Cout= 2+1 =3

Ppu= 2/1 =2 Ppd= 2/3
CMOS VLSI Design 4th Ed.
 Pseudo-NMOS NAND & NOR gates

Unit psudo psudo NMOS psudo NMOS

NMOS inverter NAND2 NOR2

CMOS VLSI Design 4th Ed.

 Pseudo-NMOS : Summary
 The clear advantage of pseudo-NMOS is the reduced number of transistors
N+1 vs. 2N for complementary CMOS).
 Ratioed circuits (In which, pull-up is made with one PMOS which is
always ON) reduce the input capacitance by replacing the pMOS transistors
connected to the inputs with a single resistive pullup.
 But on the cost of reduced noise margins and more importantly
increased static power dissipation.
 The static power dissipation of pseudo-NMOS has limited its use.
 However, pseudo-NMOS still finds use in large fan-in circuits.
 When area is most important, such an approach is attractive.

CMOS VLSI Design 4th Ed.

 Cascode voltage switch logic (CVSL)
 Seeks the performance of pseudo-nMOS without the
static power consumption.
 It uses both true and complementary input signals and
computes both true and complementary outputs using a pair
of nMOS pulldown networks, as shown in Figure.

CMOS VLSI Design 4th Ed.

 Cascode voltage switch logic (CVSL)
 The pulldown network f implements the logic function as in
a static CMOS gate, while f’ uses inverted inputs feeding
transistors arranged in the conduction complement.
 For any given input pattern, one of the pulldown networks
will be ON and the other OFF.
 The pulldown network that is ON will pull that output low.
This low output turns ON the pMOS transistor to pull the
opposite output high.
 When the opposite output rises, the other pMOS transistor
turns OFF so no static power dissipation occurs.
 CVSL disadvantage:
– Require input complement. 4th Ed.
CMOS VLSI Design
 Cascode voltage switch logic ::
2-input NAND gate
The pulldown network f implements the logic function as in a
static CMOS gate, while f’ uses inverted inputs feeding
transistors arranged in the conduction complement.

AND NAND

Symbol of CVSL NAND

Advantage of CVSL: No short Disadvantage of CVSL:

4th Ed.
CMOS VLSI Design
circuit between VDD and GND. Require input complement also.
 Cascode voltage switch logic ::
2-input XOR gate

The pulldown
network f implements
A’B’+AB A’B+AB’
the logic function as Q XNOR XOR Q
in a static CMOS
gate, while f’ uses
inverted inputs
feeding transistors
arranged in the
conduction
complement.

CMOS VLSI Design 4th Ed.

 Dynamic logic

Drawbacks of ratioed logic (In which, pull-up is made with one PMOS
which is always ON):

 The drawbacks of ratioed circuits include slow rising

transitions, contention on the falling transitions, static power
dissipation, and a nonzero VOL.
 These are due to the pull-up which is ALWAYS ON.

CMOS VLSI Design 4th Ed.

 Dynamic logic
Dynamic circuits circumvent these drawbacks by using a clocked
pullup transistor rather than a pMOS that is always ON.

Footed dynamic inverter Un-Footed dynamic logic gate

CMOS VLSI Design 4th Ed.

 Dynamic logic
Dynamic circuit operation is divided into two modes.
During precharge, the clock K is 0, so the clocked pMOS is ON
and initializes the output Y high.
During evaluation, the clock is 1 and the clocked pMOS turns
OFF. The output may remain high or may be discharged low
through the pulldown network.

CMOS VLSI Design 4th Ed.

 Dynamic logic : Gates (un-footed)

Dynamic logic Dynamic Dynamic NOR2

inverter NAND2

CMOS VLSI Design 4th Ed.

 Dynamic logic : monotonicity problem
 A fundamental difficulty with dynamic circuits is the monotonicity
requirement. While a dynamic gate is in evaluation, the inputs must be
monotonically rising. That is, the input can start LOW and remain LOW,
start LOW and rise HIGH, start HIGH and remain HIGH, but not start
HIGH and fall LOW.
 Figure shows waveforms for a footed dynamic inverter in which the input
violates monotonicity.
 The input falls low during evaluation phase, turning off the pulldown
network. However, the precharge transistor is also OFF so the output
floats, staying LOW rather than rising as it would in a normal inverter.
The output will remain low until the next precharge step.

CMOS VLSI Design 4th Ed.

 Cascading in Dynamic logic gates :
monotonicity problem

Dynamic logic Dynamic logic

inverter-1 inverter-2
CMOS VLSI Design 4th Ed.
 Domino logic
 As discussed in Dynamic logic, it suffers from monotonicity problem in
which, a high to low transition of input signal during evaluation phase
results in wrong output.
 This problem can be eliminated by inverting/complementing the high to
low transition of input signal to low to high by placing an inverter at the
each stage of dynamic logic.
 This results in domino logic which is nothing but a combination of
dynamic logic and static CMOS inverter.

CMOS VLSI Design 4th Ed.

 Domino logic
Domino AND

Dynamic gate Static CMOS Inverter

CMOS VLSI Design 4th Ed.
 Domino logic : AND gate
Domino AND
 In Domino logic, the output is
non inverted if the function is
inverted. (as shown in the
schematic)

 In psudo-NMOS, Dynamic, &

Domino logics, Logic of the
given function is implemented
with NMOS (Pull-down) only;
which is same as the pull-down
stage of CMOS logic.

Dynamic NAND Static Inverter

CMOS VLSI Design 4th Ed.
 np-CMOS logic (Zipper CMOS)
 In domino logic, static CMOS inverter is placed at each stage of output
path to overcome the monotonicity of dynamic gate. This will increase the
propagation delay in domino logic gates.
 Moreover, using only NMOS (pull-down stage) in domino logic wont
give good logic-1.
 Hence, in np-CMOS logic, complementary stage (PMOS or pull-up) is
used after each NMOS stage to avoid inverter & for good logic-1.

CMOS VLSI Design 4th Ed.

 np-CMOS logic (Zipper CMOS)
 In np-CMOS logic, total number of inputs (for a given function) are
shared among n-stage and p-stage as shown in the figure.

CMOS VLSI Design 4th Ed.

 clocked CMOS (C2MOS)
Clocked CMOS (C2MOS) circuits offer Tri-state (high
impedance state) output if clock is ‘1’. If clock is ‘0’, the
C2MOS works as static-CMOS circuits. An inverter is shown as
an example.

C2MOS inverter C2MOS inverter

schematic 4th Ed.
symbol
CMOS VLSI Design
BECE303L VLSI System Design

Dr. Sandeep Moparthi

Assistant Professor
School of Electronics Engineering
Cabin : CBMR block -102F

1
Module-6
Timing Analysis
Module 6: Timing Analysis
Introduction to Static timing analysis, Setup Time, Hold Time, calculation of critical
path, slack, setup and hold time violations
Text Books:
•Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System Perspective,
2015, 4th Edition, Pearson Education, Noida, India.
•Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits: Analysis
and Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.
Reference Books:
 Design and Analysis of VLSI Subsystems, Prof. Madhav Rao, NPTEL, IIIT BANGALORE
https://www.youtube.com/watch?v=l5a9OuyU7U8&list=PL5PDqJ5saHRIrtX-
rhGiAZzNrjX1MiU3q&index=71
 Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective Paperback, 2016, 2rd Edition, Pearson Education, India.

Course Objective:
Verify that a design meets its functionality, timing constraints, both manually and
through the use of computer-aided design tools.
Course Outcome: 2

CO5: Implement the CMOS digital circuits with the specified timing constraints.
 Set-up time & Hold time Definitions
Setup time is the minimum amount of time for which the input data must be
held stable or steady before the occurrence of the clock cycle event.

Hold time is the minimum amount of time required for the data from
previous stage (which is processed in previous clock cycle) should be held
steady at next stage (for capturing) after the occurrence of the present clock
cycle.
 Clock skew & Clock Jitter Definitions
Clock skew (sometimes called timing skew) is a phenomenon in
synchronous digital circuit systems in which the same sourced clock signal
arrives at different components at different times.

Clock Jitter: Sometimes some external sources like noise, voltage variations
may cause to disrupt the natural periodicity or frequency of the clock. This
deviation from the natural location of the clock is termed to be clock jitter.

Clock Uncertainty = Clock Jitter + Clock Skew

 Timing Constraints of a Flip-flop

Data set-up time violation due to clock skew/jitter

Maximum delay violations are a result of a slow data path, including

the registers, causing the data to change after the tsetup has passed;
therefore it is often called the “Setup” path.
 Timing Constraints of a Flip-flop

Data hold time violation due to clock skew/jitter

Minimum delay violations are a result of a short data path, causing the
data to change before the thold has passed; therefore it is often called the
“Hold” path.
 Static Timing Analysis (STA) : Scenario
of set-up and hold time violations in a
synchronous circuit
Set-up time violation scenario:
Case I: If Clock is coming early (which doesn’t allow the data to be
stabilized before the arrival of clock as per the set-up time requirement).
and/or
Case II: If Data is delayed (which doesn’t have sufficient time for
stabilization before the arrival of clock as per the set-up time requirement).

Conclusion: To avoid set-up time violation, Clock should meet

minimum/sufficient clock path delay required (should not come too
early) and data should not come too late (should not exceed
maximum/acceptable data path delay)
 Static Timing Analysis (STA) : Scenario
of set-up and hold time violations in a
synchronous circuit
Hold time violation scenario:
Case I: At later stage of circuit, If present Clock is too much delayed at next
stage (than, new data from first stage my reach the next stage & overwrite the
old data which doesn’t allow the next stage to capture the old data).
Note: Old data is the data which is processed by first stage in previous cycle
which will be captured by next stage in present cycle.
and/or
Case II: If the new data from first stage is reaching the next stage earlier than
the clock (it means, the previous data is not maintained stable for sufficient
time at next stage after the arrival of present clock as per the hold time
requirement).

Conclusion: To avoid hold time violation, Clock should not come too late
(should not exceed maximum/acceptable clock path delay) and data should
meet minimum/sufficient data path delay required (data from first
stage/new data should not come too early at next stage)
 Static Timing Analysis (STA)

Time period of clock

Static Timing Analysis (STA)
 Static Timing Analysis (STA) : What could be the
maximum operating frequency of a sequential circuit?
Clock

Maximum operable frequency or minimum clock time can be calculated

from set-up time equation.

Time period of clock

Margin = 0 (not considered here), No clock skew (clock path delay), delay of
feedback path is considered as 0.
Hence, for the above circuit,
 Static Timing Analysis (STA) : Problem 1
Verify the set-up and hold violations for below circuit.
Hint: This clock
path delay needs
to be accounted
in data path
delay since the
data is getting
delayed due to
this.

Setup slack = Min. Clock Path Delay - Max. Data Arrival Time
Margin=0 (not considered here)
= (15 ns + 2ns + 5 ns + 2 ns) - ( 2 ns + 11 ns +2 ns + 9 ns + 2 ns + 4 ns)
= 24 ns – 30 ns = -6 ns : Setup Time Violation exist.
Hold time slack = Min. Data Arrival Time - Max. Clock Path Delay
Margin=0 (not considered here)
= (1 ns + 9 ns + 1 ns + 6 ns + 1 ns) - (2 ns + 3 ns + 9ns + 3 ns)
= 18 ns – 17 ns = + 1ns : No Hold Time Violation.
 Static Timing Analysis (STA) : Problem 2

Solution:
Given: tSU = 6ns, thold = 2ns, tCQ = 10ns
Draw the logic diagram for frequency divider.
Find out maximum operable frequency (minimum time of clock required).
Check for hold time violation if any.
 Static Timing Analysis (STA) : Problem 2

Solution:

Maximum operable frequency or minimum clock time can be calculated from

set-up time equation.
tSU + tCQ + tlogic Margin = 0 (not considered here),
No clock skew (clock path delay).
tlogic (delay of feedback path) is considered as 0.

tCQ + tlogic
 Static Timing Analysis (STA) : Problem 3
Consider the below flip flop pair logic diagram and the table with three
different flip flops FF1, FF2, and FF3 with their timing specifications.

Which combination of flip flops from the table should be replaced in the
flip-flop pair of circuit to get the maximum clock frequency of operation.
Solution: Tmin can be obtained from the equation of set-up time (given
below). Here, clock path delay (skew) is zero by ignoring wire delay. tlogic is
zero since there is no combinational circuit in between. Wire delay is ignored.
Hint: Replace the first flop place with the flip flop which has the minimum
clock to Q (tCQ) delay and replace the second flop place with the flip flop
having the minimum setup time (tSU) among all of them.
So FF1 and FF3 flip flop pair can be used in the logic circuit to have the
maximum frequency of operation.
 Static Timing Analysis (STA) : Problem 4
Consider the below logic circuit with delays dly1=2ns, dly2=0.5ns, and
dly3=3ns at different places shown and determine the constraints to avoid
setup time and hold violation. Also for the given timing specifications
calculate the maximum clock frequency of operation or minimum required
clock time period. tclock_Q1 = tclock_Q2 = 2.5ns; tsetup_time1 = tsetup_time2 = 2ns;
thold_time1 = thold_time2 = 1ns.
dly
This clock path delay 1
needs to be accounted
in data path delay since
the data is getting dly
delayed due to this. 2
dly
3
Solution:
Tmin or fmax can be obtained from the equation of set-up time
Margin=0 (not considered here)
(Tmin+ 3ns) ≥ ( 0.5 ns + 2.5 ns + 2 ns +2 ns+0)
Tmin ≥ 4 ns. (fmax = 1/Tmin)
If Tmin is satisfied in setup time equation, there wont be any set-up time violation.
 Static Timing Analysis (STA) : Problem 4
Consider the below logic circuit with delays dly1=2ns, dly2=0.5ns, and
dly3=3ns at different places shown and determine the constraints to avoid
setup time and hold violation. Also for the given timing specifications
calculate the maximum clock frequency of operation or minimum required
clock time period. tclock_Q1 = tclock_Q2 = 2.5ns; tsetup_time1 = tsetup_time2 = 2ns;
thold_time1 = thold_time2 = 1ns.
dly
This clock path delay 1
needs to be accounted
in data path delay since
the data is getting dly
delayed due to this. 2
dly
3

Solution:
Hold time slack:
Margin=0 (not considered here)

= (0.5 ns + 2.5 ns + 2 ns -0) ≥ (1 ns + 3ns)

= 5 ns ≥ 4 ns = + 1ns : No Hold Time Violation.
BECE303L VLSI System Design

Dr. Sandeep Moparthi

Assistant Professor
School of Electronics Engineering
Cabin : CBMR block -102F

1
Module-7
Semiconductor
Memory Design
Module 7: Semiconductor Memory Design
Introduction, Types - Read-Only Memory (ROM) Circuits, Static Read-Write
Memory (SRAM) and Dynamic Read-Write Memory (DRAM) Circuits.
Text Books:
•Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System Perspective,
2015, 4th Edition, Pearson Education, Noida, India.
•Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits: Analysis
and Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.
Reference Books:
 Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective Paperback, 2016, 2rd Edition, Pearson Education, India.

Course Objective:
Verify that a design meets its functionality, timing constraints, both manually
and through the use of computer-aided design tools.
Course Outcome:
CO6: Design memories with efficient architectures to improve access times,
power consumption. 2
Categories of memory arrays
 Static RAM (SRAM)
• A SRAM cell needs to be able to read and write data and to hold the data as
long as the power is applied.
• An ordinary flip-flop could accomplish this requirement, but the size is
quite large.
• Figure shows a standard 6-transistor (6T) SRAM cell that can be an order
of magnitude smaller than a flip-flop.
• The 6T cell achieves its compactness at the expense of more complex
peripheral circuitry for
reading and writing
the cells.
• The 6T SRAM cell
contains a pair of weak
cross-coupled inverters
holding the state and a
pair of access transistors
to read or write the state.

6T SRAM cell
 Static RAM (SRAM) : Read operation
• It is read by pre-charging the two bitlines high, then allowing them to float.
When wordline (Word) is raised, bit or bit_b pulls down, indicating the data value.

• Assume Q is initially 0 and thus Q_b is

initially 1.
• When the wordline is raised, bit should be
pulled down through driver and access
transistors D1 and A1.
• At the same time bit is being pulled down,
node Q is held low by D1, but tend to raise
by current flowing in from A1.
• Hence, the driver D1 must be stronger
than the access transistor A1 to pull
down the node Q.
• Specifically, the transistors must be sized
such that node Q remains below the
switching threshold of the P2/D2 inverter.
This constraint is called read stability.
 Static RAM (SRAM) : Write operation
• The cell is written by driving the desired value and its complement onto the
bitlines that is bit and bit_b respectively, then raising the wordline (word).

• Assume Q is initially 0 and that we wish

to write a 1 into the cell.
• bit is pre-charged high; bit_b is pulled
low by a write driver.
• We know on account of the read stability
constraint that bit will be unable to force Q
high through A1.
• Hence, the cell must be written by forcing
Q_b low through A2. P2 opposes this
operation;
• thus, P 2 must be weaker than A 2 so
that Q_b can be pulled low enough. This
constraint is called writability.
• Once Q_b falls low, D1 turns OFF and P1
turns ON, pulling Q high as desired.
 Static RAM (SRAM) : Hold margin
• Below figure shows the hold margin i.e., the static noise margin (SNM) while
the cell is holding its state and being neither read nor written.

• This figure is called butter fly diagram which

is generated by plotting V2 against V1 (curve I)
and V1 against V2 (curve II). Where, V1 and
V2 are the input voltages of cross-coupled
inverters.
• A positive value of noise (if any) shifts curve I
left and curve II up which reduce/degrade the
noise margin (SNM).

Butter fly diagram of SRAM

cell for showing hold/static-
noise margin (SNM)

6T SRAM cell
 Static RAM (SRAM) : Advantages-Disadvantages

It has the following advantages:

• Denser than flip-flops
• Compatible with standard CMOS processes
• Faster than DRAM (Dynamic RAM)
• Easier to use than DRAM since it doesn’t require any data refresh.

It has the following disadvantages/ limitations:

• SRAM cells require clever layout to achieve good density.
• It requires additional driver circuitry for row and columns.
 Dynamic RAM (DRAM)
• Dynamic RAMs (DRAMs) store their contents as charge on a capacitor
rather than in a feedback loop.
• Thus, the basic cell is substantially smaller than SRAM, but the cell must
be periodically read and refreshed so that its contents do not leak away.
• DRAM offer a factor of 10–20 greater density (bits/cm2) than high-
performance SRAM but they also have much higher latency (delay).

• A 1-transistor (1T) dynamic RAM

cell consists of a transistor and a capacitor,
as shown in Figure.
• Like SRAM, the DRAM cell is
accessed by asserting the wordline to
connect the capacitor to the bitline.

1T DRAM cell
 Dynamic RAM (DRAM) : Read & Write
• Like SRAM, the DRAM cell is accessed by asserting the wordline to
connect the capacitor to the bitline.
• On a read, the bitline is first precharged to VDD/2.
• When the wordline rises, the capacitor shares its charge with the bitline,
causing a voltage change ∆V that can be sensed, as shown in Figure. The
read disturbs the cell contents at x, so the cell must be rewritten after each
read.
• On a write, the bitline is driven high or low and the voltage is forced onto
the capacitor.
• Some DRAMs drive the wordline to
VDD + Vt to avoid a degraded level
when writing a ‘1’.

1T DRAM cell read

operation
 Dynamic RAM (DRAM) : Read & Write
• The DRAM capacitor Ccell must be as physically small as possible to
achieve good density. However, the bitline is contacted to many DRAM
cells and has a relatively large capacitance Cbit. Therefore, the cell
capacitance is typically much smaller than the bitline capacitance.
• According to the charge-sharing equation, the voltage swing on the bitline
during readout is

• We see that a large cell capacitance is important to provide a reasonable

voltage swing. It also is necessary to retain the contents of the cell for an
acceptably long time and to minimize soft errors.
Dynamic RAM (DRAM) : Advantages-Disadvantages

It has the following advantage:

• Denser than SRAM

It has the following disadvantages/ limitations:

• SRAM cells require data refresh after every Read operation due to the
disturbance in the capacitance value.
• A perfect trade-off between cell capacitance (Ccell) and bitline capacitance
(Cbitline) need to maintain to obtain reasonable voltage swing (∆V).
 Difference between Static RAM and Dynamic RAM
SRAM DRAM
Transistors are used to store information in
Capacitors are used to store data in DRAM.
SRAM.
To store information for a longer time, the
Capacitors are not used hence no refreshing is
contents of the capacitor need to be refreshed
required.
periodically.
SRAM is faster compared to DRAM. DRAM provides slow access speeds.
These are expensive. These are cheaper.
SRAMs are low-density devices. DRAMs are high-density devices.
In this bits are stored in the form of electric
In this bits are stored in voltage form.
energy.
These are used in cache memories. These are used in main memories.
Consumes less power and generates less heat. Uses more power and generates more heat.
SRAMs has lower latency (response time) DRAM has more latency than SRAM
SRAMs are more resistant to radiation than DRAMs are less resistant to radiation than
DRAM SRAMs
SRAM has higher data transfer rate DRAM has lower data transfer rate
 Read Only Memory (ROM)
• Read-Only Memory (ROM) cells can be built with only one transistor per bit of
storage.
• A ROM is a nonvolatile memory structure in that the state is retained indefinitely
even without power.
• A ROM array is commonly implemented as a single-ended NOR array or NAND
array.
Figure shows a 4-word by 6-bit
ROM using pseudo-nMOS
pullups with the following
contents:
word0: 010101
word1: 011001
word2: 100101
word3: 101010

The contents of the ROM can

be symbolically represented
with a dot diagram in which
dots indicate the presence of
‘1’s Pseudo-nMOS ROM