Semiconductor Corporation

CS4215
16-Bit Multimedia Audio Codec
Features General Description
• Sample Frequencies from 4 kHz to 50 kHz The CS4215 is an MwaveTM

•
audio codec.
16-bit Linear, 8-bit Linear, µ-Law, or A-Law
Audio Data Coding The CS4215 is a single-chip, stereo, CMOS multime-
• Programmable Gain for Analog Inputs
dia codec that supports CD-quality music,
FM radio-quality music, telephone-quality speech, and
• Programmable Attenuation for Analog modems. The analog-to-digital and digital-to-analog
converters are 64×oversampled delta-sigma converters
Outputs
with on-chip filters which adapt to the sample fre-
• On-chip Oscillators quency selected.

• +5V Power Supply The +5V only power requirement makes the CS4215
ideal for use in workstations and personal computers.
• Microphone and Line Level Analog Inputs Integration of microphone and line level inputs, input
• Headphone, Speaker, and Line Outputs and output gain setting, along with headphone and
monitor speaker driver, results in a very small footprint.
• On-chip Anti-Aliasing/Smoothing Filters
• Serial Digital Interface
Ordering Information:
CS4215-KL 0°C to 70°C 44-pin PLCC
CS4215-KQ 0°C to 70°C 100-pin TQFP
CDB4215 Evaluation Board

CMOUT
LINL
A/D unsigned SDOUT
LINR M
µ-law SCLK
U Gain
MINL A-law
X FSYNC
A/D encode
MINR TSIN

SDIN Serial Input/Output TSOUT

CLKIN VREF
CLKOUT Voltage
Reference MOUT1
XTL1IN Clock Monitor
8 MOUT2
XTL1OUT Generator Attenuator
XTL2IN
unsigned + D/A LOUTR
XTL2OUT
µ-law LOUTL
Output
PIO0 Control HEADC
A-law Attenuator Mute
PIO1 Interface and HEADR
Registers decode + D/A
D/C HEADL
RESET
PDN

VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2

This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and
previous versions, see Appendix A.
Crystal Semiconductor Corporation SEPT ’93
P.O. Box 17847, Austin, TX 78760 Copyright  Crystal Semiconductor Corporation 1993 DS76F2
(All Rights Reserved)
(512) 445-7222 FAX: (512) 445-7581 1
 CS4215

ANALOG CHARACTERISTICS( TA = 25°C; VA1, VA2, VD1, VD2 = +5V;

Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2; Full Scale Input Sine wave, No Gain, No Attenuation 1 kHz;
Conversion Rate = 48 kHz; No Gain, No Attenuation, SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to
20 kHz; Slave mode; Unless otherwise specified.)
Parameter * Symbol Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution 16 - - Bits
ADC Differential Nonlinearity - - ±0.9 LSB
Instantaneous Dynamic Range Line Inputs IDR 80 84 - dB
Mic Inputs 72 78 - dB
Total Harmonic Distortion Line Inputs THD - - 0.012 %
Mic Inputs - - 0.032 %
Interchannel Isolation Line to Line Inputs - 80 - dB
Line to Mic Inputs - 60 - dB
Interchannel Gain Mismatch Line Inputs - - 0.5 dB
Mic Inputs - - 0.5 dB
Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB
Programmable Input Gain Line Inputs -0.2 - 23.5 dB
Mic Inputs 19.8 - 44 dB
Gain Step Size - 1.5 - dB
Absolute Gain Step Error - - 0.75 dB
Offset Error Line Inputs (AC Coupled) - ±150 ±400
with HPF = 0 Line Inputs (DC Coupled) - ±10 ±150 LSB
(No Gain) Mic Inputs - ±400 -
Offset Error Line Inputs (AC Coupled) - 0 ±5
with HPF = 1 (Notes 1,2) Line Inputs (DC Coupled) - 0 ±5 LSB
(No Gain) Mic Inputs - 0 ±5
Full Scale Input Voltage: (MLB=0) Mic Inputs 0.250 0.28 0.310 Vpp
(MLB=1) Mic Inputs 2.50 2.8 3.10 Vpp
Line Inputs 2.50 2.8 3.10 Vpp
Gain Drift - 100 - ppm/°C
Input Resistance (Note 3) 20 - - kΩ
Input Capacitance - - 15 pF
CMOUT Output Voltage (Note 4) 1.9 2.1 2.3 V
(Maximum output current = 400 µA)
Notes: 1. This specification is guaranteed by characterization, not production testing.
2. Very low frequency signals will be slightly distorted when using the HPF.
3. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input
resistance.
4. DC current only. If dynamic loading exists, then CMOUT must be buffered or the performance of
ADC’s and DAC’s may be degraded.
* Parameter definitions are given at the end of this data sheet.
Mwave is a trademark of the IBM Corporation.

2 Specifications are subject to change without notice. DS76F2

 CS4215

ANALOG CHARACTERISTICS (Continued)

Parameter * Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution 16 - - Bits
DAC Differential Nonlinearity - - ±0.9 LSB
Total Dynamic Range TDR - 95 - dB
Instantaneous Dynamic Range (OLB = 1) (All Outputs) IDR 80 85 - dB
Total Harmonic Distortion Line Out (Note 5) - - 0.025 %
(OLB = 1) Headphone Out (Note 6) THD - - 0.2 %
Speaker Out (Note 6) - - 0.32 %
Interchannel Isolation Line Out (Note 5) - 80 - dB
Headphone Out (Note 6) - 40 - dB
Interchannel Gain Mismatch Line Out - - 0.5 dB
Headphone - - 0.5 dB
Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB
Programmable Attenuation (All Outputs) 0.2 - -94.7 dB
Attenuation Step Size - 1.5 - dB
Absolute Attenuation Step Error - - 0.75 dB
Offset Voltage Line Out - 10 - mV
Full Scale Output Voltage Line Output (Note 5) 2.55 2.8 3.08 Vpp
with OLB = 0 Headphone Output (Note 6) 3.6 4.0 4.4 Vpp
Speaker Output-Differential (Note 6) 7.3 8.0 8.8 Vpp
Full Scale Output Voltage Line Output (Note 5) 1.8 2.0 2.2 Vpp
with OLB = 1 Headphone Output (Note 6) 1.8 2.0 2.2 Vpp
Speaker Output-Differential (Note 6) 3.6 4.0 4.4 Vpp
Gain Drift - 100 - ppm/°C
Deviation from Linear Phase - - 1 Degree
Out of Band Energy (22 kHz to 100 kHz) Line Out - -60 - dB
Power Supply
Power Supply Current (Note 7) Operating - 110 140 mA
Power Down - 0.5 2 mA
Power Supply Rejection (1 kHz) - 40 - dB
Notes: 5. 10 kΩ, 100 pF load. Headphone and Speaker outputs disabled.
6. 48 Ω, 100 pF load. For the headphone outputs, THD with 10kΩ, 100pF load is 0.02%.
7. Typically, 50% of the power supply current is supplied to the analog power pins (VA1, VA2)
and 50% is supplied to the digital power pins (VD1, VD2). Values given are for unloaded outputs.

DS76F2 3
 CS4215

A/D Decimation Filter Characteristics

Parameter Symbol Min Typ Max Units
Passband (Fs is conversion freq.) 0 - 0.45Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple - - ±0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ≥ 0.55Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - 16/Fs - s
Group Delay Variation vs. Frequency - - 0.0 µs

D/A Interpolation Filter Characteristics

Parameter Symbol Min Typ Max Units
Passband (Fs is conversion freq.) 0 - 0.45Fs Hz
Frequency Response -0.5 - +0.2 dB
Passband Ripple - - ±0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ≥ 0.55Fs - - Hz
Stop Band Rejection 74 - - dB
Group Delay - 16/Fs - s
Group Delay Variation vs. Frequency - - 0.1/Fs s

DIGITAL CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = 5V)

Parameter Symbol Min Max Units
High-level Input Voltage VIH (VD1,VD2)-1.0 (VD1,VD2)+0.3 V
Low-level Input Voltage VIL -0.3 1.0 V
High-level Output Voltage at I0 = -2.0 mA VOH (VD1,VD2)-0.2 - V
Low-level Output Voltage at I0 = 2.0 mA VOL - 0.1 V
Input Leakage Current (Digital Inputs) - 10 µA
Output Leakage Current (High-Z Digital Outputs) - 10 µA

4 DS76F2
 CS4215

SWITCHING CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = +5V,

outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Parameter Symbol Min Typ Max Units
SCLK period Master Mode, XCLK = 1 (Note 8) tsckw - 1/(Fs*bpf) - s
Slave Mode (XCLK = 0) tsckw 80 - - ns
SCLK high time Slave Mode, XCLK = 0 (Note 9) tsckh 25 - - ns
SCLK low time Slave Mode, XCLK = 0 (Note 9) tsckl 25 - - ns
Input Setup Time ts1 15 - - ns
Input Hold Time th1 10 - - ns
Input Transition Time 10% to 90% points - - 10 ns
Output delay tpd1 - - 28 ns
SCLK to TSOUT tpd2 - - 30 ns
Output to Hi-Z state Timeslot 8, bit 0 thz - - 12 ns
Output to non-Hi-Z Timeslot 1, bit 7 tnz 15 - - ns
Input Clock Frequency Crystals - - 27 MHz
CLKIN (Note 10) 1.024 - 13.5 MHz
Input Clock (CLKIN) low time 30 - - ns
Input Clock (CLKIN) high time 30 - - ns
Sample rate Fs 4 - 50 kHz
RESET low time (Note 11) 500 - - ns
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.
When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.
See Internal Clock Generation section.
9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec
(CLKIN, XTAL1, XTAL2).
10. Sample rate specifications must not be exceeded.
11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage
reference to settle.
t s1 t h1 t s1 t h1
FSYNC in
TSIN

t t
pd2 pd2
TSOUT

t t
FSYNC pd1 pd1
out

t sckh t sckl

SCLK
t
t s1
sckw t
h1

SDIN TS 1, Bit 7 TS 1, Bit 6 TS 8, Bit 0

t pd1
t
nz
SDOUT TS 1, Bit 7 TS 1, Bit 6 TS 8, Bit 0
t
pd1 t
hz
DS76F2 5
 CS4215

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Symbol Min Max Units
Power Supplies: Digital VD1,VD2 -0.3 6.0 V
Analog VA1,VA2 -0.3 6.0 V
Input Current (Except Supply Pins) - ±10.0 mA
Analog Input Voltage -0.3 (VA1, VA2)+0.3 V
Digital Input Voltage -0.3 (VD1, VD2)+0.3 V
Ambient Temperature (Power Applied) -55 +125 °C
Storage Temperature -65 +150 °C
Warning: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with re-
spect to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital (Note 8) VD1,VD2 4.75 5.0 5.25 V
Analog (Note 8) VA1,VA2 4.75 5.0 5.25 V
Operating Ambient Temperature TA 0 25 70 °C
Note: 8. VD - VA must be less than 0.5 Volts (one diode drop).

6 DS76F2
 CS4215

F errite B e ad
+ 5 V D ig ita l + 5V A n alog
S upply S u pp ly
+ +
0.1 u F 1 uF
1 uF 0.1 uF

3 8 24 23
0.4 7 uF
150 VD1 VD2 VA2 VA1
M icroph one 15 28
MINR M O U T1 > 3 2Ω
In pu t R ight 27
M O U T2
0 .01 u F
1 2Ω 1/2W H e a dph one
NPO 29
HEADR Jack
31
HEADL >48 Ω
30 1 2Ω 1/2W
0.47 uF HEADC
150 600 Ω
M icrophon e 17 33 +
MINL LOUTR
In put Le ft
0.00 22 u F 40 k
> 1.0 uF
0.01 u F NPO
NPO
600 Ω
32 +
LO UTL
0.00 22 u F 40 k
> 1.0 uF
19 C S4215 NPO
T o O ption al CMOUT
21
Input B uffers VR EF
+
0 .47 uF 0 .1 u F 10 uF

10 40pF
X T L2IN
16.934 4 M H z
16 11 40pF
LINR X T L2O U T
S e e Lin e Leve l
Inp uts S ection 6 40pF
18
LIN L X T L1IN
+5v
24.576 M H z
7 40pF
X T L1O U T 20 k

Refer to the Analog Inputs 1

section for terminating SDIN
unused line and mic inputs. 4
C L K IN
All other unused inputs
5
should be tied to GND. All NC CLKO UT
pins should be left floating. 12
RESET
13
PDN
44
SDOUT
41 C o ntroller
VD1 TSOUT
40
47 k TSIN
35
36 D /C
PIO0
43
37 S C LK
PIO1
42
FSYNC

AGND1 AG ND2 DG ND1 DGND2 20 k 20k

22 25 2 9

Note: AGND and DGND pins must be on the same ground plane.

Figure 1. Recommended Connection Diagram

DS76F2 7
 CS4215

FUNCTIONAL DESCRIPTION Unused analog inputs that are not selected have
a very high input impedance, so they may be
Overview tied to AGND directly. Unused analog inputs
that are selected should be tied to AGND
The CS4215 has two channels of 16-bit analog- through a 0.1uF capacitor. This prevents any DC
to-digital conversion and two channels of 16-bit current flow.
digital-to-analog conversion. Both the ADCs and
the DACs are delta-sigma converters. The ADC Line Level Inputs
inputs have adjustable input gain, while the DAC
outputs have adjustable output attenuation. Spe- LINL and LINR are the line level input pins.
cial features include a separate microphone input These pins are internally biased to the CMOUT
with a 20 dB programmable gain block, an op- voltage. Figure 2 shows a dual op-amp buffer
tional 8-bit µ-law or A-law encoder/decoder, pins which combines level shifting with a gain of 0.5
for two crystals to set alternative sample rates, to attenuate the standard line level of 2 Vrms to
direct headphone drive and mono speaker drive.
56 pF

Control for the functions available on the

0.47 uF
CS4215, as well as the audio data, are communi- Line In 20 k _
10 k
150 LINR
cated to the device over a serial interface. Right
+ (pin 16)
Separate pins for input and output data are pro- 0.01 uF
NPO
vided, allowing concurrent writing to and Example 5k
reading from the device. Data must be con- Op-Amps CMOUT
are (pin 19)
tinually written for proper operation. Multiple 0.47 uF 0.47 uF
LT1013
CS4215 devices may be attached to the same
data lines. 0.47 uF + 150 LINL
Line In 20 k _ (pin 18)
Left
10 k 0.01 uF
Analog Inputs
NPO

Figure 1, the recommended connection diagram, 56 pF

shows examples of the external analog circuitry
Op-amps are run
recommended around the CS4215. An internal from VA1, VA2 and
multiplexer selects between line level inputs and AGND.
microphone level inputs. Figure 2. DC Coupled Input.

Input filters using a 150 Ω resistor and a .01 µF

0.47 uF
NPO capacitor to ground are required to isolate Line In LINR
the input op-amps from, and provide a charge re- Right 150 (pin 16)
serve for, the switched-capacitor input of the 0.01 uF
codec. The RC values may be safely changed NPO

by a factor of two.
NPO
0.01 uF
The HPF bit in Control Time Slot 2 provides a 150
Line In LINL
high pass filter that will reduce DC offset on the Left (pin 18)
analog inputs. Using the high pass filter will 0.47 uF

cause slight distortions at very low frequencies. Figure 3. AC Coupled Input.

8 DS76F2
 CS4215

R6 R4

2.2 k 22.1 k
+ C4
10 uF C6 560 pF
VA+
NPO
C8
1 uF 2 8 C48 R56 Microphone
0.1 uF
Input Right
+ 3
1 (pin 15)
4 0.47 uF 150
MINR C5 U2 NPO
MC33078 or C47 0.01 uF
R5
50 k MC33178
CMOUT
+
R2 C7 1 uF
C2 50 k
MINL 5 C45 R57 Microphone
(Mono) 7
+ 6 Input Left
1 uF
A =20 dB 0.47 uF 150 (pin 17)
NPO
C1 560 pF
C46 0.01 uF
NPO

2.2 k 22.1 k

R3 R1
+
10 uF C3

Figure 4. Optional Microphone Input Buffer

1 Vrms. The CMOUT reference level is used to The 20 dB gain block may be disabled using the
level shift the signal. This level shifting allows MLB bit in Control Time Slot 1. When dis-
the line inputs to be DC coupled into the abled, the inputs become line level with full
CS4215. Minimum ADC offset results when the scale inputs of 1 Vrms.
line inputs are DC coupled (see Analog Charac-
teristics Table). Adjustable Input Gain

Figure 3 shows an AC coupled input circuit for The signals from the microphone or the line in-
signals centered around 0 Volts. The anti-alias- puts are routed to a programmable gain circuit
ing RC filter presents a low impedance at high which provides up to 22.5 dB of gain in 1.5 dB
frequencies and should be driven by a low im- steps. Level changes only take effect on zero
pedance source. crossings to minimize audible artifacts, often re-
ferred to as "zipper noise". The requested level
Microphone Level Inputs change is forced if no zero crossing is found af-
ter 511 frames (10.6 ms at a 48 kHz frame rate).
Internal amplifiers with a programmable 20 dB A separate zero crossing detector exists for each
gain block are provided for the microphone level channel.
inputs, MINR and MINL. Figure 4 shows a sin-
gle-ended input microphone pre-amplifier stage Analog Outputs
with a gain of 23 dB. AC coupling is mandatory
for these inputs since any DC offset on the input The analog outputs of the DACs are routed via
will be amplified by the codec. an attenuator to a pair of line outputs, a pair of

DS76F2 9
 CS4215

headphone outputs and a mono monitor speaker phone output lines are short-circuit protected.
output. These outputs may be muted.

Output Level Attenuator Speaker Output

The DAC outputs are routed through an attenu- MOUT1 and MOUT2 differentially drive a small
ator, which provides 0 dB to 94.5 dB of loudspeaker, whose impedance should be greater
attenuation, adjustable in 1.5 dB steps. Level than 32 Ω. The signal is a summed version of
changes are implemented using both analog and the right and left line output, tapped off prior to
digital attenuation techniques. Level changes the mute function, but after the attenuator. The
only take effect on zero crossings to minimize speaker output may be independently muted.
audible artifacts. The requested level change is With OLB = 0, the speaker output also contains
forced if an analog zero crossing does not occur a 3 dB gain over the line outputs. When
within 511 frames (10.6 ms at a 48 kHz frame OLB = 1, the speaker outputs are driven at the
rate). A separate zero crossing detector exists for same level as the line outputs.
each channel.
Some small speakers distort heavily when pre-
Line Outputs sented with low frequency energy. A high-pass
filter helps eliminate the low frequency energy
LOUTR and LOUTL output an analog signal, and can be implemented by AC coupling both
centered around the CMOUT voltage. The mini- speaker terminals with a resistor to ground, on
mum recommended load impedance is 8 kΩ. the speaker side of the DC blocking capacitors.
Figure 1 shows the recommended 1.0 µF DC The values selected would depend on the speaker
blocking capacitor with a 40 kΩ resistor to chosen, but typical values would be 22 µF for
ground. When driving impedances greater than the capacitors, with the positive side connected
10 kΩ, this provides a high pass corner of to the codec, and 50 kΩ resistors. This circuit is
20 Hz. These outputs may be muted. contained on the CDB4215 evaluation board as
shown in the end of this data sheet.
Headphone Outputs
Input Monitor Function
HEADR and HEADL output an analog signal,
centered around the HEADC voltage. The de- To allow monitoring of the input audio signal,
fault headphone output level (OLB = 0) contains the output of the ADCs can be routed through a
an optional 3 dB gain over the line outputs monitor path attenuator, then digitally mixed into
which provides reasonable listening levels, even the input data for the DACs (see the front page
with small amplitude digital sources. These out- block diagram). Changes in the input gain or
puts have increased current drive capability and output level settings directly affect the monitor
can drive a load impedance as low as 48 Ω. Ex- level. If full scale data from the ADCs is added
ternal 12 Ω series resistors reduce output level to full scale digital data from the serial interface,
variations with different impedance headphones. clipping will occur.
The common return line from driving head-
phones should be connected to HEADC, which Calibration
is biased to the CMOUT voltage. This removes
Both output offset voltage and input offset error
the need for AC coupling, and also controls
are minimized by an internal calibration cycle.
where the return currents flow. All three head-
At least one calibration cycle must be invoked
10 DS76F2
 CS4215

FSYNC

SCLK

CLKOUT

8.5 CLKOUT's

PIO Read
11 CLKOUT's

PIO Write
Data Mode -Read and Write

TSIN

SCLK

PIO Read
1 SCLK

Control Mode - Read Only

Notes: 1. DATA MODE READ - The data is sent out via SDOUT on the next frame.
2. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.
3. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.
They are independent of SCLK.
4. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.

Figure 5. PIO Pin Timing

after power up. A calibration cycle will occur calibration and will go low when calibration is
immediately after leaving the reset state. A cali- finished.
bration cycle will also occur immediately after
going from control mode to data mode (D/C go- Parallel Input/Output
ing high). When powering up the CS4215, or
exiting the power down state, a minimum of Two pins are provided for parallel input/output.
50 ms must occur, to allow the voltage reference These pins are open drain outputs and require
to settle, before initiating a calibration cycle. external pull-up resistors. Writing a zero turns on
This is achieved by holding RESET low or stay- the output transistor, pulling the pin to ground;
ing in control mode for 50 ms after power up or writing a one turns off the output transistor,
exiting power down mode. The input offset error which allows an external resistor to pull the pin
will be calibrated for whichever input channel is high. When used as an input, a one must be writ-
selected (microphone or line, using the IS bit). ten to the pin, thereby allowing an external
Therefore, the IS bit should remain steady while device to pull it low or leave it high. These pins
the codec is calibrating, although the other bits can be read in control mode and their state is
input to the codec are ignored. Calibration takes recorded in Control Register 5. These pins can
194 FSYNC cycles and SDOUT data bits will be be written to and read back in data mode using
zero during this period. The A/D Invalid bit, ADI Data Register 7. Figure 5 shows the Parallel In-
(bit 7 in data time slot 6), will be high during put/Output timing.

DS76F2 11
 CS4215

Clock Generation An internally generated clock which is 256 times

the sample rate (FSYNC rate) is output
The master clock operating the CS4215 may be (CLKOUT) for potential use with an external
generated using the on-chip crystal oscillators, or AES/EBU transmitter, or another CS4215. No
by using an external clock source. In all data glitch occurs on CLKOUT when selecting alter-
modes SCLK and FSYNC must be synchronous nate clock sources. CLKOUT will stop in a low
to the selected master clock. condition within two periods after D/C goes low,
assuming one of the crystal oscillators is se-
If the master clock source stops, the digital fil- lected, or either CLKIN or SCLK is the master
ters will power down after 5 µs to prevent clock source and is continuous. The duty cycle
overheating. If FSYNC stops, the digital filters of CLKOUT is 50% if the master clock is one of
will power down after approximately 1 FSYNC the crystal oscillators and the DFR bits are 0, 1,
period. The CS4215 will not enter the total 2, 6 or 7. If the DFR bits are 3 or 5, the duty
power down state. cycle is 33% (high time). If the DFR bits are 4
then CLKOUT has the timing shown in Figure 6.
Internal Clock Generation If the master clock is SCLK or CLKIN, the duty
cycle of CLKOUT will be the same as the mas-
Two external crystals may be attached to the ter clock source.
XTL1IN, XTL1OUT, XTL2IN and XTL2OUT
pins. Use of an external crystal requires addi-
tional 40 pF loading capacitors to digital ground 1 2 1 3 1 2 1 3
(see Figure 1). XTAL1 oscillator is intended for
use at 24.576 MHz and XTAL2 oscillator is in-
tended for use at 16.9344 MHz, although other
frequencies may be used. The gain of the inter- 1/(128 x FSYNC) 1/(128 x FSYNC)
nal inverter is slightly higher for XTAL1,
ensuring proper operation at >24 MHz frequen- Figure 6. CLKOUT duty cycle using the on-chip
cies. The crystals should be parallel resonant, crystal oscillator when DFR = 4
fundamental mode and designed for 20 pF load- ( typically FSYNC = 37.8 kHz)
ing (equivalent to a 40 pF capacitor on each leg).
If XTAL1 or XTAL2 is not selected as the mas- External Clock
ter clock, that particular crystal oscillator is
powered down to minimize interference. If a An external clock input pin (CLKIN) is provided
crystal is not needed, the XTL-IN pin should be for potential use with an external AES/EBU re-
grounded. An example crystal supplier is CAL ceiver, or an already existing system clock.
Crystal, telephone number (714) 991-1580. When MCK2 = 0, the input clock must be ex-
actly 256 times the sample rate, and FSYNC and
FSYNC and SCLK must be synchronous to the SCLK must be synchronous to CLKIN. When
master clock. When using the codec in slave MCK2 = 1 the DFR bits allow various divide
mode with one of the crystals as master clock, ratios off the CLKIN frequency.
the controller must derive FSYNC and SCLK
from the crystals, i.e. via CLKOUT. Note that Alternatively, an external high frequency clock
CLKOUT will stop in a low condition within may be driven into XTL1IN or XTL2IN. The
two periods after D/C goes low. correct clock source must be selected using the
MCK bits. Manipulating DFR bits will allow
various divide ratios from the clock to be se-

12 DS76F2
 CS4215

lected. SCLK and FSYNC must be synchronous or 256 bits per frame, thereby allowing for 1, 2
to the external clock. or 4 CS4215s connected to the same bus.

As a third alternative, SCLK may be pro- In a typical multi-part scenario, one CS4215 (the
grammed to be the master clock input. In this master) would generate FSYNC and SCLK,
case, it must be 256 times Fs. while the other CS4215s (the slaves) would re-
ceive FSYNC and SCLK. The CLKOUT of the
Serial Interface master would be connected to the CLKIN of
each slave device as shown in Figure 7. Then,
The serial interface of the CS4215 transfers digi- the master device would be programmed for the
tal audio data and control data into and out of desired sample frequency (assuming one of the
the device. Multiple CS4215 devices may share crystals is selected as the clock source), the num-
the same data lines. DSP’s supported include the ber of bits per frame, and for SCLK and FSYNC
Motorola 56001 in network mode and a subset to be outputs. The slave devices would be pro-
of the ‘CHI’ bus from AT&T/Intel. grammed to use CLKIN as the clock source, the
same number of bits per frame, and for SCLK
Serial Interface Signals and FSYNC to be inputs. Since CLKOUT is al-

Figure 7 shows an example of two CS4215 de-

vices connected to a common controller. The
CS4215
Serial Data Out (SDOUT) and Serial Data In SCLK
XTL1IN
SCLK
(SDIN) lines are time division multiplexed be- SDIN
SDIN XTL1OUT
tween the CS4215s. SDOUT
SDOUT
FSYNC A
Controller FSYNC
The serial interface clock, SCLK, is used for TSIN XTL2IN
transmitting and receiving data. SCLK can be TSOUT XTL2OUT
generated by one of the CS4215s, or it can be D/C
D/C
Master
input from an external SCLK source. When gen- PDN
CLKOUT
erated by an external source, SCLK must be RESET
synchronous to the master clock. Data is trans-
mitted on the rising edge of SCLK and is CS4215
SCLK
received on the falling edge of SCLK. The CLKIN
SDIN
SCLK frequency is always equal to the bit rate.
SDOUT

FSYNC
The Frame Synchronizing signal (FSYNC) is B
TSIN
used to indicate the start of a frame. It may be
TSOUT
output from one of the CS4215s, or it may be
D/C Slave
generated from an external controller. If FSYNC
PDN
is generated externally, it must be high for at
RESET
least 1 SCLK period, and it must fall at least
2 SCLKs before the start of a new frame (see
Figure 8). It must also be synchronous to the
master clock. The frequency of FSYNC is equal
to the system sample rate (see Figure 8). Each
CS4215 requires 64 SCLKs to transfer all the Figure 7. Multiple CS4215’s
data. The SCLK frequency can be set to 64, 128,

DS76F2 13
 CS4215

T1

FSYNC
TSINA

TSn TS8 TS1 TS2 TS3 TS8 TS1 TS2 TS7 TS8

DEVICE A DEVICE B
TSOUTA
TSINB

TSOUTB
T1 1/Frame Rate or 1/System Sample Rate
TSn Time slot numbers

Figure 8. Serial Interface Timing for 2 CS4215’s

1 2 8 9 10 16 17 18 64 65 66 67 68

SCLK

FSYNC
TSIN

DATA 0 7 6 1 0 7 6 1 0 7 6 1 0 7 6 5

TS1 TS2 TS3 TS8 TS1

TSOUT

Figure 9. Frame Sync and Bit Offset Timing

1 2 3 4 64 65 66 67 68 128 1 2 3 4 5 64 65 66
SCLK

FSYNC,
TSIN A

TSOUT A,
TSIN B

TSOUT B

SDIN Control to A Control to B Control to A

SDOUT Control from A Control from B

_
D/C Control Mode

Figure 10. Control Mode Timing for 2 CS4215’s

14 DS76F2
 CS4215

ways 256 times the sample frequency and scales timeout and release FSYNC and SCLK within
with the selected sample frequency on the mas- 100µs. The values in the control registers for
ter, the slave devices will automatically scale control of the serial ports are ignored in control
with changes in the master codec’s sample fre- mode. The data received on SDIN is stored into
quency. the control registers which have addresses
matching their time slots. The data in the regis-
CS4215s are time division multiplexed onto the ters is transmitted on SDOUT with the time slot
bus using the Time Slot Out (TSOUT) and Time equal to the register number (see Figure 10).
Slot In (TSIN) signals. TSOUT is an output sig-
nal that is high for one SCLK bit time, and The steps involved when going from data mode
indicates that the CS4215 is about to release the to control mode and back are shown in the flow
bus. TSIN is an input signal that informs the chart in Figure 11.
CS4215 that the next time slot is available for it
to use. The first device in the chain uses FSYNC
as its TSIN signal. All subsequent devices use Control Formats
the TSOUT of the previous device as its TSIN
input. TSIN must be high for at least 1 SCLK The CS4215 control registers have the functions
period and fall at least 2 SCLKs before start of a and time slot assignments shown in Table 1. The
new frame. register address is the time slot number when
D/C is 0. Reserved bits should be written as 0
Serial Interface Operation and could be read back as 0 or 1. When compar-
ing data read back, reserved bits should be
The serial interface format has a variable number masked. The SDOUT pin goes into a
of time slots, depending on the number of high-impedance state prior to Time Slot 1 and
CS4215s attached to the bus. All time slots have after Time Slot 8. The data listed below the reg-
8 bits. Each CS4215 requires 8 time slots (64 ister is its reset state.
bits) to communicate all data (see Figure 9).
The parallel port register is used to read and
CONTROL MODE write the two open-drain input/output pins. The
outputs are all set to 1 on RESET. PIO bits are
The Control Mode is used to set up the CS4215 read only in control mode. Note that, since PIO
for subsequent operation in Data Mode by load- signals are open drain signals, an external device
ing the internal control registers. Control mode is
asserted by bringing D/C low. If D/C is low dur- Time slot Description
ing power up, then the CS4215 will enter control
mode immediately. The SCLK and FSYNC pins 1 Status
2 Data Format
are tri-stated, and the CS4215 will receive SCLK
3 Serial Port Control
and FSYNC from an external source. If the 4 Test
CS4215 is in master mode (SCLK and FSYNC 5 Parallel Port
are outputs) and D/C is brought low, then SCLK 6 RESERVED
& FSYNC will continue to be driven for a mini- 7 Revision
8 RESERVED
mum of 4 and a maximum of 12 SCLKs, if the
ITS bit = 0. If ITS is 1, SCLK and FSYNC will
three-state immediately after D/C goes low. If
D/C is brought low when the codec is pro- Table 1. Control Registers
grammed as master with ITS=0, the codec will

DS76F2 15
 CS4215

may drive them low even when they have been

programmed as highs. Therefore, the value read
back may differ from the value written. In the
data mode, (D/C=1), this register can be read
and written to through the serial port as part of
the Input Settings Registers. In control mode,
(D/C=0) these bits can only be read.

16 DS76F2
 CS4215

Lower output level to

maximum attenuation

Mute the speaker output

Set D/C low

Wait at least 12 SCLK

Y Codec programmed for
periods for FSYNC and
Master mode & ITS=0?
SCLK to three-state

Set external controller to 1 This is a software design choice,

drive SCLK and FSYNC
not a run-time conditional branch.
into the codec

1 N
Poll for CLB=0? n=5

Y
Send valid control information Send valid control information
with CLB=0 with CLB=0

Read back and verify control information.

n=n-1
Mask off reserved bits

N N
CLB=0? n = 0?
Y Y
Set CLB=1 and send at least
two more frames of valid
control information 2 2
This will cause the codec to
ignore any further bus activity.
The SDOUT pin will be held in
Set external controller to Is codec the high impedance state after
Y
receive SCLK and FSYNC programmed for transmitting 1 frame with CLB=1
from the codec Master mode?

N
Set D/C high.

Transmit/receive data with attenuated outputs

and muted speaker for 194 FSYNC cycles
while codec executes offset calibration

Transmit/receive audio data

with desired level settings

Figure 11. Control Mode Flow Chart

DS76F2 17
 CS4215

Control Time Slot 1, Status Register

D7 D6 D5 D4 D3 D2 D1 D0
Register 0 0 1 MLB OLB CLB RSRV
Reset (R) 0 0 1 0 0 1 X X

BIT NAME VALUE FUNCTION

RSRV Reserved Bits Must be written as 0.
CLB Control Latch Bit 1 R Ensures proper transition between control and
data mode.
OLB Output Level Bit 0 R Line full scale outputs are 2.8 Vpp (1Vrms)
Headphone full scale output is 4.0 Vpp.
Speaker full scale output is 8.0 Vpp.
1 Line and Headphone full scale outputs are
2.0 Vpp. Speaker full scale output is 4.0 Vpp.
MLB Microphone Level 0 R 20 dB Fixed Gain Enabled
Full scale microphone inputs are 0.288 Vpp.
1 20 dB Fixed Gain Disabled
Full scale inputs are 2.88 Vpp.

Control Time Slot 2, Data Format Register

D7 D6 D5 D4 D3 D2 D1 D0
Register HPF RSRV DFR2 DFR1 DFR0 ST DF1 DF0
Reset (R) 0 X 0 0 0 0 0 1

BIT NAME VALUE FUNCTION

’s
DF1-0 Data Format 00 0 16-bit 2 -complement linear.
Selection 01 1 R 8-bit µ−Law.
10 2 8-bit A-Law.
11 3 8-bit unsigned linear.
ST Stereo Bit 0 R Mono Mode.
1 Stereo Mode.
DFR2-0 Data Conversion XTAL1(kHz) XTAL2 (kHz)
Frequency Selection CLKIN (÷) 24.576 MHz 16.9344 MHz
0 0 0 0 R 3072 8 5.5125
0 0 1 1 1536 16 11.025
0 1 0 2 896 27.42857 18.9
0 1 1 3 768 32 22.05
1 0 0 4 448 NA 37.8
1 0 1 5 384 NA 44.1
1 1 0 6 512 48 33.075
1 1 1 7 2560 9.6 6.615
RSRV Reserved Bit Must be written as 0
HPF High Pass Filter 0 R Disabled.
1 Enabled. A Digital High Pass Filter is used to force
the ADC DC offset to zero.

18 DS76F2
 CS4215

Control Time Slot 3, Serial Port Control Register

D7 D6 D5 D4 D3 D2 D1 D0
Register ITS MCK2 MCK1 MCK0 BSEL1 BSEL0 XCLK XEN
Reset (R) 0 0 0 0 1 0 0 1

BIT NAME VALUE FUNCTION

XEN Transmitter Enable 0 Enable the serial data output.
1 R Disable (high-impedance state) serial data output.
XCLK Transmit Clock 0 R Receive SCLK and FSYNC from external source
SLAVE Mode
1 Generate SCLK and FSYNC
MASTER Mode
BSEL1-0 Select Bit Rate 00 0 64 bits per frame.
01 1 128 bits per frame.
10 2 R 256 bits per frame.
11 3 Reserved.
MCK2-0 Clock Source Select 000 0 R SCLK is master clock, 256 bits per frame.
BSEL must equal 2, and XCLK must equal 0.
0 0 1 1 XTAL1, 24.576 MHz, is clock source.
0 1 0 2 XTAL2, 16.9344 MHz, is clock source.
0 1 1 3 CLKIN is clock source, and must be 256xFs.
1 0 0 4 CLKIN is clock source, DFR2-0 select sample
frequency.
ITS Immediate Three- 0 R SCLK and FSYNC three-state up to 12 clocks
State after D/C goes low.
1 SCLK and FSYNC three-state immediately
after D/C goes low.

Control Time Slot 4, Test Register

D7 D6 D5 D4 D3 D2 D1 D0
Register TEST ENL DAD
Reset (R) 0 0 0 0 0 0 0 0

BIT NAME VALUE FUNCTION

DAD Loopback Mode 0 R Digital-Digital Loopback.
1 Digital-Analog-Digital Loopback.
ENL Enable Loopback 0 R Disable.
Testing 1 Enable.
TEST Test bits The TEST bits must be written as zero, otherwise
special factory test modes may be invoked.

DS76F2 19
 CS4215

Control Time Slot 5, Parallel Port Register

D7 D6 D5 D4 D3 D2 D1 D0
Register PIO1 PIO0 RSRV
Reset (R) 1 1 X X X X X X

BIT NAME VALUE FUNCTION

RSRV Reserved Bits Must be written as 0.
PIO1-0 Parallel I/O Bits 11 3 R See the Parallel Input/Output Section.

Control Time Slot 6, Reserved Register

D7 D6 D5 D4 D3 D2 D1 D0
Register RSRV
Reset (R) X X X X X X X X

BIT NAME VALUE FUNCTION

RSRV Reserved Bits Must be written as 0.

Control Time Slot 7, Version Register

D7 D6 D5 D4 D3 D2 D1 D0
Register RSRV VER3 VER2 VER1 VER0
Reset (R) X X X X 0 0 1 0

BIT NAME VALUE FUNCTION

VER3-0 Device Version 0000 0 "C". See Appendix A.
Number 0001 1 "D". See Appendix A.
0010 2 R "E". This Data Sheet
RSRV Reserved Bits Must be written as 0.

Control Time Slot 8, Reserved Register

D7 D6 D5 D4 D3 D2 D1 D0
Register RSRV
Reset (R) X X X X X X X X

BIT NAME VALUE FUNCTION

RSRV Reserved Bits Must be written as 0.

20 DS76F2
 CS4215

128 1 2 3 4 64 65 66 67 68 69 128 1 2 3 4
SCLK

FSYNC,
TSIN A

TSOUT A,
TSIN B

TSOUT B

SDIN Data to A Data to B Data to A

SDOUT Data from A Data from B Data from A

_
D/C
Data Mode

Figure 12. Data Mode Timing for 2 CS4215’s

DATA MODE
Time slot Description
The data mode is used during conversions to 1 Left Audio MS8 bits
pass digital data between the CS4215 and exter- 2 Left Audio LS8 bits
nal devices. The frame sync rate is equal to the 3 Right Audio MS8 bits
value of the conversion frequency set by the 4 Right Audio LS8 bits
DFR2-DFR0 bits of the Data Format register. 5 Output Setting
6 Output Setting
Each frame has either 64, 128, or 256 bit times 7 Input Setting
depending on the BSEL bits in the Serial Con- 8 Input Setting
trol register. Control of gain, attenuation, input
selection and output muting are embedded in the Table 2. Data Registers
data stream.

Data Formats
+FS

All time slots contain 8 bits. The MSB of the

data is transmitted/received first. The CS4215
ANALOG VALUE

data registers have the functions and time slot as-

signments shown in Table 2. The register address 0
is the time slot number when D/C is 1. The
SDOUT pin goes into a high-impedance state
prior to time slot 1 and after Time Slot 8 (see
Figure 12).
-FS
8-bit 0 65 128 191 255
The CS4215 supports four audio data formats: unsigned:
16-bit -32768
16-bit 2’s-complement linear, 8-bit unsigned lin- 2’s comp:
-16384 0 16384 32767

ear, 8-bit A-Law, and 8-bit µ-Law. Figure 13 DIGITAL CODE

illustrates the transfer characteristic for 16-bit

Figure 13. Linear Data Formats
and 8-bit linear formats. Note that a digital code

DS76F2 21
 CS4215

+FS
(12) bits for the DACs and compressed from the
upper 13 (12) bits to 8 bits for the ADCs.

Data Time Slot 1&2, Left Channel Audio Data

ANALOG VALUE

Time slot 1 and 2 contain audio data for the left

0
channel. In mono modes, only the left channel
data is used, however both the right and left
output DACs are driven. In 8-bit modes, only
time slot 1 is used for the data.
-FS
A-Law: 2Ah 15h 55h/D5h 95h AAh Data Time Slot 3&4, Right Channel Audio Data
u-Law: 00h 3Fh 7Fh/FFh BFh 80h
DIGITAL CODE
Time slot 3 and 4 contains audio data for the
Figure 14. Companded Data Formats
right channel. In mono modes, the right ADC
outputs zero and the right DAC uses the left
of 128 (80 Hex) is considered analog zero for digital data. In 8-bit modes, only time slot 3 is
the 8-bit unsigned format. used for the data.

A non-linear coding scheme is used for the com- Figure 15 summarizes all the time slot bit alloca-
panded formats as shown in Figure 14. This tions for the 4 data modes and for control mode.
scheme is compatible with CCITT G.711. Com-
panding uses more precision at lower amplitudes Reset
at the expense of less precision at higher ampli-
tudes. µ-Law is equivalent to 13 bits at low RESET going low causes all the internal control
signal levels and A-Law is equivalent to 12 bits. registers to be set to the states shown with each
This low-level dynamic range is obtained at the register description. RESET must be brought low
expense of large-signal dynamic range which, for and high at least once after power up. RESET
returning high causes the CS4215 to execute an
both µ-Law and A-Law, is equivalent to 6 bits.
offset calibration cycle. RESET or D/C returning
The CS4215 internally operates at 16 bits. The
high should occur at least 50 ms after the power
companded data is expanded to the upper 13
supply has stabilized to allow the voltage refer-
ence to settle.
Data Time Slot 5, Output Setting
D7 D6 D5 D4 D3 D2 D1 D0
Register HE LE LO5 LO4 LO3 LO2 LO1 LO0
Reset (R) 0 0 1 1 1 1 1 1

BIT NAME VALUE FUNCTION

LO5-0 Left Channel Output 1 1 1 1 1 1 63 R 1.5dB attenuation steps. LO5 is the MSB.
Attenuation Setting 0 = no attenuation. 111111 = -94.5dB
LE Line Output Enable 0 R Analog line outputs off (muted).
1 Analog line outputs on.
HE Headphone Output 0 R Headphone output off (muted).
Enable 1 Headphone output on.

22 DS76F2
 CS4215

Data Time Slot 6, Output Setting

D7 D6 D5 D4 D3 D2 D1 D0
Register ADI SE RO5 RO4 RO3 RO2 RO1 RO0
Reset (R) 1 0 1 1 1 1 1 1

BIT NAME VALUE FUNCTION

RO5-0 Right Channel 1 1 1 1 1 1 63 R 1.5dB attenuation steps. RO5 is the MSB.
Output Attenuation 0 = no attenuation. 111111 = -94.5dB
Setting Not used in mono modes.
SE Speaker Enable 0 R Speaker off (muted).
1 Speaker on.
ADI A/D Data Invalid 0 A/D data valid.
1 R A/D data invalid. Busy in calibration.

Data Time Slot 7, Input Setting

D7 D6 D5 D4 D3 D2 D1 D0
Register PIO1 PIO0 OVR IS LG3 LG2 LG1 LG0
Reset (R) 1 1 0 0 0 0 0 0

BIT NAME VALUE FUNCTION

LG3-0 Left Channel Input 0000 R 1.5dB gain steps. LG3 is the MSB.
Gain Setting 0 = no gain, 1111 = 22.5dB gain.
IS Input Select 0 R Line level inputs (LINL, LINR).
1 Microphone level inputs (MINL, MINR).
OVR Overrange 0 R When read as 1, this bit indicates that an input over-
range condition has occurred. The bit remains set
until cleared by writing 0 into the register. Writing
a 1 enables the overrange detection. The bit will
remain 0 until an over-range occurs. Serial port
clear has priority over internal settings.
PIO1-0 Parallel I/O 11 3 R Parallel input/output bits.

Data Time Slot 8, Input Setting

D7 D6 D5 D4 D3 D2 D1 D0
Register MA3 MA2 MA1 MA0 RG3 RG2 RG1 RG0
Reset (R) 1 1 1 1 0 0 0 0

BIT NAME VALUE FUNCTION

RG3-0 Right Channel Input 0000 R 1.5dB gain steps. RG3 is the MSB.
Gain Setting 0 = no gain, 1111 = 22.5dB gain.
MA3-0 Monitor Path 1111 15 R 6dB attenuation steps. MA3 is the MSB.
Attenuation 0 = no attenuation, 1111 = mute.

DS76F2 23
24
1 2 3 4 5 6 7 8
16 Bit Stereo
RIGHT CHANNEL AUDIO LO RO
IS

SE
PIO

ADI

HE
LEFT CHANNEL AUDIO LG MA RG

LE

LSB
LSB
OVR

MSB
MSB
16 Bit Mono
IS

PIO

HE
LEFT CHANNEL AUDIO LO RO LG MA

LE
SE

LSB
OVR

ADI

MSB
8 Bit Stereo
IS

HE
LO RO PIO LG MA RG

LE
LEFT RIGHT
SE
ADI

LSB
LSB
OVR

MSB
MSB
8 Bit Mono
IS

PIO

HE
LO RO LG MA

LE
LEFT
SE

LSB
OVR

ADI

MSB
Control Mode
0 0 1 DFR DF MCK TEST VERSION

ST
BSEL PIO

ITS

CLB
OLB
HPF
ENL

MLB
XEN
DAD

XCLK
CS4215

Figure 1 5. Time Slot/Register Overview

DS76F2
 CS4215

C S4215

A/ µ LOUT
SDIN D /A A tte n u a tio n
D e co d e ROUT

DAD (S till O p e ra te )
DD
D ig ita l-
D ig ita l-D igita l M o n ito r = 1 1 1 1 A n a lo g -
L o o p b a ck (Full M ute) D ig ita l
L o o p b a ck

LIN
A/ µ
SDOUT A/D G a in
E n co d e R IN
(D isco n n e cte d )

C S4215

A/ µ LO UT
SDIN D /A A tte n ua tio n
D ecod e ROUT
(D A C d a ta = 0 )
0 is d iffe re n t fo r
e a ch d a ta
format M o n ito r = 0

ADA

A/ µ LIN
SDOUT A /D G a in
E n co d e R IN

Figure 16. DD, DAD & ADA Loopback Paths

Power Down Mode LOOPBACK TEST MODES

Bringing the PDN pin high puts the CS4215 into The CS4215 contains three loopback modes that
the power down mode. In this mode HEADC may be used to test the codec. Two of the loop-
and CMOUT will not supply current. Power back test modes are designed to allow the host to
down will change all the control registers to the perform a self-test on the CS4215. The third
reset state shown under each Control Time Slot mode allows laboratory testing using external
register. In the power down mode, the TSOUT equipment.
pin will follow the TSIN state with less than
10 ns delay. Host Self-Test Loopback Modes

After returning to normal operation from power Since the CS4215 is a mixed-signal device, it is
down, an offset calibration cycle must be exe- equipped with an internal register that will en-
cuted. Either bringing RESET low then high, or able the host to perform a two-tiered test on
updating the control registers, will cause an off- power-up or as needed. The loopback test is en-
set calibration cycle. In either case, a delay of abled by setting the Enable Loopback bit, ENL,
50 ms must occur after PDN goes low before in control register 4. The first tier of loopback is
executing the offset calibration. This allows the a digital-digital loopback, DD, which is selected
internal voltage reference time to settle. by clearing the DAD bit in control register 4 (see

DS76F2 25
 CS4215

Figure 16). DD loopback checks the interface Analog-to-Analog Loopback Mode

between the host and the CS4215 by taking the
data on SDIN and looping it back onto SDOUT, A third loopback mode is achieved by setting the
with the data on SDOUT being one frame de- monitor attenuator to zero attenuation and send-
layed from the data on SDIN. The host can ing the DACs digital zero via SDIN. This
verify that the data received is exactly the same loopback is termed analog-digital-analog, ADA,
as the data sent, thereby indicating the interface since the selected analog input will now appear
between the two devices and the digital interface on the enabled analog outputs. Since this test is
on the CS4215 are operating properly. The out- controlled by external stimulus and the host is
put DAC’s are functional in DD loopback. Now not involved (except to send the DACs zeros), it
that the interface has been verified, the rest of is generally considered a laboratory test as op-
the CS4215 can be tested using the second tier posed to a self test. The bottom portion of
of loopback. Figure 16 illustrates the ADA signal flow
through the CS4215. Note that this test requires
The second tier of loopback is a digital-analog- the host send analog zeros to the DAC. Each
digital loopback, DAD, which is selected by data format has a different code for zero. See
setting the DAD bit in control register 4. DAD Figures 13 and 14.
loopback checks the analog section of the
CS4215 by connecting the right and left analog
outputs, after the output attenuator, to the analog
inputs of the gain stage. This allows testing of
most of the CS4215 from the host by sending a
known digital signal to the DACs and monitoring
the digital signal from the ADCs. During DAD
loopback, the monitor attenuator must be set at
maximum (full mute), and the analog outputs
may be individually muted. The analog inputs
are disconnected internally. The flow of test data
for both DD and DAD loopback modes is illus-
trated in the top portion of Figure 16.

Ferrite Bead
2.0 0.1 uF 0.1 uF
+5V
Supply + 1 uF 0.1 uF + + 1 uF
1 uF

3 8 23 24
VD1 VD2 VA1 VA2

CS4215

Figure 17. Optional Power Supply Arrangement

26 DS76F2
 CS4215

> 1/8"

Digital Analog Note that the CS4215

Ground Ground is oriented with its
Plane Plane digital pins towards the
Ground
digital end of the board.
Connection CS4215

+5V
Ferrite
Bead

Codec Codec
CPU & Digital
digital analog
Logic
signals signals &
Components

Figure 18. Suggested Layout Guideline

POWER SUPPLY AND GROUNDING on a solid ground plane as shown in Figure 18.
Preferably, it should also have its own power
When using separate supplies, the digital power plane. A single connection between the CS4215
should be connected to the CS4215 via a ferrite ground and the board ground should be posi-
bead, positioned closer than 1" to the device (see tioned as shown in Figure 18.
Figure 1). The codec VA1, VA2 pins should be
derived from the cleanest power source available. Figure 19 illustrates the optimum ground and de-
If only one supply is available, use the suggested coupling layout for the CS4215 assuming a
arrangement in Figure 17. VA1 supplies analog surface-mount socket and leaded decoupling ca-
power to the ADCs and DACs while VA2 sup- pacitors. Surface-mount sockets are useful since
plies p ower to the output power drivers the pad locations are exactly the same as the ac-
(headphones and speaker). The large currents tual chip; therefore, given that space for the
necessary for VA2 are not flowing through the socket is left on the board, the socket can be op-
2.0 Ω resistor, and therefore do not corrupt the tional for production. Figure 19 depicts the top
VA1 converter supply. layer containing signal traces and assumes the
bottom or inter-layer contains a solid analog
The CS4215 along with associated analog cir- ground plane. The important points with regards
cuitry, should be positioned near to the edge of to this diagram are that the ground plane is
the circuit board, and have its own, separate, SOLID under the codec and connects all codec
ground plane. On the CS4215, the analog and ground pins with thick traces providing the abso-
digital grounds are internally connected; there- lute lowest impedance between ground pins. The
fore, the four ground pins must be externally decoupling capacitors are placed as close as pos-
connected with zero impedance between ground sible to the device which, in this case, is the
pins. The best solution is to place the entire chip socket boundary. The lowest value capacitor is

DS76F2 27
 CS4215

0.1 u F

1 uF
Analog
+ Supply
1

+
Digital
Supply

10 uF
0.1 uF

0.1 uF
1 uF
+

Figure 19. CS4215 Decoupling Layout Guideline

0.1 uF

1 uF

1 Analog
+ Supply
0.1 uF

0.1 u F

+ 10 uF
Digital
Supply

+ 1 uF

Figure 20. CS4215 Surface Mount Decoupling Layout

28 DS76F2
 CS4215

placed closest to the codec. Vias are placed near 10

the AGND and DGND pins, under the IC, and 0
should be attached to the solid analog ground -10
plane on another layer. The negative side of the -20

Magnitude (dB)
decoupling capacitors should also attach to the -30
same solid ground plane. Traces bringing the -40

power to the codec should be wide thereby keep- -50

ing the impedance low. -60

-70
-80
Although not shown in the figures, the trace lay-
-90
ers (top layer in the figures) should have ground
-100
plane fill in-between the traces to minimize cou- 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
pling into the analog section. See the CDB4215 Input Frequency (Fs)

evaluation board data sheet for an example lay- Figure 21. ADC Frequency Response
out.

If using all surface-mount components, the de- 0.2

coupling capacitors should still be placed on the 0.1

layer with the codec and in the positions shown -0.0
Magnitude (dB)

in Figure 20. The vias shown are assumed to at- -0.1

tach to the appropriate power and analog ground -0.2
layers. Traces bringing power to the codec -0.3
should be as wide as possible to keep the imped- -0.4
ance low. For the same reason, vias should be
-0.5
large for power and ground runs.
-0.6
-0.7
If using through-hole sockets, effort should be
made to find a socket with the minimum height -0.8
0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
which will minimize the socket impedance. Input Frequency (Fs)
When using a through-hole socket, the vias un- Figure 22. ADC Passband Ripple
der the codec in Figure 19 are not needed since
the pins serve the same function. 0
-10
ADC and DAC Filter Response Plots -20
Magnitude (dB)

-30
Figures 21 through 27 show the overall fre-
-40
quency response, passband ripple and transition
-50
band for the CS4215 ADCs and DACs. Fig-
-60
ure 27 shows the DACs’ deviation from linear
-70
phase. Fs is the selected sample frequency. Since
-80
the sample frequency is programmable, the fil-
ters will adjust to the selected sample frequency. -90

Fs is also the FSYNC frequency. -100

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Input Frequency (Fs)

Figure 23. ADC Transition Band

DS76F2 29
 CS4215

10 0.2

0 0.1
-10 -0.0

Magnitude (dB)
-20
Magnitude (dB)

-0.1
-30
-0.2
-40
-0.3
-50
-0.4
-60
-70 -0.5

-80 -0.6
-90 -0.7
-100 -0.8
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs) Input Frequency (Fs)

Figure 24. DAC Frequency Response Figure 25. DAC Passband Ripple

0 2.5

-10 2.0

-20 1.5
Magnitude (dB)

-30 1.0
Phase (degrees)

-40 0.5
-50 0.0
-60 -0.5
-70 -1.0
-80 -1.5
-90 -2.0
-100 -2.5
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency (Fs)
Input Frequency (Fs)

Figure 26. DAC Transition Band Figure 27. DAC Deviation from Linear Phase

30 DS76F2
 CS4215

PIN DESCRIPTIONS

CLKOUT

DGND1

SDOUT
XTL1IN

FSYNC
TSOUT
CLKIN

SCLK
SDIN

TSIN
VD1
100

97
95
93
91
89
87
85
83
81
79
77
76
75
1 74 PIO1
XTL1OUT 2
CS4215 72 PIO0
VD2 4
100-PIN 70 D/C
DGND2 6
TQFP
XTL2IN 8 (Q)
66 LOUTR
XTL2OUT 10
Top View 64 LOUTL

RESET 14
60 HEADL
PDN 16
MINR 18
56 HEADC
LINR 20
MINL 22
52 HEADR
LINL 24 51
25
26

31
33
35
37
39
41
43
45

50
VA1
VA2
VREF
AGND1

AGND2
MOUT2
MOUT1
CMOUT

Note: All unlabeled pins are No Connects

DS76F2 31
 CS4215

SDIN
DGND1 SDOUT
VD1 SCLK
CLKIN FSYNC
CLKOUT TSOUT
XTL1IN TSIN
XTL1OUT NC
VD2 6 4 2 1 44 42 40
NC
7 39
DGND2 PIO1
8 38
XTL2IN 9 CS4215 37 PIO0
XTL2OUT 10 44-PIN 36
D/C
11 35
RESET 12 PLCC 34 NC
PDN 13 (L) 33
LOUTR
14 32
NC 15 31 LOUTL
MINR 16 Top View 30
HEADL
17 29
LINR 18 20 22 24 26 28 HEADC
MINL HEADR
LINL MOUT1
CMOUT MOUT2
NC NC
VREF AGND2
AGND1 VA2
VA1

Power Supply
VA1, VA2 - Analog Power Input, Pins 23(L), 24(L), 37(Q), 39 (Q)
+5 V analog supply.

AGND1, AGND2 - Analog Ground, Pins 22(L), 25(L), 35(Q), 41(Q)

Analog ground. Must be connected to DGND1, DGND2 with zero impedance.

VD1, VD2 - Digital Power Input, Pins 3(L), 8(L), 91(Q), 4(Q)
+ 5 V digital supply.

DGND1, DGND2 - Digital Ground, Pin 2(L), 9(L), 89(Q), 6(Q)

Digital ground. Must be connected to AGND1, AGND2 with zero impedance.

32 DS76F2
 CS4215

Analog Inputs
LINL, LINR - Left and Right Channel Line Level Inputs, Pins 18(L), 16(L), 24(Q), 20(Q)
Line level input connections for the right and left channels.

MINL, MINR - Left and Right Channel Microphone Inputs, Pins 17(L), 15(L), 22(Q), 18(Q)
Microphone level input connections for the right and left channels.

Analog Outputs
LOUTR, LOUTL - Line Level Outputs, Pins 33(L), 32(L), 66(Q), 64(Q)
One pair of line level outputs are provided. The output level for right and left outputs can be
independently varied. These outputs can be muted.

HEADR, HEADL - Headphone Outputs, Pins 29(L), 31(L), 52(Q), 60(Q)

HEADR and HEADL are intended to drive a pair of headphones. Additional current drive,
along with an optional +3 dB of gain, ensures reasonable listening levels. These outputs can be
muted.

HEADC - Common Return for Headphone Outputs, Pin 30(L), 56(Q)

HEADC is the return path for large currents when driving headphones from the HEADR and
HEADL outputs. This pin is nominally at 2.1 V.

CMOUT - Common Mode Output, Pin 19(L), 31(Q)

Common mode voltage output. This signal may be used for level shifting the analog inputs. The
load on CMOUT must be DC only, with an impedance of not less than 10kΩ. CMOUT should
be bypassed with a 0.47 µF to AGND. CMOUT is nominally at +2.1V.

MOUT1, MOUT2 - Mono Speaker Outputs, Pins 28(L), 27(L), 45(Q), 43(Q)
Mono external loudspeaker differential output connections. The loudspeaker output is a mix of
left and right line outputs. Independent muting of the speaker is provided. MOUT1 and
MOUT2 output voltage is nominally at 2.1 V with no signal.

VREF - Voltage Reference Output, Pin 21(L), 33(Q)

The on-chip generated ADC/DAC reference voltage is brought out to this pin for decoupling
purposes. This output must be bypassed with a 10 µF capacitor in parallel with a 0.1 µF
capacitor to the adjacent AGND1 pin. No other external load may be connected to this output.

Digital Interface Signals

SDIN - Serial Data Input, Pin 1(L), 87(Q)
Audio data for the DACs and control information for all functions is presented to the CS4215
on this pin.

SDOUT - Serial Data Output, Pin 44(L), 85(Q)

Audio data from the ADCs and status information concerning all functions is written out by the
CS4215 onto this pin.
DS76F2 33
 CS4215

SCLK - Serial Port Clock, Pin 43(L), 83(Q)

SCLK rising causes the data on SDOUT to be updated. SCLK falling latches the data on SDIN
into the CS4215. The SCLK signal can be generated off-chip, and input into the CS4215.
Alternatively, the CS4215 can generate and output SCLK in data mode.

FSYNC - Frame Sync Signal, Pin 42(L), 81(Q)

The Frame Synchronizing Signal is sampled by SCLK, with a rising edge indicating a new
frame is about to start. FSYNC frequency is always the system sample rate. Each frame may
have 64, 128 or 256 data bits, allowing for 1, 2 or 4 CS4215s connected to the same bus.
FSYNC may be input to the CS4215, or may be generated and output by the CS4215 in data
mode. When FSYNC is an input, it must be high for at least 1 SCLK period. FSYNC can stay
high for the rest of the frame, but must return low at least 2 SCLKs before the next frame starts.

TSIN - Time Slot Input, Pin 40(L), 77(Q)

TSIN high for at least 1 SCLK cycle indicates to the CS4215 that the next time slot is allocated
for it to use. TSIN is normally connected to the TSOUT pin of the previous device in the chain.
TSIN should be connected to FSYNC for the 1st (or only) CS4215 in the chain.

TSOUT - Time Slot Output, Pin 41(L), 79(Q)

TSOUT goes high for 1 SCLK cycle, indicating that the CS4215 is about to release the data
bus. Normally connected to the TSIN pin on the next device in the chain.

D/C - Data/Control Select Input, Pin 35(L), 70(Q)

When D/C is low, the information on SDIN and SDOUT is control information. When D/C is
high, the information on SDIN and SDOUT is data information.

PDN - Power Down Input, Pin 13(L), 16(Q)

When high, the PDN pin puts the CS4215 into the power down mode. In this mode HEADC
and CMOUT will not supply current. Power down causes all the control registers to change to
the default reset state. In the power down mode, the TSOUT pin remains active, and follows
TSIN delayed by less than 10 ns.

RESET - Active Low Reset Input, Pin 12(L), 14(Q)

Upon reset, the values of the control information (when D/C = 0) will be initialized to the
values given in the Reset Description section of this data sheet.

Clock and Crystal Pins

XTL1IN, XTL1OUT, XTL2IN, XTL2OUT - Crystals 1 and 2 Inputs and Outputs, Pins 6(L),
7(L), 10(L), 11(L), 97(Q), 2(Q), 8(Q), 10(Q)
Input and output connections for crystals 1 and 2. One of these oscillators may provide the
master clock to run the CS4215.

CLKIN - External Clock Input, Pin 4(L), 93(Q)

External clock input optionally used to clock the CS4215. The CLKIN frequency must be
256 times the maximum sample rate (FSYNC frequency).

34 DS76F2
 CS4215

CLKOUT - Master Clock Output, Pin 5(L), 95(Q)

Master clock output, whose frequency is always 256 times the system sample rate (FSYNC
frequency). CLKOUT is active only in data mode and is low during control mode.

Miscellaneous Pins
PIO0, PIO1 - Parallel Input/Output, Pins 36(L), 37(L), 72(Q), 74(Q)
These pins are provided as general purpose digital parallel input/output and have open drain
outputs. An external pull-up resistor is required. They can be read in control mode, and read
and written to in data mode.

Note: All unlabeled pins are No Connects which should be left floating.

DS76F2 35
 CS4215

PARAMETER DEFINITIONS

Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.

Differential Nonlinearity
The worst case deviation from the ideal codewidth. Units in LSB.

Total Dynamic Range

The rms value of a full scale signal to the lowest obtainable noise floor. It is measured by
comparing a full scale signal to the lowest noise floor possible in the codec (ie. attenuation bits
for the DACs at full attenuation.) Units in dB.

Instantaneous Dynamic Range

The dynamic range available at any instant in time. It is measured using S/(N+D) with a 1 kHz,
-60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small
input signal reduces to harmonic distortion components of the noise to insignificance. Units in
dB.

Total Harmonic Distortion

THD is the ratio of the rms value of a signal’s first five harmonic components to the rms value
of the signals fundamental component. THD is calculated for the ADCs using an input signal
which is 3dB below typical full-scale, and is referenced to typical full-scale. A digital full-scale
output is used to calculate THD for the DACs.

Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
0 dB signal present on the other channel. Units in dB.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.

Frequency Response
Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB.

Step Size
Typical delta between two adjacent gain or attenuation values. Units in dB.

Absolute Step Error

The deviation of a gain or attenuation step from a straight line passing through the
no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB.

36 DS76F2
 CS4215

Out-of-Band Energy
The ratio of the rms sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale
signal value. Tested with 48kHz Fs giving an out-of-band energy range of 22kHz to 100kHz.

Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input at
CMOUT. For the DACs, the deviation of the output from CMOUT with mid-scale input code.
Units in volts.

DS76F2 37
 CS4215

APPENDIX A

This data sheet describes version 2 of the CS4215. Therefore, this appendix is included to describe the
differences between versions 0,1 and version 2. This information is only useful for users that still have
version 0 and version 1 devices since version 2 devices will supplant the earlier versions. The version
number can be found in control mode, time slot 7. The version can also be identified by the revision
letter stamped on the top of the actual chip. The revision letter immediately precedes the data code on
the second line of the package marking (See General Information section of the Crystal Data Book).
Version 0 corresponds to chip revision C, version 1 corresponds to chip revision D, and version 2 cor-
responds to chip revision E. Future chip revisions (ie. F, G, H) may still be version 2 since the version
number only changes if there is a register change to the part that will affect driver software.
The Functional Differences Between Version 0(Rev. C) and Version 1(Rev. D)
1. FSYNC on version 0 must be ONLY one SCLK period high, whereas on version 1 FSYNC must be
AT LEAST one SCLK period high.

2. When driving an external CMOS clock into one of the XTL-IN pins, version 0 devices must have a
series resistor of at least 1kΩ between the CS4215 and the clock source. The resistor is needed be-
cause the codec will put XTL-IN to ground (on version 0 only) when that crystal is not selected, as is
the case on power-up. In version 1 the XTL-IN pins are floated when not selected; therefore, the series
resistor is not needed on version 1. Version 1 will work properly if the resistor is included.

3. The OLB and ITS bits do not exist on version 0. Writing these bits as zero makes both versions
function identically; therefore, version 1 is backwards compatible with version 0.

4. When entering control mode, CLKOUT stops 4 to 12 clocks later and may start up briefly when
switching master clock sources on version 0. On version 1 CLKOUT stops within two clocks and
doesn’t start up until data mode is entered.

5. In version 0 the headphone and speaker outputs are not short-circuit protected, whereas in version 1
they are short-circuited protected.
The functional differences between Version 1(Rev. D) and Version 2(Rev. E)
1. The MLB, HPF, and MCK2 bits in control mode do not exist in version 0 or version 1. Writing
these bits as zero makes all versions functionally identical; therefore, version 2 is backwards compat-
ible with previous versions.

2. The A/D invalid bit, ADI, in data mode does not exist in version 0 or version 1.

3. The 8-bit unsigned data format (DF1,0=3) does not exist in version 0 or version 1.

4. SDOUT contained random data during calibration in versions 0 and 1. SDOUT outputs zeros dur-
ing calibration in version 2.

38 DS76F2
 CDB4215
Semiconductor Corporation

CS4215 Evaluation Board

Features General Description

•
The CDB4215 evaluation board allows easy evaluation
Easy DSP Hook-Up of the CS4215 audio multimedia codec. Analog inputs
provided include two 1/4" microphone jacks and two

• Correct Grounding and Layout

BNC line inputs. Analog outputs provided are two BNC
line outputs, one stereo 1/4" headphone jack and one
pair of speaker terminals.
Digital interfacing is facilitated by two buffered ribbon
• Microphone Pre-Amplifier cable headers. One contains the serial port and the
other contains the codec control pins.

• Line Input Buffer

• Digital Patch Area ORDERING INFORMATION: CDB4215

+5VA AGND DGND +5VD

Microphone
A = 23 dB CLKOUT
Jacks

CLKIN

Line Inputs A = - 6 dB Digital Control

I/O Pin
CS4215 Buffers Header
Line Outputs Serial
Port
Headphone Header
Jack
Digital
Speaker PIO Patch
Terminals Indicators Area

Crystal Semiconductor Corporation JUL ’93

P.O. Box 17847, Austin, TX 78760 Copyright  Crystal Semiconductor Corporation 1992 DS76DB3
(All Rights Reserved)
(512) 445 7222 Fax: (512) 445 7581 39
 CDB4215

GENERAL INFORMATION header buffer circuitry. Space for a ferrite bead

inductor, L1, has been provided so that the board
The CDB4215 is designed to provide an easy may be modified to power the codec from the
platform for evaluating the performance of the digital supply. Selection of L1 will depend on
CS4215 Multimedia Audio Codec. The board the characteristics of the noise on the digital sup-
provides a buffered serial interface for easy con- ply used.
nection to the serial port of a DSP or other serial
device. A single +5 V power supply is all that is
required to power the evaluation board. ANALOG INPUTS

The line input buffers are designed to accept The analog inputs consist of a pair of 1/4" jacks
standard CD-level inputs of 2 VRMS and BNC- for two microphones, and a pair of BNC’s for
to-phono adapters are included to support line level inputs. BNC-to-phono adapters are in-
various test setups. The microphone inputs con- cluded to allow testing of the line inputs using
sist of two 1/4" mono jacks that are designed to coax or standard audio cables.
accept standard single-ended dynamic or con-
denser microphones. The line-level inputs go through a buffer, Fig-
ure 2, with a gain of 0.5 which allows input
The line outputs are supplied via BNC jacks signals of up to 2 VRMS.
with two more BNC-to-phono adapters. The
headphone output is supplied via a 1/4" stereo The two microphone inputs are single-ended and
jack and will drive headphones of 48 Ω or are designed to work with both condenser and
greater. This includes most "walkman" style dynamic mics. The microphone input buffer cir-
headphones. Speaker terminals are provided and cuit, shown in Figure 3, has a gain of 23 dB
can be connected to speakers with an impedance thereby defining a full-scale input voltage to the
of 32 Ω or greater. mic jacks of 19.5 mVpp.

The film plots of the board are included to pro-

vide an example of the optimum layout, ANALOG OUTPUTS
grounding, and decoupling arrangement for the
CS4215. The CDB4215 includes three analog output
paths: a pair of line output BNC’s, a stereo 1/4"
headphone jack, and a pair of mono speaker ter-
POWER SUPPLY CIRCUITRY minals.

Figure 1 illustrates a portion of the CDB4215 The CS4215 drives the line outputs into an R-C
schematic and includes the CS4215 codec along filter and then to a pair of BNC’s. As with the
with power supply circuitry. Power is supplied to line inputs, BNC-to-phono adapters are provided
the board via two sets of binding posts, one for for flexibility. The line outputs can drive an im-
digital and one for analog. The analog supply pedance of 10 kΩ or more, which is the typical
must be +5 Volts and supplies power for the en- input impedance of most audio gear.
tire codec (both digital and analog power supply
pins) along with the analog input buffers for the The stereo headphone output can drive head-
line and microphone inputs. The digital supply is phones with an impedance of 48 Ω or greater.
also +5 Volts and supplies power to the digital This includes most "walkman" style headphones.

40 DS76DB3
 CDB4215

Ferrite Bead R28

+5VD VD L1 2 VA +5VA

D2 + 47 uF 0.1 uF + 1 uF 0.1 uF + 1 uF 0.1 uF 0.1 uF 47 uF + D1

P6KE C32 C30 C14 C13 C11 C12 C31 C33 P6KE

DGND
AGND
3 8 23 24
VD1 VD2 VA1 VA2
15 C34
MINR 28
Microphone MOUT1
19 + R52
Input Buffer CMOUT 22 uF 50 k MOUT1
See Figure 3 17 MINL
C16 R51
27 50 k
16 CS4215 MOUT2 +
Line Input LINR
22 uF MOUT2
Buffer
18
U1 16 1/2W
See Figure 2 LINL HEADR 29
R21
40pF 10 XTL2IN 31 R20 Headphones
C24 HEADL
Y2
30 16 1/2W
16.9344 MHz HEADC
40pF 11 XTL2OUT C29
R24
C25 600 1 uF LOUTR
33 +
LOUTR
40pF 6
XTL1IN 0.0022 uF C27 39 k
C22 Y1 NPO R26
24.576 MHz R25 C28
40pF 7 600 1 uF LOUTL
XTL1OUT 32 +
C23 LOUTL
0.0022 uF C26 39 k
NPO R27

4 CLKIN 21
See Fig 5 VREF +
0.1 uF 10 uF
C21 C20

AGND1 AGND2 DGND1 DGND2

22 25 2 9

Figure 1. CS4215 & Power Supplies

DS76DB3 41
 CDB4215

C19 56 pF NPO
VA
R19 10 k
C36
LINR 0.47 uF 0.1 uF
20 k CS4215
2 _ 8 150
1 16
R12 3 + LINR
C17 4 R14 0.01 uF NPO
C10
5k 19
U3
CMOUT
LT1013 + 1 uF R17
C35
LINL
(Mono) 5 150
0.47 uF + 7 18
20 k 6 _ LINL
R15 C9
R13 R18 10 k 0.01 uF
C37
NPO

C18 56 pF NPO

Figure 2. Line Input Buffer

R6 R4

1.5 k 22.1 k
+ C4
10 uF C6 560 pF
VA+
NPO
C8
2 8 R56 C48 CS4215
1 uF 0.1 uF
15
+ 3 MINR
1
4 150 0.47 uF
MINR NPO
C5 U2 C47
0.01 uF
R5 MC33178
50 k
19
CMOUT
+
R2 C7 1 uF
50 k
MINL C2
5 R57 C45
(Mono) 7 17
+ 6 MINL
1 uF
150 0.47 uF
NPO
C1 560 pF C46
0.01 uF
NPO

1.5 k 22.1 k

R3 R1
+
10 uF C3

Figure 3. Microphone Input Buffer

42 DS76DB3
 CDB4215

Speaker terminals are provided and are labeled mode. In control mode the codec is always a
MOUT1 and MOUT2. Speakers connected to the slave and FSYNC and SCLK must be driven
terminals must have an impedance of 32 Ω or from the DSP. Since the evaluation board buffers
greater. DC blocking capacitors are included to all the signals between the codec and the DSP,
form a high-pass filter with the speaker imped- the board must "know" which of the two modes
ance. This filter blocks very low frequency is being used. Jumper P3 selects the particular
signals which can heavily distort some inexpen- mode.
sive speakers.
Codec Master Data Mode

SERIAL INTERFACE When the codec is to be programmed as a mas-

ter in data mode, the direction of FSYNC and
The CDB4215 is primarily designed to evaluate SCLK have to be changed between control mode
the CS4215 is single chip mode, i.e. only one and data mode. In this case the P3 jumper must
codec on the serial bus. This is the default state be set for "M/S" which uses the D/C signal to
for the CDB4215 and is defined by having the control the direction of the buffers (U7) for
P4 jumper in the "1CHIP" position, see Figure 4, SCLK and FSYNC. When P3 is set to M/S, the
which connects FSYNC to TSIN. This connec- buffers drive the J15 header in data mode and
tion defines the board codec’s time slots as the receives FSYNC and SCLK from the header in
first 64 bits of the frame. The only signals that control mode.
need to be connected to the DSP are the five sig-
nals on header J15. The serial interface is Codec Slave Data Mode
illustrated in Figure 4.
When the codec is to be programmed as a slave
If the goal is to connect multiple CDB4215s on in data mode, FSYNC and SCLK are always in-
the same serial port, jumper P4 must be in the puts to the codec. In this mode P3 must be set to
"MULTI" position which disconnects TSIN from "SLAVE" which configures the FSYNC and
FSYNC. The MULTI position also connects an SCLK buffers to always receive FSYNC and
unbuffered SDOUT to header J14. This header SCLK from the J15 header.
pin, SDOUTUB, must be used in lieu of
SDOUT since SDOUT is buffered and does not As stated in the CS4215 data sheet, when the
go high impedance during other codec’s time codec is programmed in slave mode, XCLK = 0
slots. Using the multi-chip scenario, the TSIN in control mode, SCLK and FSYNC are inputs
header pin must be connected to the previous and must be derived from the same clock used as
codec’s TSOUT line and the first codec’s TSIN the master clock for the codec. Although SCLK
must be connected, via the header, to FSYNC. and FSYNC must be frequency locked to the
master clock, there is no phase requirement.
Note that when P4 is in the 1CHIP mode, the
SDOUTUB pin on header J14 is not connected
to the SDOUT pin on the CS4215 and is float- CONTROL PINS
ing.
All control pins, located on header J14, are de-
There are two scenario’s that must be addressed fined as pins that are not essential to the DSP
when connecting the CDB4215 to a DSP: one is serial port when used in 1CHIP mode.
when the codec is the master in data mode and
the other is when the codec is a slave in data
DS76DB3 43
 CDB4215

VD

P3
M/S 14 C41 0.1 uF
SLAVE 1
13 U7
R43 1k OEB OEA 74HCT243
43 11 3 VD
SCLK B0 A0
42 10 4
FSYNC B1 A1 C49
9 5 RP2
R44 1k
8 B2 A2 6 20 k SIP 1 0.1 uF
VD B3 A3
GND
C40
7
U1 40 k 2
0.1 uF 8
CS4215 RP1
R49
20 100 Ohm Dip
35 18 2 16 1 J15
D/C
D/C
44 3 17 SDOUT
SDOUT
SDIN
1 16 4
SDIN SCLK
FSYNC
40 15 5
TSIN P4
1CHIP
MULTI TSIN
41 6 14
TSOUT
TSOUT
7 13 9 8 PDN
R47
PIO0
20 k
13 12 8 PIO1
PDN
RESET
5 9 11
CLKOUT SDOUTUB

J14
10

U4
R50
74HTC541
VD CLKOUT
50
C42 R9
0.1 uF 20 k
14 U5B
10 R42
12 8 4
RESET 6
5 100 R55 VD
U5C 9
7 800
VD

D3 R7 RESET PIO0
800 R54
47 k 100
IN4148
237 k D3
+ R8
C15 Q2
1 uF R30 PIO1

PIO0 36 237 k D4
Q3
37 R53
PIO1
Q2,Q3 = MPSA14

Figure 4. Digital Interface

44 DS76DB3
 CDB4215

PDN and RESET CLOCKS

Power down, PDN, controls the PDN pin on the The CDB4215 can accommodate all clocking
codec. The line has an on-board pull-down resis- modes supported by the CS4215. A CLKIN
tor thereby defining the default state as powered. BNC, as shown in Figure 5 allows the CLKIN
This pin only needs to be controlled if the power pin on the CS4215 to be used as the master
down feature is used. clock source. The two crystals listed in the
CS4215 data sheet are also provided and support
RESET controls the RESET pin on the codec all the audio and multimedia standard sample
and is pulled up on the board. This defines the frequencies. The master clock is selected via a
default state as not reset. This pin only needs to CS4215 internal register from control mode.
be controlled if the reset feature on the codec is
needed. Since the codec does require a reset at The CLKOUT BNC is a buffered version of the
power up, a power-up reset circuit is included on CLKOUT pin on the CS4215. CLKOUT is al-
the board. A reset switch is also included to reset ways 256 times the programmed sample
the device without having to remove the power frequency in data mode. CLKOUT is held low in
supply. The power-up reset plus switch are logi- control mode.
cally OR’ed with the RESET pin on header J14.

PIO Lines LAYOUT ISSUES

The parallel input/output, PIO, lines are pulled Figure 6 contains the silk screen, Figure 7 con-
up on the evaluation board. If they are to be used tains the top-side copper layer, and Figure 8
as inputs, they should be driven by open-collec- contains the bottom-side copper layer of the
tor gates since inadvertently setting the PIO bits CDB4215 evaluation board. These plots are in-
low in software will force the external lines low. cluded to provide an example of how to layout a
The PIO lines are available on header J14. PCB for the codec. Two of the more important
aspects are the position of the ground plane split,
The PIO lines also go through a high-impedance which is next to the part - NOT UNDER IT, and
buffer and drive LED’s on the evaluation board. the ground plane fill between traces on both lay-
When the LED is on, the corresponding bit is 1 ers, which minimizes coupling of radiated
or high. The LED’s provide a visual indication energy.
that may be used to verify that the software is
writing the bits correctly.

VD
CS4215
R16
10 k

U5D U5A
4 R32 13 1
CLKIN 11 3
12 2
1k
74HC132 74HC132 R29 CLKIN
5k

Figure 5. CLKIN

DS76DB3 45
 CDB4215

Figure 6. CDB4215 Board Silkscreen (Not to Scale)

46 DS76DB3
 CDB4215

Figure 7. CDB4215 Compont Side Layout (Not to Scale)

DS76DB3 47
 CDB4215

Figure 8. CDB4215 Solder Side Layout (Not to Scale)

48 DS76DB3
 44 pin
PLCC

NO. OF TERMINALS
MILLIMETERS INCHES
E1 E
DIM MIN NOM MAX MIN NOM MAX
A 4.20 4.45 4.57 0.165 0.175 0.180
A1 2.29 2.79 3.04 0.090 0.110 0.120
B 0.33 0.41 0.53 0.013 0.016 0.021
D/E 17.40 17.53 17.65 0.685 0.690 0.695
D1 D1/E1 16.51 16.59 16.66 0.650 0.653 0.656
D D2/E2 14.99 15.50 16.00 0.590 0.610 0.630
e 1.19 1.27 1.35 0.047 0.050 0.053

B e
A1 A

D2/E2
 D

D1
100 pin
TQFP

E E1

A
A1
C
e
B Terminal
Detail 1
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
A - - 1.66 - - 0.065 ∝
L
A1 0.00 - - 0.000 - - M
B 0.14 0.20 0.26 0.006 0.008 0.010
C 0.40 0.51 0.60 0.016 0.020 0.024
D 15.70 16.00 16.30 0.618 0.630 0.642
D1 13.90 14.00 14.10 0.547 0.551 0.555
E 15.70 16.00 16.30 0.618 0.630 0.642
E1 13.90 14.00 14.10 0.547 0.551 0.555
e 0.375 0.5 0.625 0.015 0.020 0.025
L 0.30 0.51 0.70 0.012 0.020 0.028
∝ 0° - 12° 0° - 12°
M 1.00 BSC 0.039 BSC
• Notes •
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation