ES8396

Low Power Stereo Audio CODEC

FEATURES DAC

• 24-bit, 8 to 96 kHz sampling frequency

System
• 95 dB dynamic range, 95 dB signal to
• High performance and low power multi- noise ratio, -85 dB THD+N
bit delta-sigma stereo ADC and DAC • Digital peak limiter (DPL)
• Two independent I2S/PCM master or • Pop and click noise suppression
slave serial data port
DSP
• Three pairs of analog input
• Four pairs of analog output • Flexible digital signal routing and mixing
• 2x0.9W stereo or 1.8W mono class D • Asynchronous sample rate conversion
speaker driver • Six programmable digital filters for PEQ
• Ground centered headphone driver and noise reduction
• Mono ear speaker driver • Stereo enhancement
• 256/384Fs, USB 12/24 MHz, fractional • Support u/A law
PLL for wide range of system clocks
• Sophisticated analog input and output Low Power
routing, mixing and gain
• Support analog and digital microphone • 1.8V to 3.3V operation
• GPIO • 7 mW playback; 16 mW playback and
• I2C interface record

ADC
APPLICATIONS
• 24-bit, 8 to 96 kHz sampling frequency
• 95 dB dynamic range, 95 dB signal to • MID/Phoblet
noise ratio, -85 dB THD+N • Smart Phone
• Low noise pre-amplifier • Digital amplifier
• Auto level control (ALC) and noise gate
• Microphone bias
ORDERING INFORMATION
ES8396 -40°C ~ +85°C
QFN-48

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 Everest Semiconductor Confidential ES8396

1. BLOCK DIAGRAM

GPIO1/DMIC_SCL1
GPIO2/DMIC_SCL2

DACDAT1
ADCDAT1

DACDAT2
ADCDAT2
BCLK1

BCLK2
LRCK1

LRCK2
MCLK

SDA
SCL

2 2 2
PLL IC GPIO I S/PCM 1 I S/PCM 2
Clock Mgr

DSP
ASRC
L/R Line Mixer Out Mixing
PGA Stereo ADC ALC Stereo
L/R Aux Mixer Out
ADC DAC DPL DAC
L/R Mono Mixer Out
Programmable Filters
PEQ
L/R ADC PGA Out SE
u/A Law

L/R DAC Out

AINL/AINR L/R Line Mixer Out LOUT1/ROUT1 (LOUT1N)

MONOP/MONON Line Mixer Line Driver
L/R Aux Mixer Out
Aux Mixer Aux Driver
AINL/AINR
L/R Mono Mixer Out MONOUTP/MONOUTN
MONOP/MONON
Mono Mixer Mono Driver
MIC1P/MIC1N
L/R HP Mixer Out HPLOUT/HPROUT
MIC2P/MIC2N
HP Mixer HP Driver
L/R, P/N SPK Mixer Out SPKLOUTP/SPKLOUTN
SPK Mixer SPK Driver
MICP/MICN D2S SPKROUTP/SPKROUTN
Preamp

Charge
Pump Mic Bias Analog Reference Power Supply and LDO
CPVSSP
CPBOT
CPTOP
CPGND
CPVDD

MICBIAS

VMID
DACVRP
ADCVRP

SPKGND
SPKLDO
SPKVDD2
SPKVDD1
AGND
AVDDLDO
AVDD
DGND
DPVDD
DCVDD

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2. PIN OUT AND DESCRIPTION

SPKROUTN
SPKROUTP

SPKLOUTN

SPKLOUTP
SPKVDD2

SPKVDD1

HPROUT
SPKGND

HPLOUT
SPKLDO

CPGND
CPBOT
48
47
46
45
44
43
42
41
40
39
38
37
GPIO1 1 36 CPVSSP
DACDAT1 2 35 CPTOP
ADCDAT1 3 34 CPVDD
BCLK1 4 ES8396 33 DACVRP
LRCK1 5 32 MONOUTN
SDA 6 31 MONOUTP
QFN 48
SCL 7 30 AVDDLDO
DPVDD 8 29 AVDD
DGND 9 28 AGND
DCVDD 10 27 VMID
MCLK 11 26 ADCVRP
GPIO2 12 25 MICN
13
14
15
16
17
18
19
20
21
22
23
24
BCLK2
LRCK2
DACDAT2
ADCDAT2
ROUT
LOUT
MICBIAS
MONOP
MONON
AINR
AINL
MICP

Name Type Description

MCLK DI Master clock
SDA DIO I2C data
SCL DI I2C clock
GPIO1 DIO GPIO (digital mic clock, ADC LRCK, etc)
GPIO2 DIO GPIO (digital mic clock, ADC LRCK, etc)

ADCDAT1/AD0 DIO I2S/PCM serial data out; Also used as I2C address
DACDAT1 DI I2S/PCM serial data in
LRCK1 DIO I2S/PCM left and right clock
BCLK1 DIO I2S/PCM bit clock
ADCDAT2 DIO I2S/PCM serial data out
DACDAT2 DI I2S/PCM serial data in
LRCK2 DIO I2S/PCM left and right clock
BCLK2 DIO I2S/PCM bit clock

AINL/JD1 AI Left analog line input or jack detect 1

AINR/JD2 AI Right analog line input or jack detect 2
MONOP AI Mono positive input or left analog line input
MONON AI Mono negative input or right analog line input
MICP AI Mic positive input or left analog line input
MICN/DMIC_SDA AI Mic negative input or right analog line input or digital mic data

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LOUT AO Left line out

ROUT/LOUTN AO Right line out or negative left line out
MONOUTP AO Mono positive output
MONOUTN AO Mono negative output
HPLOUT AO Left headphone out
HPROUT AO Right headphone out
SPKLOUTP AO Positive left speaker out
SPKLOUTN AO Negative left speaker out
SPKROUTP AO Positive right speaker out
SPKROUTN AO Negative right speaker out

CPVDD Charge pump power supply

CPGND Charge pump ground
CPTOP Charge pump capacitor top
CPBOT Charge pump capacitor bottom
CPVSSP Charge pump filtering

MICBIAS AO Mic bias

ADCVRP ADC reference filtering

DACVRP DAC reference filtering
VMID Common mode filtering

DCVDD Digital core power supply

DPVDD Digital IO power supply
DGND Digital ground
AVDD Analog power supply
AVDDLDO Analog LDO power supply
AGND Analog ground
SPKVDD1 Speaker driver power supply
SPKVDD2 Speaker driver power supply
SPKLDO Speaker driver LDO power supply
SPKGND Speaker driver ground

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3. TYPICAL APPLICATION CIRCUIT

SPKR_P

8OHMRSPEAKER

SPK_GND AGND DGND SPKR_N

1nF 1nF

SPKL_N
SPK_GND
8OHMLSPEAKER

1nF 1nF SPKL_P

VP_DUT HP_L
HP_R
SPK_GND
5
10K VSPK_DUT(+5V) 4
3
10uF 0.1uF 10uF 0.1uF 2
VP_DUT
I2CA0 10K 6
SPK_GND HPDETECT 1
Headphone
VP_DUT 10uF 0.1uF

49
48
47
46
45
44
43
42
41
40
39
38
37
SPK_GND SPK_GND AGND AGND MOUT_N
10K 10K 33

CPBOT
CPGND
SPKLDO
SPKGND

HPROUT
HPLOUT
SPKROUTP
SPKROUTN
SPKVDD2
SPKLOUTN
SPKVDD1
SPKLOUTP
THERMAL
Receiver earpiece
0.1uF 10uF 33
0.01uF 0.01uF
MOUT_P
I2C_SDA
1

1 36 0.1uF 10uF
I2C_SCL I2S1_ALRCK_GPIO 2 ADCLRCK/GPIO CPVSSP
35
I2S1_DACDAT 0 DACDAT1 CPTOP AGND
I2CA0 3 ADCDAT1 CPVDD 34 AGND
I2S1_ADCDAT 4 33 VCP_DUT(+1.8V)
VP_DUT(+1.8V- +3.3V) I2S1_BCLK 5 BCLK1 DACVRP
32
I2S1_LRCK LRCK1 MONOOUTN 0.1uF 10uF
6
7 SDA
SCL
ES8396 MONOOUTP
AVDDLDO
31
30 10uF 0.1uF AGND
10uF 0.1uF 8 29
9 DPVDD AVDD
28 VA_DUT(+3.3V)
DGND DGND AGND AGND AGND
10 DCVDD VMID 27
VD_DUT(+1.8V- +3.3V) 11 26
MCLK 12 MCLK ADCVRP
25 10uF 0.1uF 0.1uF 10uF
1

I2S2_ALRCK ADCLRCK2/GPIO MICN

0
10uF 0.1uF 10uF 0.1uF
DACDAT2
ADCDAT2

AGND
MICBIAS

MONON
MONOP
BCLK2
LRCK2

ROUT
LOUT

MICP
AINR
AINL
DGND AGND
13
14
15
16
17
18
19
20
21
22
23
24

4.7uF 0.1uF
I2S2_SCLK
I2S2_LRCK
I2S2_DACDAT
I2S2_ADCDAT AGND
4.7uF
ROUT_N
4.7uF
LOUT_P MICBIAS
4.7uF 2.2K
10K 10K MONOIN_P 10uF 0.1uF
4.7uF
MONOIN_N 4.7uF
AGND
4.7uF
AIN_R
4.7uF 4.7uF
AIN_L MICROPHONE
AGND
2.2K
MICN
MICP

AGND

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4. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports three types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc),
USB clocks (12/24 MHz), and an on-chip 22-bit fractional PLL clock.

According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.

5. MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard I2C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.

I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line
(SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1.
Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each
bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred
byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of
this interface can be up to 100 kbps.

Figure 1 Data Transfer for I2C Interface

A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It
is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x
equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by
the RW bit. The master can terminate the communication by generating a “stop” signal, which is
defined as a low-to-high transition at SDA while SCL is high.

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In I2C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register. There are no acknowledge bit after data to be written or read, this is the only
difference from the I2C protocol.

Table 1 Write Data to Register in I2C Interface Mode

Chip Address R/W Register Address Data to be written

001000 AD0 0 ACK RAM ACK DATA

Table 2 Read Data from Register in I2C Interface Mode

Chip Address R/W Register Address

001000 AD0 0 ACK RAM
Chip Address R/W Data to be read
001000 AD0 1 ACK Data

6. DIGITAL AUDIO INTERFACE

The device provides many formats of serial audio data interface to the input of the DAC or
output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are
I2S, left justified, right justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the
device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The
relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through
Figure 2 to Figure 6.
1 SCLK 1 SCLK
SDATA 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
MSB LSB MSB LSB

SCLK

LEFT CHANNEL
LRCK RIGHT CHANNEL

Figure 2 I2S Serial Audio Data Format Up To 24-bit

SDATA 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

SCLK

LRCK LEFT CHANNEL RIGHT CHANNEL

Figure 3 Left Justified Serial Audio Data Format Up To 24-bit

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SDATA 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

SCLK

LRCK LEFT CHANNEL RIGHT CHANNEL

Figure 4 Right Justified Serial Audio Data Format Up To 24-bit

Figure 5 DSP/PCM Mode A

Figure 6 DSP/PCM Mode B

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7. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Continuous operation at or beyond these conditions may permanently damage the device.

PARAMETER MIN MAX

Analog Supply Voltage Level -0.3V +5.0V
Digital Supply Voltage Level -0.3V +5.0V
Input Voltage Range DGND-0.3V DVDD+0.3V
Operating Temperature Range -40°C +85°C
Storage Temperature -65°C +150°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER MIN TYP MAX UNIT
Analog Supply Voltage Level 2.0 3.3 3.6 V
Analog Supply Voltage Level – Class D 4.5 5.0 5.5 V
Digital Supply Voltage Level 1.6 1.8 3.6 V

ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS

Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz,
MCLK/LRCK=256.

PARAMETER MIN TYP MAX UNIT

ADC Performance
Signal to Noise ratio (A-weigh) 85 95 98 dB
THD+N -88 -85 -75 dB
Channel Separation (1KHz) 80 85 90 dB
Interchannel Gain Mismatch 0.1 dB
Gain Error ±5 %
Filter Frequency Response – Single Speed
Passband 0 0.4535 Fs
Stopband 0.5465 Fs
Passband Ripple ±0.05 dB
Stopband Attenuation 50 dB
Filter Frequency Response – Double Speed
Passband 0 0.4167 Fs
Stopband 0.5833 Fs
Passband Ripple ±0.005 dB
Stopband Attenuation 50 dB
Analog Input
Full Scale Input Level AVDD/3.3 Vrms
Input Impedance 20 KΩ

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DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS

Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz,
MCLK/LRCK=256.

PARAMETER MIN TYP MAX UNIT

DAC Performance
Signal to Noise ratio (A-weigh) 83 96 98 dB
THD+N -85 -83 -75 dB
Channel Separation (1KHz) 80 85 90 dB
Interchannel Gain Mismatch 0.05 dB
Filter Frequency Response – Single Speed
Passband 0 0.4535 Fs
Stopband 0.5465 Fs
Passband Ripple ±0.05 dB
Stopband Attenuation 40 dB
Filter Frequency Response – Double Speed
Passband 0 0.4167 Fs
Stopband 0.5833 Fs
Passband Ripple ±0.005 dB
Stopband Attenuation 40 dB
De-emphasis Error at 1 KHz (Single Speed Mode Only)
Fs = 32KHz 0.002 dB
Fs = 44.1KHz 0.013
Fs = 48KHz 0.0009
Analog Output
Full Scale Output Level AVDD/3.3 Vrms

POWER CONSUMPTION CHARACTERISTICS

PARAMETER MIN TYP MAX UNIT
Normal Operation Mode
DVDD=1.8V, AVDD=1.8V: mW
Play back 7
Play back and record 16
DVDD=3.3V, AVDD=3.3V:
Play back 31
Play back and record 59
Power Down Mode
DVDD=1.8V, AVDD=1.8V TBD mW
DVDD=3.3V, AVDD=3.3V TBD

SERIAL AUDIO PORT SWITCHING SPECIFICATIONS

PARAMETER Symbol MIN MAX UNIT
MCLK frequency 51.2 MHz
MCLK duty cycle 40 60 %
LRCK frequency 200 KHz

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LRCK duty cycle 40 60 %

SCLK frequency 26 MHz
SCLK pulse width low TSCLKL 15 ns
SCLK Pulse width high TSCLKH 15 ns
SCLK falling to LRCK edge TSLR –10 10 ns
SCLK falling to SDOUT valid TSDO 0 ns
SDIN valid to SCLK rising setup time TSDIS 10 ns
SCLK rising to SDIN hold time TSDIH 10 ns

Figure 8 Serial Audio Port Timing

I2C SWITCHING SPECIFICATIONS

PARAMETER Symbol MIN MAX UNIT
SCL Clock Frequency FSCL 100 KHz
Bus Free Time Between Transmissions TTWID 4.7 us
Start Condition Hold Time TTWSTH 4.0 us
Clock Low time TTWCL 4.0 us
Clock High Time TTWCH 4.0 us
Setup Time for Repeated Start Condition TTWSTS 4.7 us
SDA Hold Time from SCL Falling TTWDH 0.1 us
SDA Setup time to SCL Rising TTWDS 100 ns
Rise Time of SCL TTWR 25 us
Fall Time SCL TTWF 25 ns

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SDA

TTWSTS TTWSTH TTWDH TTWDS TTWID

TTWCL

SCL
TTWCH
S P S
TTWF TTWR

Figure 10 I2C Timing

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8. PACKAGE

9. CORPORATE INFORMATION

Everest Semiconductor Co., Ltd.

苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021

Email: [email protected]

Revision 2.0 13 June 2014