Combinational Circuit

Minimization, Analysis and

Design EE203 Digital
Systems Design
Melike Gürcan, 042301166
Mustafa Doğukan Büyükaydın, 042201046
MEF University, Istanbul, Turkey

Section : 2.1
Date Performed: 25.10.2024
Submission Date: 1.11.2024

Abstract
This report presents the results and analysis of the 1-2 laboratory session for
the EE203 Digital Systems Design course. The emphasis is placed on the
interpretation of results and their alignment with theoretical expectations. It also
highlights the critical steps taken to achieve the objectives, including schematics,
screenshots, and waveforms where applicable. Hardcopy reports without proper
electronic submission or lacking signatures will not be accepted.

1 Introduction
The purpose of this laboratory session was to design and evaluate combinational logic
circuits, with a specific focus on minimizing the use of gates. The session focused on
understanding combinational logic optimization and applying it to combinational logic
principles and applying them to simplification tasks. This report includes an explanation
of the procedures followed, key findings, and a critical analysis of the outcomes.

2 Theory
This section provides a theoretical background necessary to understand the lab
objectives and tasks. The pre-lab calculations and relevant proofs are included:

Pre-lab2.1

• Insert pre-lab calculations or theory here.

TheBoolean expression abd’ + bcd’ in Sum of Products (SOP) form. SOP form means
that the expression is a sum (OR) of multiple products (AND) terms. Each term
represents a condition under which the output will be 1.

2.3

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 A B C D Y

0 0 0 X 0

0 0 1 X 0

0 1 1 0 1

0 1 1 X 0

1 1 0 0 1

1 0 1 X 0

1 1 1 0 1

1 1 1 X 0

The truth table provided describes the behavior of a Boolean function with inputs A, B,
C, and D, and output Y. X in the D column represents a "don't care" condition. This means
that the value of D (0 or 1) does not affect the output Y for those specific rows.

B1B0
B3B2 00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 X X X X
10 1 1 X X

A Karnaugh map (K-map) is a visual tool used to simplify Boolean algebra expressions.
It provides a straightforward way to minimize logic expressions, which is particularly
useful in digital circuit design. K-maps organize truth table values into a grid format that
makes it easier to identify patterns and groups, enabling quick simplification of complex
expressions.Using X values allows for more flexibility in grouping cells because you can
treat X as either 0 or 1—whichever option allows for larger groups and simpler
expressions. This flexibility helps to further minimize the Boolean expression. So in the
end we have the optimum result.

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 Each module and its interactions are explained, and the expected behavior is
discussed. Schematics for each module are presented to illustrate the system design:

3 Experimental Results
The experimental setup is briefly described, and key configurations are displayed using
pictures or diagrams:

3.1

3
As can be seen in the photos, we first tested the circuit on the logisim and then applied it
to the board. The theoretical values we tested on the logisim were found to be correct on
the board. In this circuit and, or, inverter gates were used.
This circuit appears to be a 2:1 Multiplexer circuit. In such circuits, the value of one of
the inputs A and B is transferred to the output according to the selector input S.

If S=0, the output is equal to the input A.

If S=1, the output is equal to input B.
A B S Output
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

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3.2

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As can be seen in my logisim, the circuit that needs to be created using MUX has been
created. 4 ICs were implemented as you can see in the photo.

Inputs A and B are directly connected to some MUX inputs.

Additionally, the A input has a NOT gate applied to it, producing an inverted signal that
feeds into one of the MUX inputs.
The first MUX gate selects between the D input and the inverted A signal.
The second MUX gate selects between the B input and a constant 0 signal.
The third and final MUX gate takes the outputs of the previous two MUX gates as inputs
and produces the final output.
The final MUX gate determines the output of the circuit based on the signals from the
first two MUX gates.

A B C D output
0 0 0 X 0
0 0 1 X 0
0 1 1 0 1
0 1 1 X 0
1 1 0 0 1
1 0 1 X 0
1 1 1 0 1
6
1 1 1 X 0
3.3

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This circuit appears to implement a specific Boolean logic function using AND, OR, and
NOT gates. It takes four inputs: B3B3B3, B2B2B2, B1B1B1, and B0B0B0 and generates a
single output.The outputs of these AND gates are fed into two OR gates, which combine
the expressions.The final OR gate produces the circuit's output, which is a Boolean
expression combining all the previous terms.
B3 B2 B1 B0 A B C D E F G
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1

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 0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

EE203 Digital Systems Design Lab Report

Figure 1: Schematic of [module name].

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 Figure 2: Experimental Setup.
Input Output
[Input Case 1] [Output 1]
[Input Case 2] [Output 2]
Table 1: Input and Output Results.

The input cases and their corresponding outputs are summarized in the following
table:
The results were analyzed based on the expected theoretical outcomes, and the
accuracy of the tests is discussed.
EE203 Digital Systems Design Lab Report

4 Discussion
• Please discuss the results of the experiments. Comment on the external
factors that occur during the experiment. Give examples of the real-life use of
the models you implemented in the experiment:

The experiments demonstrated the efficiency of different simplification techniques

in achieving efficient combinational logic circuit designs.

There are several external factors that are affect the experimental results. Precise
wiring layout is essential to avoid wiring overlap, particularly in complex circuit
boards.

The optimization principles used here are fundamental for designing low-power,
high-performance circuits in mobile devices and embedded systems where efficiency
is very important. Binary to 7-segment decoders form the basis of display systems
such as digital clocks, calculators and instrument panels where numerical outputs
are required.

• A bill of materials (sometimes bill of material, BOM or associated list) is a list

of the raw materials, sub-assemblies, intermediate assemblies, sub
components, extra parts and the quantities of each needed to

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 manufacture/implement a certain functionality or a product. Generate and
discuss the BOM for this laboratory. Calculate the total cost for each
experiment. You can use the prices you find on the internet for this:

BOM shows the components required to implement and test circuits on a

breadboard. If the first circuit is calculated, the total cost for the 2:1 multiplexer
designed by using logical gates is as follows: 1 AND Gate IC, 1 OR Gate IC, 1 NOT Gate
IC, 1 Breadboard, Jumper Cables.

If the second circuit is calculated, the total cost for the 3 2:1 multiplexers is as
follows: 3 MUX IC 74157S, 1 NOT Gate IC, 1 Breadboard, Jumper Cables.

If the third circuit is calculated, the total cost for the binary to 7-segment decoder is
as follows: 1 AND Gate IC, 1 OR Gate IC, 1 NOT Gate IC, 1 Breadboard, Jumper Cables.

• Please discuss the IC/gate delay. How can we measure it? Spell out the
equipment you use in your measurements. Also can this delay cause errors in
digital circuits? If they can, in what ways they may be detrimental:

The IC or gate delay of a signal path is the time it takes between the change in input
and the change in output for that signal. In digital circuits, this type of delay is
crucial, it affects the overall speed and performance of the system.

If gate delay not managed properly, it can result in logic circuits that run too slowly
to meet their requirements, or that fail altogether. If the operating frequency is too
high relative to the circuit's delay, the input may change before the previous output
has settled, which can lead to unexpected behavior. This can cause glitches, errors, or
failures in the circuit.

Using faster logic gates with lower propagation delay times can improve circuit
performance, though this often comes at the cost of higher power consumption.
Additionally, optimizing the circuit design to minimize the number of logic gates can
be achieved through techniques like Karnaugh map (K-map) minimization.

5 Labor Authentication
The following table details the labor distribution among group members:
Task Group Member
Responsible
Prelab, Melike Gürcan
Introduction,
Discussion
Prelab, Mustafa Doğukan
Theory, Büyükaydın
Experimental
Results
Table 2: Labor Distribution.

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 All group members confirm the completion and accuracy of the work claimed by
signing below:

[Signature of Group Member 1] [Signature of Group Member 2]

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