E SI G

NS ISL6261A
®
W D
E RT
D F O R N EN T PA
NDE CE M
C O M M E D R E P LA   Data Sheet November 5, 2009 FN6354.3
RE DE 4C
NOT OMMEN ISL6288
R EC

Single-Phase Core Regulator for IMVP-6® Features

Mobile CPUs • Precision single-phase CORE voltage regulator
The ISL6261A is a single-phase buck regulator - 0.5% system accuracy over temperature
implementing lntel® IMVP-6® protocol, with embedded gate - Enhanced load line accuracy
drivers. lntel® Mobile Voltage Positioning (IMVP) is a smart
• Internal gate driver with 2A driving capability
voltage regulation technology effectively reducing power
dissipation in lntel® Pentium processors. • Microprocessor voltage identification input
- 7-Bit VID input
The heart of the ISL6261A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with - 0.300V to 1.500V in 12.5mV steps
the traditional multi-phase buck regulator, the R3 - Support VID change on-the-fly
Technology™ has faster transient response. This is due to • Multiple current sensing schemes supported
the R3 modulator commanding variable switching frequency - Lossless inductor DCR current sensing
during a load transient. - Precision resistive current sensing
The ISL6261A provides three operation modes: the • Thermal monitor
Continuous Conduction Mode (CCM), the Diode Emulation
Mode (DEM) and the Enhanced Diode Emulation Mode • Power monitor indicating CPU instantaneous power
(EDEM). To boost battery life, the ISL6261A changes its • User programmable switching frequency
operation mode based on CPU mode signals DPRSLRVR
• Differential remote voltage sensing at CPU die
and DPRSTP#, and the FDE pin setting, to maximize the
efficiency. In CPU active mode, the ISL6261A commands • Overvoltage, undervoltage, and overcurrent protection
the CCM operation. When the CPU enters deeper sleep • Pb-free (RoHS compliant)
mode, the ISL6261A enables the DEM to maximize the
efficiency at light load. Asserting the FDE pin of the Ordering Information
ISL6261A in CPU deeper sleep mode will enable the EDEM
TEMP.
to further decrease the switching frequency at light load and PART NUMBER PART RANGE PACKAGE PKG.
increase the regulator efficiency. (Notes 2, 3) MARKING (°C) (Pb-Free) DWG. #
A 7-bit Digital-to-Analog Converter (DAC) allows dynamic ISL6261ACRZ ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
adjustment of the core output voltage from 0.300V to 1.500V. ISL6261ACRZ-T* ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
The ISL6261A has 0.5% system voltage accuracy over (Note 1) Tape and Reel
temperature.
ISL6261AIRZ 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6
A unity-gain differential amplifier provides remote voltage ISL6261AIRZ-T* 6261A IRZ -40 to +100 40 Ld 6x6 QFN L40.6x6
sensing at the CPU die. This allows the voltage on the CPU (Note 1) Tape and Reel
die to be accurately measured and regulated per lntel®
NOTES:
IMVP-6 specification. Current sensing can be implemented
1. Please refer to TB347 for details on reel specifications.
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor 2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
network will thermally compensates the gain and the time 100% matte tin plate plus anneal (e3 termination finish, which is
constant variations caused by the inductor DCR change. RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
The ISL6261A provides the power monitor function through Pb-free peak reflow temperatures that meet or exceed the Pb-free
the PMON pin. PMON output is a high-bandwidth analog requirements of IPC/JEDEC J STD-020.
voltage signal representing the CPU instantaneous power. 3. For Moisture Sensitivity Level (MSL), please see device information
The power monitor function can be used by the system to page for ISL6261A. For more information on MSL please see
optimize the overall power consumption, extending battery techbrief TB363.
run time.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007, 2009. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
 ISL6261A

Pinout
ISL6261A
(40 LD QFN)
TOP VIEW

DPRSLPVR
DPRSTP#
CLK_EN
PGOOD

VR_ON

VID6

VID5

VID4

VID3
3V3
40 39 38 37 36 35 34 33 32 31

FDE 1 30 VID2

PMON 2 29 VID1

RBIAS 3 28 VID0

VR_TT# 4 27 VCCP

NTC 5 26 LGATE
GND PAD
(BOTTOM)
SOFT 6 25 VSSP

OCSET 7 24 PHASE

VW 8 23 UGATE

COMP 9 22 BOOT

FB 10 21 NC

11 12 13 14 15 16 17 18 19 20
VSUM
DROOP

VO

VSS
VDIFF

VSEN

RTN

DFB

VIN

VDD

2 FN6354.3
November 5, 2009
 ISL6261A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V QFN Package. . . . . . . . . . . . . . . . . . . . 33 6
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC) Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns) Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) http://www.intersil.com/pbfree/Pb-FreeReflow.asp
UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
Recommended Operating Conditions
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
. . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V Ambient Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +100°C.
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
INPUT POWER SUPPLY
+5V Supply Current IVDD VR_ON = 3.3V - 3.1 3.6 mA
VR_ON = 0V - - 1 µA
+3.3V Supply Current I3V3 No load on CLK_EN# pin - - 1 µA
Battery Supply Current at VIN Pin IVIN VR_ON = 0, VIN = 25V - - 1 µA
POR (Power-On Reset) Threshold PORr VDD rising - 4.35 4.5 V
PORf VDD falling 3.85 4.1 - V
SYSTEM AND REFERENCES
System Accuracy %Error No load, close loop, active mode, -0.5 - 0.5 %
(Vcc_core) TA =-10°C to +100°C, VID = 0.75V to 1.5V
ISL6261ACRZ
VID = 0.5V to 0.7375V -8 - 8 mV
VID = 0.3V to 0.4875V -15 - 15 mV
%Error No load, close loop, active mode, -0.8 - 0.8 %
(Vcc_core) VID = 0.75V to 1.5V
ISL6261AIRZ
VID = 0.5V to 0.7375V -10 - 10 mV
VID = 0.3V to 0.4875V -18 - 18 mV
RBIAS Voltage RRBIAS RRBIAS = 147kΩ 1.45 1.47 1.49 V
Boot Voltage VBOOT 1.188 1.2 1.212 V
Maximum Output Voltage VCC_CORE VID = [0000000] - 1.5 - V
(max)
Minimum Output Voltage VCC_CORE VID = [1100000] - 0.3 - V
(min)
VID Off State VID = [1111111] - 0.0 - V
CHANNEL FREQUENCY
Nominal Channel Frequency fSW RFSET = 7kΩ, Vcomp = 2V 318 333 348 kHz

3 FN6354.3
November 5, 2009
 ISL6261A

Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
Adjustment Range 200 - 500 kHz
AMPLIFIERS
Droop Amplifier Offset -0.3 - 0.3 mV
Error Amp DC Gain (Note 6) AV0 - 90 - dB
Error Amp Gain-Bandwidth Product GBW CL = 20pF - 18 - MHz
(Note 6)
Error Amp Slew Rate (Note 6) SR CL = 20pF - 5.0 - V/µs
FB Input Current IIN(FB) - 10 150 nA
SOFT-START CURRENT
Soft-start Current ISS -47 -42 -37 µA
Soft Geyserville Current IGV |SOFT - REF|>100mV ±180 ±205 ±230 µA
Soft Deeper Sleep Entry Current IC4 DPRSLPVR = 3.3V -46 -41 -36 µA
Soft Deeper Sleep Exit Current IC4EA DPRSLPVR = 3.3V 36 41 46 µA
Soft Deeper Sleep Exit Current IC4EB DPRSLPVR = 0V 175 200 225 µA
POWER MONITOR
PMON Output Voltage Range VPMON VSEN = 1.2V, VDROOP - VO = 40mV 1.638 1.680 1.722 V
VSEN = 1V, VDROOP - VO = 10mV 0.308 0.350 0.392 V
PMON Maximum Voltage VPMONMAX 2.8 3.0 - V
PMON Sourcing Current ISC_PMON VSEN = 1V, VDROOP - VO = 25mV 2 - - mA
PMON Sinking Current ISK_PMON VSEN = 1V, VDROOP - VO = 25mV 2 - - mA
Maximum Current Sinking Capability PMON/250Ω PMON/180Ω PMON A
/130Ω
PMON Impedance ZPMON When PMON current is within its - 7 - Ω
ourcing/sinking current range (Note 6)
GATE DRIVER DRIVING CAPABILITY (Note 6)
UGATE Source Resistance RSRC(UGATE) 500mA source current - 1 1.5 Ω
UGATE Source Current ISRC(UGATE) VUGATE_PHASE = 2.5V - 2 - A
UGATE Sink Resistance RSNK(UGATE) 500mA sink current - 1 1.5 Ω
UGATE Sink Current ISNK(UGATE) VUGATE_PHASE = 2.5V - 2 - A
LGATE Source Resistance RSRC(LGATE) 500mA source current - 1 1.5 Ω
LGATE Source Current ISRC(LGATE) VLGATE = 2.5V - 2 - A
LGATE Sink Resistance RSNK(LGATE) 500mA sink current - 0.5 0.9 Ω
LGATE Sink Current ISNK(LGATE) VLGATE = 2.5V - 4 - A
UGATE to PHASE Resistance RP(UGATE) - 1.1 - kΩ
GATE DRIVER SWITCHING TIMING (Refer to “Gate Driver Timing Diagram” on page 6)
UGATE Turn-on Propagation Delay tPDHU TA = -10°C to +100°C, 20 30 44 ns
ISL6261ACRZ PVCC = 5V, output unloaded
tPDHU PVCC = 5V, output unloaded 18 30 44 ns
ISL6261AIRZ
LGATE Turn-on Propagation Delay tPDHL TA = -10°C to +100°C, 7 15 30 ns
ISL6261ACRZ PVCC = 5V, output unloaded
tPDHL PVCC = 5V, output unloaded 5 15 30 ns
ISL6261AIRZ
BOOTSTRAP DIODE
Forward Voltage VDDP = 5V, forward bias current = 2mA 0.43 0.58 0.72 V

4 FN6354.3
November 5, 2009
 ISL6261A

Electrical Specifications VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
Leakage VR = 16V - - 1 μA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage VOL IPGOOD = 4mA - 0.11 0.4 V
PGOOD Leakage Current IOH PGOOD = 3.3V -1 - 1 µA
PGOOD Delay tpgd CLK_EN# low to PGOOD high 5.5 6.8 8.1 ms
Overvoltage Threshold OVH VO rising above setpoint > 1ms 155 195 235 mV
Severe Overvoltage Threshold OVHS VO rising above setpoint > 0.5µs 1.675 1.7 1.725 V
OCSET Reference Current I(RBIAS) = 10µA 9.8 10 10.2 µA
OC Threshold Offset DROOP rising above OCSET > 120µs -3.5 - 3.5 mV
Undervoltage Threshold UVf VO below set point for > 1ms -360 -300 -240 mV
(VDIFF-SOFT)
LOGIC THRESHOLDS
VR_ON and DPRSLPVR Input Low VIL(3.3V) - - 1 V
VR_ON and DPRSLPVR Input High VIH(3.3V) 2.3 - - V
Leakage Current on VR_ON IIL Logic input is low -1 0 - μA
IIH Logic input is high - 0 1 μA
Leakage Current on DPRSLPVR IIL_DPRSLP DPRSLPVR logic input is low -1 0 - μA
IIH_DPRSLP DPRSLPVR logic input is high - 0.45 1 μA
DAC(VID0-VID6), PSI# and VIL(1.0V) - - 0.3 V
DPRSTP# Input Low
DAC(VID0-VID6), PSI# and VIH(1.0V) 0.7 - - V
DPRSTP# Input High
Leakage Current of DAC(VID0-VID6) IIL DPRSLPVR logic input is low -1 0 - μA
and DPRSTP#
IIH DPRSLPVR logic input is high - 0.45 1 μA
THERMAL MONITOR
NTC Source Current NTC = 1.3 V 53 60 67 µA
Over-temperature Threshold V(NTC) falling 1.17 1.2 1.25 V
VR_TT# Low Output Resistance RTT I = 20mA - 5 9 Ω
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage VOH 3V3 = 3.3V, I = -4mA 2.9 3.1 - V
CLK_EN# Low Output Voltage VOL ICLK_EN# = 4mA - 0.18 0.4 V
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.

5 FN6354.3
November 5, 2009
 ISL6261A

Gate Driver Timing Diagram

PWM

tPDHU tFU
tRU

UGATE 1V

LGATE 1V

tRL
tFL tPDHL

6 FN6354.3
November 5, 2009
 ISL6261A

Functional Pin Description

DPRSLPVR
DPRSTP#
CLK_EN
PGOOD

VR_ON

VID6

VID5

VID4

VID3
3V3
40 39 38 37 36 35 34 33 32 31

FDE 1 30 VID2

PMON 2 29 VID1

RBIAS 3 28 VID0

VR_TT# 4 27 VCCP

NTC 5 26 LGATE
GND PAD
(BOTTOM)
SOFT 6 25 VSSP

OCSET 7 24 PHASE

VW 8 23 UGATE

COMP 9 22 BOOT

FB 10 21 NC

11 12 13 14 15 16 17 18 19 20
VDIFF

VSEN

RTN

DFB

VSUM

VIN

VDD
VO

VSS
DROOP

FDE VW
Forced diode emulation enable signal. Logic high of FDE A resistor from this pin to COMP programs the switching
with logic low of DPRSTP# forces the ISL6261A to operate frequency (eg. 6.81k = 300kHz).
in diode emulation mode with an increased VW-COMP
COMP
voltage window.
The output of the error amplifier.
PMON
FB
Analog voltage output pin. The voltage potential on this pin
indicates the power delivered to the output. The inverting input of the error amplifier.

RBIAS VDIFF
A 147K resistor to VSS sets internal current reference. The output of the differential amplifier.

VR_TT# VSEN
Thermal overload output indicator with open-drain output. Remote core voltage sense input.
Over-temperature pull-down resistance is 10. RTN
NTC Remote core voltage sense return.
Thermistor input to VR_TT# circuit and a 60µA current DROOP
source is connected internally to this pin.
The output of the droop amplifier. DROOP-VO voltage is the
SOFT droop voltage.
A capacitor from this pin to GND pin sets the maximum slew DFB
rate of the output voltage. The SOFT pin is the non-inverting
The inverting input of the droop amplifier.
input of the error amplifier.
VO
OCSET
An input to the IC that reports the local output voltage.
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.

7 FN6354.3
November 5, 2009
 ISL6261A

VSUM VC24CP
This pin is connected to one terminal of the capacitor in the 5V power supply for the gate driver.
current sensing R-C network.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VIN VID input with VID0 as the least significant bit (LSB) and
Power stage input voltage. It is used for input voltage feed VID6 as the most significant bit (MSB).
forward to improve the input line transient performance.
VR_ON
VSS VR enable pin. A logic high signal on this pin enables the
Signal ground. Connect to controller local ground. regulator.

VDD DPRSLPVR
5V control power supply. Deeper sleep enable signal. A logic high indicates that the
microprocessor is in Deeper Sleep Mode and also indicates
NC
a slow Vo slew rate with 41μA discharging or charging the
Not connected. Ground this pin in the practical layout. SOFT cap.
BOOT DPRSTP#
Upper gate driver supply voltage. An internal bootstrap diode Deeper sleep slow wake up signal. A logic low signal on this
is connected to the VCCP pin. pin indicates that the microprocessor is in Deeper Sleep
UGATE Mode.

The upper-side MOSFET gate signal. CLK_EN#

PHASE Digital output for system PLL clock. Goes active 13 clock
cycles after Vcore is within 20mV of the boot voltage.
The phase node. This pin should connect to the source of
upper MOSFET. 3V3
VSSP 3.3V supply voltage for CLK_EN#.

The return path of the lower gate driver. PGOOD

LGATE Power good open-drain output. Needs to be pulled up
externally by a 680 resistor to VCCP or 1.9k to 3.3V.
The lower-side MOSFET gate signal.

8 FN6354.3
November 5, 2009
 Function Block Diagram
RBIAS VR_ON FDE DPRSLPVR DPRSTP# CLK_EN# PGOOD 3V3 VIN VDD VCCP

VID0
VIN VCCP
MODE CONTROL PGOOD MONITOR AND LOGIC
VID1
60µA
VID2 FLT PGOOD

VID3 DAC SOFT

9

FAULT AND PGOOD LOGIC

VID4

VID5 VO
1.22V
VID6 10µA

OCSET OC VCCP

VSUM

DROOP
OC VIN VSOFT FLT

ISL6261A
DFB

DROOP DRIVER
1 E/A MODULATOR LOGIC
VCCP

VO

1 Mupti-plier

VW

VO VSEN RTN PMON VDIFF SOFT FB COMP VW VSS

FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261A

November 5, 2009
FN6354.3
 ISL6261A

Simplified Application Circuit for DCR Current Sensing

V V V
+3.3 +5 in

R4

C4

3V3 VDD VCCP

R5
RBIAS VIN
R6 C8
NTC
C5 UGATE
SOFT
BOOT
L
C6 o V
VR_TT# VR_TT# o
PHASE
VID<0:6> VIDs C
o
DPRSTP# DPRSTP#

DPRSLPVR DPRSLPVR
LGATE
FDE

PMON PMON VSSP

CLK_ENABLE# CLK_EN#

VR_ON VR_ON R8
VSUM
IMVP6_PWRGD PGOOD
R9
VCC-SENSE VSEN C9
NTC
Network
VSS-SENSE RTN
R7 VO
ISL6261A
C7 R10
C3 R11
VW
OCSET
R2 C2 C10
COMP DFB

FB R12

R3 C1

VDIFF DROOP
R1
VSS

FIGURE 2. ISL6261A-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING

10 FN6354.3
November 5, 2009
 ISL6261A

Simplified Application Circuit for Resistive Current Sensing

V V V
+3.3 +5 in

R4

C4

3V3 VDD VCCP

R5
RBIAS VIN
R6 C8
NTC
C5 UGATE
SOFT
BOOT
L R
C6 o V
VR_TT# VR_TT# sen o
PHASE
VID<0:6> VIDs C
o
DPRSTP# DPRSTP#

DPRSLPVR DPRSLPVR
LGATE
FDE

PMON PMON VSSP

CLK_ENABLE# CLK_EN#

VR_ON VR_ON R8
VSUM
IMVP6_PWRGD PGOOD

VCC-SENSE VSEN C9

VSS-SENSE RTN
R7 VO
ISL6261A
C7 R10
C3 R11
VW
OCSET
R2 C2 C10
COMP DFB

FB R12

R3 C1

VDIFF DROOP
R1
VSS

FIGURE 3. ISL6261A-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING

11 FN6354.3
November 5, 2009
 ISL6261A

Theory of Operation
The ISL6261A is a single-phase regulator implementing
Intel® IMVP-6® protocol and includes an integrated gate VDD
driver for reduced system cost and board area. The
ISL6261A IMVP-6® solution provides optimum steady state VR_ON 10mV/µs
and transient performance for microprocessor core voltage 100µs 20mV
regulation applications up to 25A. Implementation of Diode Vboot

Emulation Mode (DEM) operation further enhances system

efficiency. SOFT &VO 13xTs
2mV/µs
The heart of the ISL6261A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. The R3™
CLK_EN#
modulator combines the best features of fixed frequency and
hysteretic PWM controllers while eliminating many of their ~7ms
shortcomings. The ISL6261A modulator internally
IMVP-VI PGOOD
synthesizes an analog of the inductor ripple current and
uses hysteretic comparators on those signals to establish FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
PWM pulses. Operating on the large-amplitude and noise- CAPACITOR
free synthesized signals allows the ISL6261A to achieve
A true differential amplifier remotely senses the core voltage
lower output ripple and lower phase jitter than either
to precisely control the voltage at the microprocessor die.
conventional hysteretic or fixed frequency PWM controllers.
VSEN and RTN pins are the inputs to the differential
Unlike conventional hysteretic converters, the ISL6261A has
amplifier.
an error amplifier that allows the controller to maintain 0.5%
voltage regulation accuracy throughout the VID range from As the load current increases from zero, the output voltage
0.75V to 1.5V. droops from the VID value proportionally to achieve the
IMVP-6® load line. The ISL6261A can sense the inductor
The hysteretic window voltage is with respect to the error
current through the intrinsic series resistance of the
amplifier output. Therefore the load current transient results
inductors, as shown in Figure 2, or through a precise resistor
in increased switching frequency, which gives the R3™
in series with the inductor, as shown in Figure 3. The
regulator a faster response than conventional fixed
inductor current information is fed to the VSUM pin, which is
frequency PWM regulators.
the non-inverting input to the droop amplifier. The DROOP
Start-up Timing pin is the output of the droop amplifier, and DROOP-VO
With the controller’s VDD pin voltage above the POR voltage is a high-bandwidth analog representation of the
threshold, the start-up sequence begins when VR_ON inductor current. This voltage is used as an input to a
exceeds the 3.3V logic HIGH threshold. In approximately differential amplifier to achieve the IMVP-6® load line, and
100μs, SOFT and VO start ramping to the boot voltage of also as the input to the overcurrent protection circuit.
1.2V. At start-up, the regulator always operates in The PMON pin is the power monitor output. The voltage
Continuous Current Mode (CCM), regardless of the control potential on this pin (VPMON) is given by VPMON = 35x(VSEN-
signals. During this interval, the SOFT cap is charged by a VRTN)x(VDROOP-VO). Since VSEN-VRTN is the CPU voltage
41μA current source. If the SOFT capacitor is 20nF, the and VDROOP-VO represents the inductor current, VPMON is
SOFT ramp will be 2mV/µs for a soft-start time of 600µs. an analog voltage indicating the power consumed by the
Once VO is within 20mV of the boot voltage the ISL6261A CPU. VPMON has high bandwidth so it represents the
will count 13 clock cycles, then pull CLK_EN# low, and instantaneous power including the pulsation caused inductor
charge/discharge the SOFT cap with approximately 200µA, current switching ripple. The maximum available VPMON is
therefore VO slews at 10mV/µs to the voltage set by the VID approximately 3V.
pins. In approximately 7ms, PGOOD is asserted HIGH.
Figure 4 shows typical start-up timing. When using inductor DCR current sensing, an NTC
thermistor is used to compensate the positive temperature
Static Operation coefficient of the copper winding resistance to maintain the
After the start-up sequence, the output voltage will be load-line accuracy.
regulated to the value set by the VID inputs per Table 1,
The switching frequency of the ISL6261A controller is set by
which is presented in the lntel® IMVP-6® specification. The
the resistor RFSET between pins VW and COMP, as shown in
ISL6261A regulates the output voltage with ±0.5% accuracy
Figures 2 and 3.
over the range of 0.7V to 1.5V.

12 FN6354.3
November 5, 2009
 ISL6261A

TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)

0 0 0 0 0 0 0 1.5000 0 1 0 1 0 1 0 0.9750

0 0 0 0 0 0 1 1.4875 0 1 0 1 0 1 1 0.9625

0 0 0 0 0 1 0 1.4750 0 1 0 1 1 0 0 0.9500

0 0 0 0 0 1 1 1.4625 0 1 0 1 1 0 1 0.9375

0 0 0 0 1 0 0 1.4500 0 1 0 1 1 1 0 0.9250

0 0 0 0 1 0 1 1.4375 0 1 0 1 1 1 1 0.9125

0 0 0 0 1 1 0 1.4250 0 1 1 0 0 0 0 0.9000

0 0 0 0 1 1 1 1.4125 0 1 1 0 0 0 1 0.8875

0 0 0 1 0 0 0 1.4000 0 1 1 0 0 1 0 0.8750

0 0 0 1 0 0 1 1.3875 0 1 1 0 0 1 1 0.8625

0 0 0 1 0 1 0 1.3750 0 1 1 0 1 0 0 0.8500

0 0 0 1 0 1 1 1.3625 0 1 1 0 1 0 1 0.8375

0 0 0 1 1 0 0 1.3500 0 1 1 0 1 1 0 0.8250

0 0 0 1 1 0 1 1.3375 0 1 1 0 1 1 1 0.8125

0 0 0 1 1 1 0 1.3250 0 1 1 1 0 0 0 0.8000

0 0 0 1 1 1 1 1.3125 0 1 1 1 0 0 1 0.7875

0 0 1 0 0 0 0 1.3000 0 1 1 1 0 1 0 0.7750

0 0 1 0 0 0 1 1.2875 0 1 1 1 0 1 1 0.7625

0 0 1 0 0 1 0 1.2750 0 1 1 1 1 0 0 0.7500

0 0 1 0 0 1 1 1.2625 0 1 1 1 1 0 1 0.7375

0 0 1 0 1 0 0 1.2500 0 1 1 1 1 1 0 0.7250

0 0 1 0 1 0 1 1.2375 0 1 1 1 1 1 1 0.7125

0 0 1 0 1 1 0 1.2250 1 0 0 0 0 0 0 0.7000

0 0 1 0 1 1 1 1.2125 1 0 0 0 0 0 1 0.6875

0 0 1 1 0 0 0 1.2000 1 0 0 0 0 1 0 0.6750

0 0 1 1 0 0 1 1.1875 1 0 0 0 0 1 1 0.6625

0 0 1 1 0 1 0 1.1750 1 0 0 0 1 0 0 0.6500

0 0 1 1 0 1 1 1.1625 1 0 0 0 1 0 1 0.6375

0 0 1 1 1 0 0 1.1500 1 0 0 0 1 1 0 0.6250

0 0 1 1 1 0 1 1.1375 1 0 0 0 1 1 1 0.6125

0 0 1 1 1 1 0 1.1250 1 0 0 1 0 0 0 0.6000

0 0 1 1 1 1 1 1.1125 1 0 0 1 0 0 1 0.5875

0 1 0 0 0 0 0 1.1000 1 0 0 1 0 1 0 0.5750

0 1 0 0 0 0 1 1.0875 1 0 0 1 0 1 1 0.5625

0 1 0 0 0 1 0 1.0750 1 0 0 1 1 0 0 0.5500

0 1 0 0 0 1 1 1.0625 1 0 0 1 1 0 1 0.5375

0 1 0 0 1 0 0 1.0500 1 0 0 1 1 1 0 0.5250

0 1 0 0 1 0 1 1.0375 1 0 0 1 1 1 1 0.5125

0 1 0 0 1 1 0 1.0250 1 0 1 0 0 0 0 0.5000

0 1 0 0 1 1 1 1.0125 1 0 1 0 0 0 1 0.4875

0 1 0 1 0 0 0 1.0000 1 0 1 0 0 1 0 0.4750

0 1 0 1 0 0 1 0.9875 1 0 1 0 0 1 1 0.4625

13 FN6354.3
November 5, 2009
 ISL6261A

TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued) (Continued)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)
1 0 1 0 1 0 0 0.4500 1 1 0 1 0 1 1 0.1625
1 0 1 0 1 0 1 0.4375 1 1 0 1 1 0 0 0.1500
1 0 1 0 1 1 0 0.4250 1 1 0 1 1 0 1 0.1375
1 0 1 0 1 1 1 0.4125 1 1 0 1 1 1 0 0.1250
1 0 1 1 0 0 0 0.4000 1 1 0 1 1 1 1 0.1125
1 0 1 1 0 0 1 0.3875 1 1 1 0 0 0 0 0.1000
1 0 1 1 0 1 0 0.3750 1 1 1 0 0 0 1 0.0875
1 0 1 1 0 1 1 0.3625 1 1 1 0 0 1 0 0.0750
1 0 1 1 1 0 0 0.3500 1 1 1 0 0 1 1 0.0625
1 0 1 1 1 0 1 0.3375 1 1 1 0 1 0 0 0.0500
1 0 1 1 1 1 0 0.3250 1 1 1 0 1 0 1 0.0375
1 0 1 1 1 1 1 0.3125 1 1 1 0 1 1 0 0.0250
1 1 0 0 0 0 0 0.3000 1 1 1 0 1 1 1 0.0125
1 1 0 0 0 0 1 0.2875 1 1 1 1 0 0 0 0.0000
1 1 0 0 0 1 0 0.2750 1 1 1 1 0 0 1 0.0000
1 1 0 0 0 1 1 0.2625 1 1 1 1 0 1 0 0.0000
1 1 0 0 1 0 0 0.2500 1 1 1 1 0 1 1 0.0000
1 1 0 0 1 0 1 0.2375 1 1 1 1 1 0 0 0.0000
1 1 0 0 1 1 0 0.2250 1 1 1 1 1 0 1 0.0000
1 1 0 0 1 1 1 0.2125 1 1 1 1 1 1 0 0.0000
1 1 0 1 0 0 0 0.2000 1 1 1 1 1 1 1 0.0000
1 1 0 1 0 0 1 0.1875
1 1 0 1 0 1 0 0.1750

TABLE 2. ISL6261A OPERATING CONFIGURATIONS

VW-COMP VOLTAGE
DPRSTP# PHASE DETECTOR HISTORY FDE DPRSLPVR OPERATIONAL MODE WINDOW INCREASE

0 x 0 0 CCM 0%

<3 consecutive PWM with PHASE>0V 1 DEM

1 0 +20%

Three consecutive PWM with PHASE>0V 0 1

1 0 EDEM +40%

1 x x x CCM 0%

14 FN6354.3
November 5, 2009
 ISL6261A

High Efficiency Operation Mode based on load current. Light-load efficiency is increased in
The operational modes of the ISL6261A depend on the both active mode and deeper sleep mode.
control signal states of DPRSTP#, FDE, and DPRSLPVR, as CPU mode-transition sequences often occur in concert with
shown in Table 2. These control signals can be tied to lntel® VID changes. The ISL6261A employs carefully designed
IMVP-6® control signals to maintain the optimal system mode-transition timing to work in concert with the VID changes.
configuration for all IMVP-6® conditions.
The ISL6261A is equipped with internal counters to prevent
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the control signal glitches from triggering unintended mode
ISL6261A to operate in Diode Emulation Mode (DEM) by transitions. For example: Control signals lasting less than
monitoring the low-side FET current. In diode emulation seven switching periods will not enable the diode emulation
mode, when the low-side FET current flows from source to mode.
drain, it turns on as a synchronous FET to reduce the
conduction loss. When the current reverses its direction, trying Dynamic Operation
to flow from drain to source, the ISL6261A turns off the The ISL6261A responds to VID changes by slewing to new
low-side FET to prevent the output capacitor from discharging voltages with a dv/dt set by the SOFT capacitor and the logic of
through the inductor, therefore eliminating the extra DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the output
conduction loss. When DEM is enabled, the regulator works in voltage will move at a maximum dv/dt of ±10mV/μs for large
automatic Discontinuous Conduction Mode (DCM), meaning changes. The maximum dv/dt can be used to achieve fast
that the regulator operates in CCM in heavy load, and recovery from Deeper Sleep to Active mode. If CSOFT = 20nF
operates in DCM in light load. DCM in light load decreases the and DPRSLPVR = 1, the output voltage will move at a dv/dt of
switching frequency to increase efficiency. This mode can be ±2mV/μs for large changes. The slow dv/dt into and out of
used to support the deeper sleep mode of the microprocessor. deeper sleep mode will minimize the audible noise. As the
output voltage approaches the VID command value, the dv/dt
DPRSTP# = 0 and FDE = 1 enables the Enhanced Diode
moderates to prevent overshoot. The ISL6261A is IMVP-6®
Emulation Mode (EDEM), which increases the VW-COMP
compliant for DPRSTP# and DPRSLPVR logic.
window voltage by 33%. This further decreases the
switching frequency at light load to boost efficiency in the Intersil R3™ has an intrinsic voltage feed forward function.
deeper sleep mode. High-speed input voltage transients have little effect on the
output voltage.
For other combinations of DPRSTP#, FDE, and
DPRSLPVR, the ISL6261A operates in forced CCM. Intersil R3™ commands variable switching frequency during
transients to achieve fast response. Upon load application,
The ISL6261A operational modes can be set according to
the ISL6261A will transiently increase the switching
CPU mode signals to achieve the best performance. There
frequency to deliver energy to the output more quickly.
are two options: (1) Tie FDE to DPRSLPVR, and tie
Compared with steady state operation, the PWM pulses
DPRSTP# and DPRSLPVR to the corresponding CPU mode
during load application are generated earlier, which
signals. This configuration enables EDEM in deeper sleep
effectively increases the duty cycle and the response speed
mode to increase efficiency. (2) Tie FDE to “1” and
of the regulator. Upon load release, the ISL6261A will
DPRSTP# to “0” permanently, and tie DPRSLPVR to the
transiently decrease the switching frequency to effectively
corresponding CPU mode signal. This configuration sets the
reduce the duty cycle to achieve fast response.
regulator in EDEM all the time. The regulator will enter DCM

TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261A

FAULT DURATION
FAULT TYPE PRIOR TO PROTECTION PROTECTION ACTIONS FAULT RESET

Overcurrent fault 120µs PWM tri-state, PGOOD latched low VR_ON toggle or VDD toggle

Way-Overcurrent fault <2µs PWM tri-state, PGOOD latched low VR_ON toggle or VDD toggle

Overvoltage fault (1.7V) Immediately Low-side FET on until Vcore < 0.85V, then VDD toggle
PWM tri-state, PGOOD latched low
(OV-1.7V always)
Overvoltage fault (+200mV) 1ms PWM tri-state, PGOOD latched low VR_ON toggle or VDD toggle

Undervoltage fault (-300mV) 1ms PWM tri-state, PGOOD latched low VR_ON toggle or VDD toggle

Over-temperature fault (NTC<1.18) Immediately VR_TT# goes high N/A

15 FN6354.3
November 5, 2009
 ISL6261A

Protection The ISL6261A has a thermal throttling feature. If the voltage

The ISL6261A provides overcurrent (OC), overvoltage (OV), on the NTC pin goes below the 1.2V over-temperature
undervoltage (UV) and over-temperature (OT) protections as threshold, the VR_TT# pin is pulled low indicating the need
shown in Table 3. for thermal throttling to the system oversight processor. No
other action is taken within the ISL6261A.
Overcurrent is detected through the droop voltage, which is
designed as described in the “Component Selection and Component Selection and Application
Application” section. The OCSET resistor sets the
overcurrent protection level. An overcurrent fault will be Soft-Start and Mode Change Slew Rates
declared when the droop voltage exceeds the overcurrent The ISL6261A commands two different output voltage slew
set point for more than 120µs. A way-overcurrent fault will be rates for various modes of operation. The slow slew rate
declared in less than 2µs when the droop voltage exceeds reduces the inrush current during start-up and the audible noise
twice the overcurrent set point. In both cases, the UGATE during the entry and the exit of Deeper Sleep Mode. The fast
and LGATE outputs will be tri-stated and PGOOD will go low. slew rate enhances the system performance by achieving
active mode regulation quickly during the exit of Deeper Sleep
The overcurrent condition is detected through the droop
Mode. The SOFT current is bidirectional-charging the SOFT
voltage. The droop voltage is equal to Icore × Rdroop, where
capacitor when the output voltage is commanded to rise, and
Rdroop is the load line slope. A 10μA current source flows out
discharging the SOFT capacitor when the output voltage is
of the OCSET pin and creates a voltage drop across ROCSET
commanded to fall.
(shown as R10 in Figure 2). Overcurrent is detected when
the droop voltage exceeds the voltage across ROCSET. Figure 5 shows the circuitry on the SOFT pin. The SOFT pin,
Equation 1 gives the selection of ROCSET. the non-inverting input of the error amplifier, is connected to
ground through capacitor CSOFT. ISS is an internal current
I OC × Rdroop (EQ. 1)
ROCSET = source connected to the SOFT pin to charge or discharge
10 μA CSOFT. The ISL6261A controls the output voltage slew rate
by connecting or disconnecting another internal current
For example: The desired overcurrent trip level, Ioc, is 30A,
source IZ to the SOFT pin, depending on the state of the
Rdroop is 2.1mΩ, Equation 1 gives ROCSET = 6.3k.
system, i.e. Start-up or Active mode, and the logic state on
Undervoltage protection is independent of the overcurrent the DPRSLPVR pin. The SOFT-START CURRENT section
limit. A UV fault is declared when the output voltage is lower of the Electrical Specification Table shows the specs of these
than (VID-300mV) for more than 1ms. The gate driver outputs two current sources.
will be tri-stated and PGOOD will go low. Note that a practical
core regulator design usually trips OC before it trips UV.
I I
There are two levels of overvoltage protection and response. SS Z
INTERNAL TO
An OV fault is declared when the output voltage exceeds the ISL6261A

VID by +200mV for more than 1ms. The gate driver outputs
will be tri-stated and PGOOD will go low. The inductor
current will decay through the low-side FET body diode. ERROR
AMPLIFLIER

Toggling of VR_ON or bringing VDD below 4V will reset the

fault latch. A way-overvoltage (WOV) fault is declared
immediately when the output voltage exceeds 1.7V. The
ISL6261A will latch PGOOD low and turn on the low-side C V
FETs. The low-side FETs will remain on until the output SOFT REF

voltage drops below approximately 0.85V, then all the FETs

are turned off. If the output voltage again rises above 1.7V,
the protection process repeats. This mechanism provides
FIGURE 5. SOFT PIN CURRENT SOURCES FOR FAST AND
maximum protection against a shorted high-side FET while SLOW SLEW RATES
preventing the output from ringing below ground. Toggling
VR_ON cannot reset the WOV protection; recycling VDD will ISS is 41µA typical and is used during start-up and mode
reset it. The WOV detector is active all the time, even when changes. When connected to the SOFT pin, IZ adds to ISS to
other faults are declared, so the processor is still protected get a larger current, labeled IGV in the “Electrical
against the high-side FET leakage while the FETs are Specification Table” starting on page 3, on the SOFT pin. IGV
commanded off. is typically 200µA with a minimum of 175µA.

16 FN6354.3
November 5, 2009
 ISL6261A

10µA
R ocset
OCSET

I phase L
OC DCR Vo

Rs
VSUM
C
o

INTERNAL TO ISL6261A DROOP

DFB

series
ESR

R
DROOP

par
Cn
1

R drp2

R
VO

ntc
R
R drp1

opn1
1000pF
0~10

R
VSEN
VCC-SENSE TO PROCESSOR
SOCKET KELVIN
1 1000pF CONECTIONS
RTN
VSS-SENSE

opn2
330pF

R
VDIFF

FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING

The IMVP-6® specification reveals the critical timing Start-up Operation - CLK_EN# and PGOOD
associated with regulating the output voltage. SLEWRATE, The ISL6261A provides a 3.3V logic output pin for
given in the IMVP-6® specification, determines the choice of CLK_EN#. The system 3.3V voltage source connects to the
the SOFT capacitor, CSOFT, through Equation 2: 3V3 pin, which powers internal circuitry that is solely devoted
I GV to the CLK_EN# function. The output is a CMOS signal with
CSOFT = (EQ. 2)
4mA sourcing and sinking capability. CMOS logic eliminates
SLEWRATE
the need for an external pull-up resistor on this pin,
If SLEWRATE is 10mV/μs, and IGV is typically 200μA, CSOFT eliminating the loss on the pull-up resistor caused by
is calculated as: CLK_EN# being low in normal operation. This prolongs
C SOFT = 200 μA (10 mV μs ) = 20 nF (EQ. 3) battery run time. The 3.3V supply should be decoupled to
digital ground, not to analog ground, for noise immunity.
Choosing 0.015μF will guarantee 10mV/μs SLEWRATE at
minimum IGV value. This choice of CSOFT controls the start- At start-up, CLK_EN# remains high until 13 clock cycles
up slew rate as well. One should expect the output voltage to after the core voltage is within 20mV of the boot voltage. The
slew to the Boot value of 1.2V at a rate given by Equation 4: ISL6261A triggers an internal timer for the IMVP6_PWRGD
dV soft signal (PGOOD pin). This timer allows PGOOD to go high
I ss 41μA
= = = 2.8 mV (EQ. 4) approximately 7ms after CLK_EN# goes low.
dt C SOFT 0.015 μF μs
Static Mode of Operation - Processor Die Sensing
Selecting Rbias Remote sensing enables the ISL6261A to regulate the core
To properly bias the ISL6261A, a reference current needs to be voltage at a remote sensing point, which compensates for
derived by connecting a 147k, 1% tolerance resistor from the various resistive voltage drops in the power delivery path.
RBIAS pin to ground. This provides a very accurate 10μA
current source from which OCSET reference current is derived. The VSEN and RTN pins of the ISL6261A are connected to
Kelvin sense leads at the die of the processor through the
Caution should be used during layout. This resistor should processor socket. (The signal names are Vcc_sense and
be placed in close proximity to the RBIAS pin and be Vss_sense respectively). Processor die sensing allows the
connected to good quality signal ground. Do not connect any voltage regulator to tightly control the processor voltage at
other components to this pin, as they will negatively impact the die, free of the inconsistencies and the voltage drops due
the performance. Capacitance on this pin may create to layouts. The Kelvin sense technique provides for
instabilities and should be avoided. extremely tight load line regulation at the processor die side.

17 FN6354.3
November 5, 2009
 ISL6261A

These traces should be laid out as noise sensitive traces.

For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the 54µA 6µA
Internal to
processor should be laid out away from rapidly rising voltage ISL6261A

nodes (switching nodes) and other noisy traces. Common

NTC SW1 VR_TT#
mode and differential mode filters are recommended as
shown in Figure 6. The recommended filter resistance range
V R
is 0~10Ω so it does not interact with the 50k input resistance NTC NTC

of the differential amplifier. The filter resistor may be inserted SW2

R
between VCC-SENSE and the VSEN pin. Another option is S

to place one between VCC-SENSE and the VSEN pin and

1.23V 1.20V
another between VSS-SENSE and the RTN pin. The need of
these filters also depends on the actual board layout and the
noise environment.

Since the voltage feedback is sensed at the processor die, if FIGURE 7. CIRCUITRY ASSOCIATED WITH THE THERMAL
the CPU is not installed, the regulator will drive the output THROTTLING FEATURE
voltage all the way up to damage the output capacitors due Figure 7 shows the circuitry associated with the thermal
to lack of output voltage feedback. Ropn1 and Ropn2 are throttling feature of the ISL6261A. At low temperature, SW1
recommended, as shown in Figure 6, to prevent this is on and SW2 connects to the 1.20V side. The total current
potential issue. Ropn1 and Ropn2, typically ranging going into the NTC pin is 60µA. The voltage on the NTC pin
20~100Ω, provide voltage feedback from the regulator local is higher than 1.20V threshold voltage and the comparator
output in the absence of the CPU. output is low. VR_TT# is pulled up high by an external
Setting the Switching Frequency - FSET resistor. Temperature increase will decrease the NTC
thermistor resistance. This decreases the NTC pin voltage.
The R3 modulator scheme is not a fixed frequency PWM
When the NTC pin voltage drops below 1.2V, the comparator
architecture. The switching frequency increases during the
output goes high to pull VR_TT# low, signaling a thermal
application of a load to improve transient performance.
throttle. In addition, SW1 turns off and SW2 connects to
It also varies slightly depending on the input and output 1.23V, which decreases the NTC pin current by 6uA and
voltages and output current, but this variation is normally increases the threshold voltage by 30mV. The VR_TT#
less than 10% in continuous conduction mode. signal can be used by the system to change the CPU
operation and decrease the power consumption. As the
Resistor Rfset (R7 in Figure 2), connected between the VW
temperature drops, the NTC pin voltage goes up. If the NTC
and COMP pins of the ISL6261A, sets the synthetic ripple
pin voltage exceeds 1.23V, VR_TT# will be pulled high.
window voltage, and therefore sets the switching frequency.
Figure 8 illustrates the temperature hysteresis feature of
This relationship between the resistance and the switching
VR_TT#. T1 and T2 (T1>T2) are two threshold temperatures.
frequency in CCM is approximately given by Equation 5.
VR_TT# goes low when the temperature is higher than T1
R fset (kΩ ) = ( period(μs) − 0.29) × 2.33 (EQ. 5)
and goes high when the temperature is lower than T2.

In diode emulation mode, the ISL6261A stretches the VR_TT#

switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the Logic_1
switching loss at light load, which is important in conserving
battery power.

Voltage Regulator Thermal Throttling

Logic_0
lntel® IMVP-6® technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the T2 T1 T (oC)
voltage regulator. The ISL6261A features a thermal monitor
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
sensing the voltage across an externally placed negative
temperature coefficient (NTC) thermistor. Proper selection
and placement of the NTC thermistor allows for detection of
a designated temperature rise by the system.

18 FN6354.3
November 5, 2009
 ISL6261A

The NTC thermistor’s resistance is approximately given by Once RNTCTo and Rs is designed, the actual NTC resistance
the following formula: at T2 and the actual T2 temperature can be found in:

b⋅(
1
−
1
) (EQ. 6) RNTC _ T 2 = 2.78kΩ + RNTC _ T 1 (EQ. 13)
R (T ) = R ⋅e T + 273 To + 273
NTC NTCTo 1
T2 _ actual = − 273
T is the temperature of the NTC thermistor and b is a 1 R NTC _ T2 (EQ. 14)
constant determined by the thermistor material. To is the ln( ) + 1 ( 273 + To )
b R NTCTo
reference temperature at which the approximation is
derived. The most commonly used To is +25°C. For most One example of using Equations 10, 11 and 12 to design a
commercial NTC thermistors, there is b = 2750k, 2600k, thermal throttling circuit with the temperature hysteresis
4500k or 4250k. +100°C to +105°C is illustrated as follows. Since T1 = +105°C
From the operation principle of VR_TT#, the NTC resistor and T2 = +100°C, if we use a Panasonic NTC with b = 4700,
satisfies the following equation group: Equation 9 gives the required NTC nominal resistance as

1.20V R NTC_To = 431kΩ

R NTC (T1 ) + Rs = = 20kΩ (EQ. 7)
60 μA The NTC thermistor datasheet gives the resistance ratio as
1.23V 0.03956 at +100°C and 0.03322 at +105°C. The b value of
R NTC (T2 ) + Rs = = 22.78kΩ (EQ. 8) 4700k in Panasonic datasheet only covers up to +85°C;
54 μA
therefore, using Equation 11 is more accurate for +100°C
From Equation 7 and Equation 8, the following can be design and the required NTC nominal resistance at +25°C is
derived: 438kΩ. The closest NTC resistor value from manufacturers
is 470kΩ. So Equation 12 gives the series resistance as
RNTC(T2 ) − RNTC(T1 ) = 2.78kΩ (EQ. 9)
follows:
Substitution of Equation 6 into Equation 9 yields the required Rs = 20kΩ − R NTC _ 105C = 20kΩ − 15.61kΩ = 4.39kΩ
nominal NTC resistor value:
1 The closest standard value is 4.42kΩ. Furthermore,
b⋅( )
To + 273 Equation 13 gives the NTC resistance at T2:
2.78kΩ ⋅ e
RNTCTo = 1 1
(EQ. 10)
RNTC _ T 2 = 2.78kΩ + RNTC _ T 1 = 18.39kΩ
b⋅( ) b⋅( )
T2 + 273 T1 + 273
e −e
The NTC branch is designed to have a 470k NTC and a
In some cases, the constant b is not accurate enough to 4.42k resistor in series. The part number of the NTC
approximate the resistor value; manufacturers provide the thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
resistor ratio information at different temperatures. The thermistor should be placed in the spot that gives the best
nominal NTC resistor value may be expressed in another indication of the temperature of the voltage regulator. The
way as follows: actual temperature hysteretic window is approximately
2.78kΩ +105°C to +100°C.
RNTCTo = Λ Λ
(EQ. 11)
R NTC (T2 ) − R NTC (T1 )

Λ
where R NTC (T ) is the normalized NTC resistance to its
nominal value. The normalized resistor value on most NTC
thermistor datasheets is based on the value at +25°C.

Once the NTC thermistor resistor is determined, the series

resistor can be derived by:
1.20V
Rs = − R NTC (T1 ) = 20kΩ − R NTC_T1 (EQ. 12)
60 μA

19 FN6354.3
November 5, 2009
 ISL6261A

10µA
R ocset
OCSET
VO

OC

Rs
VSUM

Internal to ISL6261A DROOP

DFB

DROOP Vdcr I DCR

R series o

Cn
R par

R drp2
1
VO
R ntc (Rntc +Rseries ) Rpar
Rn
Rntc +Rseries +Rpar

R drp1
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING

Static Mode of Operation - Static Droop Using DCR G1, the gain of Vn to VDCR, is also dependent on the
Sensing temperature of the NTC thermistor:
The ISL6261A has an internal differential amplifier to Δ Rn (T )
accurately regulate the voltage at the processor die. G1 (T ) = (EQ. 17)
Rn (T ) + Rs
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2 The inductor DCR is a function of the temperature and is
shows the DCR sensing method. Figure 9 shows the approximately given by Equation 18:
simplified model of the droop circuitry. The inductor DC DCR(T ) = DCR25C ⋅ (1 + 0.00393 * (T − 25)) (EQ. 18)
current generates a DC voltage drop on the inductor DCR.
Equation 15 gives this relationship. in which 0.00393 is the temperature coefficient of the copper.
The droop amplifier output voltage divided by the total load
V DCR = I o × DCR (EQ. 15)
current is given by Equation 19:
An R-C network senses the voltage across the inductor to Rdroop = G1(T) ⋅ DCR (T ) ⋅ k droopamp (EQ. 19)
get the inductor current information. Rn represents the NTC
network consisting of Rntc, Rseries and Rpar. The choice of Rs Rdroop is the actual load line slope. To make Rdroop
will be discussed in the next section. independent of the inductor temperature, it is desired to
have:
The first step in droop load line compensation is to choose
Rn and Rs such that the correct droop voltage appears even G1 (T ) ⋅ (1 + 0.00393 * (T − 25)) ≅ G1t arg et (EQ. 20)
at light loads between the VSUM and VO nodes. As a rule of
thumb, the voltage drop across the Rn network, Vn, is set to where G1target is the desired ratio of Vn/VDCR. Therefore, the
be 0.5 to 0.8 times VDCR. This gain, defined as G1, provides temperature characteristics G1 is described by Equation 21:
a fairly reasonable amount of light load signal from which to G 1 t arg et
derive the droop voltage. G 1 (T ) = (EQ. 21)
(1 + 0.00393* (T − 25)
The NTC network resistor value is dependent on the
temperature and is given by Equation 16: For different G1 and NTC thermistor preference, Intersil
provides a design spreadsheet to generate the proper value
( Rseries + Rntc ) ⋅ R par
Rn (T ) = (EQ. 16) of Rntc, Rseries, Rpar.
Rseries + Rntc + R par
Rdrp1 (R11 in Fig. 2) and Rdrp2 (R12 in Figure 2) sets the
droop amplifier gain, according to Equation 22:

Rdrp 2
k droopamp = 1 + (EQ. 22)
R drp1

20 FN6354.3
November 5, 2009
 ISL6261A

After determining Rs and Rn networks, use Equation 23 to response. Figure 11 shows the transient response when Cn
calculate the droop resistances Rdrp1 and Rdrp2. is too small. Vcore may sag excessively upon load
application to create a system failure. Figure 12 shows the
Rdroop
Rdrp 2 = ( − 1) ⋅ Rdrp1 (EQ. 23) transient response when Cn is too large. Vcore is sluggish in
DCR ⋅ G1(25 o C ) drooping to its final value. There will be excessive overshoot
if a load occurs during this time, which may potentially hurt
Rdroop is 2.1mV/A per lntel® IMVP-6® specification.
the CPU reliability.
The effectiveness of the Rn network is sensitive to the
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in close icore ΔIcore
proximity of the inductor.

To verify whether the NTC network successfully compensates

the DCR change over temperature, one can apply full load Vcore Vcore ΔVcore
current, wait for the thermal steady state, and see how much
the output voltage deviates from the initial voltage reading. ΔVcore= ΔIcore×Rdroop
Good thermal compensation can limit the drift to less than FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
2mV. If the output voltage decreases when the temperature WAVEFORMS
increases, that ratio between the NTC thermistor value and
the rest of the resistor divider network has to be increased.
Following the evaluation board value and layout of NTC
icore
placement will minimize the engineering time.

The current sensing traces should be routed directly to the

Vcore Vcore
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated Rdrp2
may still need slight adjustment to achieve optimum load line FIGURE 11. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
slope. It is recommended to adjust Rdrp2 after the system SMALL
has achieved thermal equilibrium at full load. For example, if
the max current is 20A, one should apply 20A load current
and look for 42mV output voltage droop. If the voltage droop
icore
is 40mV, the new value of Rdpr2 is calculated by:

42 mV
R drp 2 _ new = ( R drp 1 + R drp 2 ) − R drp 1 Vcore Vcore
40 mV
(EQ. 24) FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
LARGE
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current The current sensing network consists of Rn, Rs and Cn. The
of the droop amplifier does not cause an offset voltage. The effective resistance is the parallel of Rn and Rs. The RC time
effective resistance on the VSUM pin is the parallel of Rs and constant of the current sensing network needs to match the
Rn, and the effective resistance on the DFB pin is the parallel L/DCR time constant of the inductor to get correct
of Rdrp1 and Rdrp2. representation of the inductor current waveform. Equation 25
shows this equation:
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing L ⎛ R × Rs ⎞
= ⎜⎜ n ⎟ × Cn (EQ. 25)
Figure 10 shows the desired waveforms during load DCR ⎝ Rn + Rs ⎟⎠
transient response. Vcore needs to be as square as possible
at Icore change. The Vcore response is determined by several Solving for Cn yields:
factors, namely the choice of output inductor and output
capacitor, the compensator design, and the droop capacitor L
design.
C n = DCR (EQ. 26)
The droop capacitor refers to Cn in Figure 9. If Cn is Rn × Rs
designed correctly, its voltage will be a high-bandwidth Rn + Rs
analog voltage of the inductor current. If Cn is not designed
correctly, its voltage will be distorted from the actual
waveform of the inductor current and worsen the transient

21 FN6354.3
November 5, 2009
 ISL6261A

For example: L = 0.45µH, DCR = 1.1mΩ, Rs = 7.68kΩ, and in the FB pin. It is recommended to keep this resistor below
Rn = 3.4kΩ 3k.

0.45μH Droop using Discrete Resistor Sensing -

0.0011 (EQ. 27) Static/Dynamic Mode of Operation
Cn = = 174nF
parallel(7.68k ,3.4k ) Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 14 shows the
Since the inductance and the DCR typically have 20% and equivalent circuit. Since the current sensing resistor voltage
7% tolerance respectively, the L/DCR time constant of each represents the actual inductor current information, Rs and Cn
individual inductor may not perfectly match the RC time simply provide noise filtering. The most significant noise
constant of the current sensing network. In mass production, comes from the ESL of the current sensing resistor. A low
this effect will make the transient response vary a little bit low ESL sensing resistor is strongly recommended. The
from board to board. Compared with potential long-term recommended Rs is 100Ω and the recommended Cn is
damage on CPU reliability, an immediate system failure is 220pF. Since the current sensing resistance does not
worse. So it is desirable to avoid the waveforms shown in appreciably change with temperature, the NTC network is
Figure 11. It is recommended to choose the minimum Cn not needed for thermal compensation.
value based on the maximum inductance so only the
scenarios of Figures 10 and 12 may happen. It should be Droop is designed the same way as the DCR sensing
noted that, after calculation, fine-tuning of Cn value may still approach. The voltage on the current sensing resistor is
be needed to account for board parasitics. Cn also needs to given by the following Equation 28:
be a high-grade cap like X7R with low tolerance. Another Vrsen = Rsen ⋅ I o (EQ. 28)
good option is the NPO/COG (class-I) capacitor, featuring
only 5% tolerance and very good thermal characteristics. But Equation 21 shows the droop amplifier gain. So the actual
the NPO/COG caps are only available in small capacitance droop is given by Equation 29:
values. In order to use such capacitors, the resistors and
thermistors surrounding the droop voltage sensing and ⎛ Rdrp 2 ⎞
Rdroop = Rsen ⋅ ⎜1 + ⎟ (EQ. 29)
droop amplifier need to be scaled up 10X to reduce the ⎜ R ⎟
capacitance by 10X. Attention needs to be paid in balancing ⎝ drp1 ⎠
the impedance of droop amplifier. Solving for Rdrp2 yields:

Dynamic Mode of Operation - Compensation ⎛ Rdroop ⎞

Parameters Rdrp 2 = Rdrp1 ⋅ ⎜⎜ − 1⎟⎟ (EQ. 30)
⎝ Rsen ⎠
The voltage regulator is equivalent to a voltage source equal
to VID in series with the output impedance. The output For example: Rdroop = 2.1mΩ. If Rsen = 1m and Rdrp1 = 1k,
impedance needs to be 2.1mΩ in order to achieve the easy calculation gives that Rdrp2 is 1.1k.
2.1mV/A load line. It is highly recommended to design the
The current sensing traces should be routed directly to the
compensation such that the regulator output impedance is
current sensing resistor pads for accurate measurement.
2.1mΩ. A type-III compensator is recommended to achieve
However, due to layout imperfections, the calculated Rdrp2
the best performance. Intersil provides a spreadsheet to
may still need slight adjustment to achieve optimum load line
design the compensator parameters. Figure 13 shows an
slope. It is recommended to adjust Rdrp2 after the system
example of the spreadsheet. After the user inputs the
has achieved thermal equilibrium at full load.
parameters in the blue font, the spreadsheet will calculate
the recommended compensator parameters (in the pink
font), and show the loop gain curves and the regulator output
impedance curve. The loop gain curves need to be stable for
regulator stability, and the impedance curve needs to be
equal to or smaller than 2.1mΩ in the entire frequency range
to achieve good transient response.

The user can choose the actual resistor and capacitor values
based on the recommendation and input them in the
spreadsheet, then see the actual loop gain curves and the
regulator output impedance curve.

Caution needs to be used in choosing the input resistor to

the FB pin. Excessively high resistance will cause an error to
the output voltage regulation due to the bias current flowing

22 FN6354.3
November 5, 2009
 ISL6261A

VSS

FIGURE 13. AN EXAMPLE OF ISL6261A COMPENSATION SPREADSHEET

23 FN6354.3
November 5, 2009
 ISL6261A

10µA
Rocset
OCSET
VO

OC

Rs
VSUM

Internal to ISL6261A DROOP

DFB

DROOP Vrsen I Rsen

o

Cn
1

R drp2
VO

R drp1
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING

Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board)

FIGURE 15. CCM EFFICIENCY, VID = 1.1V, FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V

FIGURE 17. DEM EFFICIENCY, VID = 0.7625V, FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V

24 FN6354.3
November 5, 2009
 ISL6261A

Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)

FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V, FIGURE 20. ENHANCED DEM LOAD LINE, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V

FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V, FIGURE 22. ENHANCED DEM LOAD LINE, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V

5V/div 5V/div

0.5V/div 0.5V/div

1V/div 1V/div

10V/div 10V/div
FIGURE 23. SOFT-START, VIN = 19V, Io = 0A, VID = 1.5V, FIGURE 24. SOFT-START, VIN = 19V, Io = 0A, VID = 1.1V,
Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE

25 FN6354.3
November 5, 2009
 ISL6261A

Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)

5V/div 5V/div

0.1V/div 0.1V/div

1V/div 1V/div

10V/div 10V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V, FIGURE 26. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 0.7625V,
Ch1: CLK_EN#, Ch2: VO, Ch3: PMON, Ch1: CLK_EN#, Ch2: VO, Ch3: PMON,
Ch4: PHASE Ch4: PHASE

5V/div

0.5V/div
7.68ms
5V/div

10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY, FIGURE 28. SHUT DOWN, VIN = 12.6V, Io = 2A, VID = 1.1V,
VIN = 19V, Io = 2A, VID = 1.1V, Ch1: CLK_EN#, Ch1: VR_ON, Ch2: VO, Ch3: PGOOD,
Ch2: VO, Ch3: PGOOD, Ch4: PHASE Ch4: PHASE

FIGURE 29. SOFT START INRUSH CURRENT, VIN = 19V, FIGURE 30. VIN TRANSIENT TEST, VIN = 8Æ19V, Io = 2A,
Io = 2A, VID = 1.1V, Ch1: DROOP-VO VID = 1.1V, Ch2: VO, Ch3: VIN, Ch4: PHASE
(2.1mV = 1A), Ch2: VO, Ch3: Vcomp, Ch4: PHASE

26 FN6354.3
November 5, 2009
 ISL6261A

Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)

FIGURE 31. C4 ENTRY/EXIT, VIN = 12.6V, Io = 0.7A, FIGURE 32. VID TOGGLING, VIN = 12.6V, Io= 16.5A,
HFM/LFM/C4 VID = 1.05V/0.8375V/0.7625V, HFM/LFM VID = 1.05V/0.8375V,
FDE = DPRSLPVR, Ch1: PMON, Ch2: VO, FDE = DPRSLPVR, Ch1: PMON, Ch2: VO,
Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE

FIGURE 33. LOAD TRANSIENT RESPONSE IN CCM FIGURE 34. LOAD TRANSIENT RESPONSE IN CCM
VIN = 12.6V, Io = 2AÆ20A (100A/µs), VID = 1.1V, VIN = 12.6V, Io = 20AÆ2A (50A/µs), VID = 1.1V,
Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED
PMON, Ch4: PHASE PMON, Ch4: PHASE

100A/us 50A/us

FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM FIGURE 36. LOAD TRANSIENT RESPONSE IN EDEM
VIN = 12.6V, Io = 2AÆ20A (100A/µs)Æ2A (50A/µs), VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
VID = 1.1V, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
FILTERED PMON, Ch4: PHASE

27 FN6354.3
November 5, 2009
 ISL6261A

Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)

100A/us 50A/us

FIGURE 37. LOAD TRANSIENT RESPONSE IN EDEM FIGURE 38. LOAD TRANSIENT RESPONSE IN EDEM
VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE

120us

FIGURE 39. OVERCURRENT PROTECTION, VIN = 12.6V, FIGURE 40. OVERVOLTAGE (>1.7V) PROTECTION,
Io = 0AÆ28A, VID = 1.1V, Ch1: DROOP-VO VIN = 12.6V, Io = 2A, VID = 1.1V,
(2.1mV = 1A), Ch2: VO, Ch3: PGOOD, Ch2: VO, Ch3: PGOOD, Ch4: PHASE
Ch4: PHASE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

28 FN6354.3
November 5, 2009
 ISL6261A Eval1 Evaluation Board Schematics
Controller
+3.3V

P13
P16
P18
P19
P20

P23
P24
P25
P27
P28

P33
P31
S1

P2
J8
+3.3V1 1 2 2 21 10 DPRSLPVR

R32
10K
R36
10K
R37
10K
R38
10K
R40
10K

10K
R42
10K

R47
100
R41
1 ON 9 IN
3 2 ON 8 PSI# U1
4 3 ON 7 IN
4 ON R108 R107
5 5 ON 6 PMON/PGD_IN VR_ON 1 1 14 14
DNP
DPRSTP# 0 DPRSLPVR 2 13
SD05H0SK IN 2 13

C92
DNP
FDE DPRSTP# 3 3 12 12
+3.3V

R103
CLK_EN# 4 11

10K
R10
10K
R14
10K
R18
10K

10K
R21
4 11
1 12 2

OUT
5 10
3 R2 510 J9

5 10
P6
6 9
10K
29

6 9
R3

J15
R1 510

OUT
+3.3V 1 1 2 2 7 7 8 8
PGOOD
C24 MST7_SPST
DPRSLPVR
SSL_LXA3025IGC

VID6

J1
IN
1

J10 VID5 IN
1 1UF VID4
FDE 2 21 IN
GRN
RED

VID3 IN
3 3 VID2 IN
J17
PGOOD 3V3 VID1 IN 2 2 1 1 5V 3.3V J3
D3

+3.3V PSI# 1X3 VID0 IN

P10

P14
P7

P1
R17 DNP R16

DNP

R46
PGOOD

VR_ON
CLK_EN
DPRSTP

10
DPRSLPVR
3V3
34
2

VID6
VID5
VID4
VID3

10UF
0

R39

C30
0.015UF

147K

2
2N7002
R20
499

R22
1
C10

Q5

P34
C8

+3.3V

C17
DNP

FDE VID2
2

10UF
R4 PMON/PGD_IN +5V

C31
U6
RBIAS PMON VID1 J2
VR_TT RBIAS VID0
6.34K VR_TT VCCP
SOFT NTC LGATE LGATE J4

ISL6261A
C3 SOFT VSSP OUT
VCC_PRM OCSET

0.01UF
OCSET PHASE GND_POWER
ISL6261A

C28

C29
1UF
DNP VW UGATE OUT
VW COMP BOOT PHASE
FB NC OUT
1000PF
6.81K

FB UGATE
DNP
R13

C13

OUT
R9

VDIFF
DROOP
VSEN

VSUM
BOOT

DFB
EP

RTN

VIN
VSS
VDD
OUT
P8

VO
P12
C23 R43
P5
P4

C9 R19 R23 C20 3 OFF

10K 2 VR_ON
DNP 1 S4
150PF 464K 5.49K 390PF ON

P32
IN VCCSENSE C12 R24 R30 R44
COMP VDIFF1 +3.3V J19
R5 1
IN VCORE 47PF 2.21K 0 10K 2 21
R11 R25 R33 R45 3 3
0 1 1 2 2 5V VR_ON1

P26
IN
10UF

C14 1X3
C2

0 0 2 10K
P17

P21
P9

J16
1000PF

C27
1UF
R6
GND_POWER 1000PF C18 VSEN
C11

IN
0 R34
P15
P11

R12

P29
IN VSSSENSE 330PF RTN 0
0.22UF
0
C26

DROOP R7 C6 R35
DFB VIN IN
P3

DNP R8 DNP R15 0

3.57K 10K NTC

5.23K C7 1K NOTE:
0.1UF
C15

R28

DNP
C25
P30 DNP
R31

RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING TITLE: REV:

0.068UF

330PF
0.12UF

8200PF

4.53K

VCC_PRM ISL6261 EVAL1

P22

PGND1 AND SOURCE OF Q3 AND Q4. ?

C16

C19

R27
C21

IN
CONTROLLER
ENGINEER: DATE:
R29

JIA WEI MAR-14

VSUM
IN
DRAWN BY: SHEET:
1 OF
November 5, 2009
FN6354.3
November 5, 2009
FN6354.3 30

IN
IN
IN
IN

BOOT
PHASE
UGATE

LGATE
Power Stage

0
R48
P36 P35

C1
0.22UF
Q1

Q2
IRF7821

IRF7832
Q4
Q3
VIN

IRF7821

IRF7832
OUT

C33 R49 C32

DNP DNP 1UF
2 D2 1 C4
10UF
DNP
10UF C5
J20 4

10UF C5B
3 R82
1
2

56UF
J21 4

R83
1
ISL6261A Eval1 Evaluation Board Schematics (Continued)

3 56UF
1

1
2
J6

C34
J5

0.1UF P37
P38

VSUM
OUT R51 R50
VSSSENSE
VCCSENSE

P39
7.68K 0
IN
IN
L1

DNP
R52
0.45UH

VCC_PRM
OUT R53
P40
0
J22 4

3
DNP
R54
R60

1
2
BUS WIRE

C35
1
J13

0.1UF P41
C91
0.1UF

C45 C42 C39 C43 C38 C37 C36 C40

22UF 22UF 22UF 330UF 22UF 22UF 22UF 330UF

C51 C50 C49 C44 C48 C47 C46 C41

22UF 22UF 22UF 330UF 22UF 22UF 22UF 330UF

C57 C56 C55 C90 C54 C53 C52 C89

22UF 22UF 22UF 330UF 22UF 22UF 22UF 330UF

C63 C62 C61 C60 C59 C58

VCORE

22UF 22UF 22UF 22UF 22UF 22UF

C69 C68 C67 C66 C65 C64
22UF 22UF 22UF 22UF 22UF 22UF
C71 C70
GND_POWER

22UF 22UF
J14
1

OUT
OUT

ISL6261A
 ISL6261A Eval1 Evaluation Board Schematics (Continued)
Socket

AF24
AF19
AF16
AF13

AE26
AE23
AE19
AE16
AE14
AF21

AF11

AE11
AF8
AF6
AF3

AE8
AE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A4 VSS VSS AE1
A8 VSS VSS AD25
A11 VSS VSS AD22
A14 VSS VSS AD19
A16 VSS VSS AD16
A19 VSS VSS AD13
B26 VCCA A23 VSS VSS AD11
VCCSENSE
VCCP G21 A26 VSS VSS AD8
OUT AF7 VCCSENSE VCCP J6 B6 VSS VSS AD5
VCCP J21 B8 VSS VSS AD2
A7 K6 B11 AC24

OUT
IN A9 VCC VCCP K21 B13 VSS VSS AC21
VCC VCCP VSS VSS
31

A10 VCC VCCP M6 B16 VSS VSS AC19

A12 M21 B19 AC16

AE2 VID6 OUT

AF2 VID5 OUT
AE3 VID4 OUT
AF4 VID3 OUT
AE5 VID2 OUT
AF5 VID1 OUT
AD6 VID0 OUT
VCORE
VCC VCCP VSS VSS

PSI#
A13 VCC VCCP N6 B21 VSS VSS AC14
A15 VCC VCCP N21 B24 VSS VSS AC11
A17 VCC VCCP R6 C2 VSS VSS AC8
A18 VCC VCCP R21 C5 VSS VSS AC6
A20 T6 C8 AC3

AD26

AF26
AF25
AF23
AF22
AE25
AE24
AE22
AD24
AD23
AD20

AC26
AC25
AC23
AC22
AC20

AB25
AB24
AB22

AA26
AA24
AA23
AE21

AD21

AB21

AA21
B7 VCC VCCP T21 C11 VSS VSS AB26

AE6

AD4
AD3

AC5
AC4
AC2

AB6
AB5
AB3
AB2

AA6
AF1

AD1

AC1
B9 VCC VCCP V6 C14 VSS VSS AB23
B10 VCC VCCP V21 C16 VSS VSS AB19
B12 VCC VCCP W21 C19 VSS VSS AB16
VCC VCCP VSS VSS

GTLREF
VID6
VID5
VID4
VID3
VID2
VID0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
PSI

VID1
B14 VCC A3 S COMP3 V1 C22 VSS VSS AB13
B15 VCC VCC AF20 A5 S COMP1 U26 C25 VSS VSS AB11
B17 VCC VCC AF18 A6 S COMP2 U1 D1 VSS VSS AB8
B18 AF17 A21 R26 D4 AB4

INTEL_IMPV6
VCC VCC S VSS

SOCKET1
B20 AF15 A22 COMP0 AA4 D8 VSS AB1
C9 VCC VCC AF14 A24 S S AA3 D11 VSS VSS AA25
C10 VCC VCC AF12 A25 S S AA1 D13 VSS VSS AA22
INTEL_IMPV6

VCC
SOCKET1

C12 VCC AF10 B1 S S Y26 D16 VSS VSS AA19

C13 VCC VCC AF9 B2 S S Y25 D19 VSS VSS AA16
C15 VCC VCC AE20 B3 S S Y23 D23 VSS VSS AA14
C17 VCC VCC AE18 B4 S S Y22 D26 VSS VSS AA11
C18 VCC VCC AE17 B5 S S Y5 E3 VSS VSS AA8
D9 VCC VCC AE15 B22 S S Y4 E6 VSS VSS AA5
D10 VCC VCC AE13 B23 S S Y2 E8 VSS VSS AA2
D12 VCC VCC AE12 B25 S S Y1 E11 VSS VSS Y24
VCC VCC S VSS VSS

ISL6261A
D14 AE10 C1 S W25 E14 Y21
VCC VCC S S VSS VSS

W22
D15 VCC VCC AE9 C3 S S W24 E16 VSS VSS Y6
D17 VCC VCC AD18 C4 S S E19 VSS VSS Y3
D18 VCC VCC AD17 C6 S S W6 E21 VSS VSS W26
E7 VCC VCC AD15 C7 S S W5 E24 VSS VSS W23
E9
E10
E12
VCC
VCC
VCC
VCC
AD14
AD12
AD10
C20
C21
C23
S
S INTEL_IMPV6 S
S
W3
W2
V26
F2
F5
F8
VSS
VSS
VSS
VSS
W4
W1
V25
E13 VCC VCC AD9 C24 S S V24 F11 VSS VSS V22
VCC VCC S VSS VSS
SOCKET1
E15 AD7 C26 S V23 F13 V5
E17 VCC VCC AC18 D2 S S V4 F16 VSS VSS V2
E18 VCC VCC AC17 D3 S S V3 F19 VSS VSS U24
E20 VCC VCC AC15 D5 S S U25 F22 VSS VSS U21
F7 VCC VCC AC13 D6 S S U23 F25 VSS VSS U6
F9 VCC VCC AC12 D7 S S U22 G1 VSS VSS U3
F10 VCC VCC AC10 D20 S S U5 G4 VSS VSS T26
F12 VCC VCC AC9 D21 S S U4 G23 VSS VSS T23
F14 VCC VCC AC7 D22 S S U2 G26 VSS VSS T4
F15 VCC VCC AB20 D24 S S T25 H3 VSS VSS T1
F17 VCC VCC AB18 D25 S S T24 H6 VSS VSS R25
F18 VCC VCC AB17 E1 S S T22 H21 VSS VSS R22
F20 VCC VCC AB15 E2 S S T5 H24 VSS VSS R5
AA7 VCC VCC AB14 E4 S S T3 J2 VSS VSS R2
VCC VCC S S VSS VSS

VSSSENSE
AA9 VCC VCC AB12 E5 S S T2 J5 VSS VSS P24
AA10 VCC VCC AB10 E22 S S R24 J22 VSS VSS P21
AA12 VCC VCC AB9 E23 S S R23 J25 VSS VSS P6
AA13 VCC VCC AB7 E25 S R4 VSS VSS P3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA15 AA20 E26 S R3
AA17 VCC VCC AA18 F1 S S R1
VCC VCC F3 S S P26
S S

VSSSENSE
F4 S S P25

K4

L3
L6
K23
K26

L24
M2
M5

N4
M22
M25

N23
N26
AE7
L21

N1
K1
F6 S S P23
F21 S S P22
F23 S S P5
F24 P4

GND_POWER
S

OUT
S

IN
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
H2
H4
H5

K2
K3
K5

L2
L4
L5
G2
G3
G5
G6

H22
H23
H25
H26
J3
J4

K22
K24
K25

L22
L23
L25
L26
M3
M4

N2
N3
N5

P2
F26

G22
G24
G25

J23
J24
J26

M23
M24
M26

N22
N24
N25
J1

M1

P1
H1

L1
November 5, 2009
FN6354.3
 ISL6261A Eval1 Evaluation Board Schematics (Continued)
Dynamic Load

J12

J11
GND_POWER +12V
U5
C80
32

1 VDD LO 8
1UF 2 7 IN VCORE
HB VSS
3 HO LI 6
R74
4 HS HI 5
249 D1

2
2 HUF76129D3S
HIP2100 3 1
1 Q15
R73
BAV99 1
4 J23

3
249 2

3
0.12
R75

R76
0.1

ISL6261A
+12V
+12V GND_POWER
49.9K

ON
R71

R72 3
2
S5 1
3

2N7002 499
1 OFF
10UF

Q14
C81
2
November 5, 2009
FN6354.3
 ISL6261A Eval1 Evaluation Board Schematics (Continued)
Geyserville Transition Gen.

U10

10K
R84
10K
R87
10K
R90
10K
R93
10K
R96
10K
R99
10K
R81
U7 1 U2 20 +3.3V_GEY 32 8 VID0
G1 VCC 35 RC0 RB0 9 VID1 OUT
C72 RC1 RB1 OUT
1 1 14 14 2 A1 G2 19 36 RC2 RB2 10 VID2 OUT
37 RC3 RB3 11 VID3 OUT
2 2 13 13 3 A2 Y1 18 0.1UF 42 RC4 RB4 14 VID4 OUT
43 RC5 RB5 15 VID5 OUT
3 3 12 12 4 A3 Y2 17 44 RC6 RB6 16 VID6 OUT
1 RC7 RB7 17
4 4 11 11 5 A4 Y3 16
12 33

1X3
NC NC

J7

3 3
5 10 10 6 15 13 34

2 21
5 A5 Y4 NC NC DIRECT DELAY
PSI#

1
6 6 9 9 7 A6 Y5 14 38 RD0 19
39 RA0 20 OUT DPRSLPVR
7 RD1 RA1 DPRSTP# OUT
7 8 8 8 A7 Y6 13 40 RD2 RA2 21 OUT
33

41 RD3 RA3 22 R106

9 A8 Y7 12 2 RD4 RA4 23 PGD_IN OUT
MST7_SPST 3 RD5 RA5 24
DNP VR_ON1 OUT
10 GND Y8 11 4 RD6
5 RD7 30
HC540 OSC1
25 RE0 31 U11
26 OSC2
27 RE1 18 1 2
R100 RE2 MCLR

15PF

15PF
R82
10K
R85
10K
R88
10K
10K
R94
10K
R97
10K
10K
C78
R91

C85

C87
U8 1 U3 20 +3.3V_GEY 6 7
G1 VCC 29 VSS VDD 28 HCM49
C73 VSS VDD 1UF
1 1 14 14 2 A1 G2 19
0.1UF RESETS8
2 2 13 13 3 A2 Y1 18 PIC16F874 +3.3V_GEYR69 1 4
3 3 12 12 4 A3 Y2 17 R104 10K

0.01UF
2 3
4 11 11 5 16

C79
4 A4 Y3 0 EVQPA
5 5 10 10 6 A5 Y4 15 R67

R105
CLK_EN# J28

P43
IN
+3.3V

0
6 6 9 9 7 A6 Y5 14 1 1 2 2
DNP
7 7 8 8 8 A7 Y6 13 C86

P42

P45
9 A8 Y7 12
1UF

ISL6261A
R68
DNP
MST7_SPST
10 GND Y8 11
HC540 U12
+3.3V_GEY R77
1 1A Vcc 14
10K
R101

MODE TRANS 2 13
R83
10K
R86
10K
R89
10K
R92
10K
R95
10K
R98
10K
10K

R65
10K
U9 1 U4 20 +3.3V_GEY 1Y 6A
G1 VCC S2 3 12
C74 2A 6Y
1 1 14 14 2 A1 G2 19 1 4

3
4 2Y 5A 11
2 13 13 3 18 0.1UF +3.3V_GEY 2 3

0.1UF
2 A2 Y1 5 10

C77
3A 5Y

BAV99

BAV99
3 3 12 12 4 A3 Y2 17 EVQPA

S3

S9
6 3Y 4A 9
4 11 5 16

R63
10K
4 11 A4 Y3 7 8
GND 4Y
5 5 10 10 6 A5 Y4 15 DPRSLP
S6 AC04

2
1

1
6 6 9 9 7 A6 Y5 14 1 4

R70 0

R78 0

R79 0

R80 0
7 8 8 13 2 3

0.1UF
7 8 A7 Y6 +3.3V_GEY

C75
9 A8 Y7 12 EVQPA
MST7_SPST

P44
10 11

R66
10K
GND Y8
HC540
LOOP

C84
DNP

C88
DNP
J25
1 1 2 2
R55 10K +3.3V_GEY

R64
10K
R56 10K PSI# S7
R57 1 4
10K
2 3
J24 R58 0.1UF
C76

+3.3V 1 1 2 2 +3.3V_GEY 10K +3.3V_GEY EVQPA

TITLE: REV:
R59 10K R102 ISL6261 EVAL1
PSI#
R61
10K J29
GEYSERVILLE TRANSITION GEN.
10K 1 ENGINEER: DATE:
1 2 2 JIA WEI MAR-
R62 10K DRAWN BY: SHEET:
5
November 5, 2009
FN6354.3
 ISL6261A

Package Outline Drawing

L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00 A 36X 0.50
6
B 31 40
PIN #1 INDEX AREA

6
30 1
PIN 1
INDEX AREA

4 . 10 ± 0 . 15

6.00
21 10
(4X) 0.15
20 11
0.10 M C A B
TOP VIEW 40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW

SEE DETAIL "X"

0.10 C C
0 . 90 ± 0 . 1
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
SIDE VIEW 0.08 C
( 4 . 10 )

( 36X 0 . 5 )

C 0 . 2 REF 5
( 40X 0 . 23 )

0 . 00 MIN.
( 40X 0 . 6 ) 0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.

34 FN6354.3
November 5, 2009