Digital Systems Design : BECE102L

Design procedure of Decoder and problems

Dr. Prashanth Kumar B

Sr. Assistant Professor
Department
School of Electronics Engineering
 INTRODUCTION TO COMBINATIONAL LOGIC

The digital system consists of two types of circuits,

 Combinational circuit:
 consists of logic gates
 output at any time is determined from the
present combination of inputs.

 Sequential circuit:
 comprises both logic gates and the state of
storage elements such as flip-flops.
 The output of a sequential circuit depends not
only on present value of inputs but also on
past state of inputs.
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 INTRODUCTION TO COMBINATIONAL LOGIC

 A combinational circuit consists of input variables,

logic gates, and output variables.

 The logic gates accept signals from inputs and

output signals are generated according to the
logic circuits employed in it.

 Binary information from the given data transforms

to desired output data in this process.

 Both input and output are obviously the binary

signals, i.e., either logic 1 or logic 0.
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 INTRODUCTION TO COMBINATIONAL LOGIC

Block diagram of a combinational logic circuit

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 INTRODUCTION TO COMBINATIONAL LOGIC

 For n number of input variables to a

combinational circuit, 2n possible combinations of
binary input states are possible.

 For each possible combination, there is one and

only one possible output combination.

 A combinational logic circuit can be described by

m Boolean functions and each output can be
expressed in terms of n input variables.

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MODULE- 4 ECE2003 – DIGITAL LOGIC DESIGN 23
 DESIGN PROCEDURE

 Any combinational circuit can be designed by the

following steps of design procedure.
1. The problem statement.
2. Identify the number of input and output variables.
3. The input and output variables are assign with letter

symbols.
4. Construction of a truth table for the given logic.

5. The simplified Boolean expression is obtained by any

method of minimization—algebraic method, Karnaugh
map method.

MODULE- 4 6.A logic diagram EiCsE20r0e3 –aDlIiGzITeA LdLO GfrICoDm

E SIG Nthe simplified Boolean 24
 DESIGN PROCEDURE
EXAMPLE-1:
 Design a combinational circuits with three input
variables that will produce a logic-1 output when
more than one input variables are HIGH state.
Solution:
STEP1: The problem statement.
Design a combinational circuits with three input variables that
will produce a logic-1 Output when more than one input
variables are HIGH.

STEP2: Identify the input and output variables

No. of inputs required: 3
No. of output required: 1
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 DESIGN PROCEDURE

STEP3: The input & outputs are assign with letter symbols
Letter symbol for inputs: A, B, C
Letter symbol for output: Y

STEP4: Construction of a truth table for the given logic

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 DESIGN PROCEDURE

STEP5: obtain the simplified expression for output variable

using K-map simplification

STEP6: A logic diagram is realized from the simplified

Boolean expression using logic gates
C
0 1
AB
00 0 0
01 0 1
11 1 1
10 0 1 Y = (AB)+(AC)+(BC)
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MO DULE-4 ECE2003 – DIGITAL LOGIC DESIGN 188
 DECODERS

 A decoder is a combinational circuit that converts

binary information from ‘n’ input lines to a
maximum of ‘2n’ unique output lines.

 The encoded information is presented as ‘n’

inputs producing ‘2n’ possible outputs. The 2n
output values are from 0 through 2n-1.

 A decoder is provided with enable inputs to

activate decoded output based on data inputs.
When any one enable input is unasserted, all
outputs of decoder are disabled.
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 DECODERS

Block diagram of decoders

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 DECODERS
2 : 4 Decoders

 A binary decoder is used when it is necessary to

activate exactly one of 2n outputs based on an n-
bit input value.

 Here the 2 inputs are decoded into 4 outputs,

each output representing one of the minterms of
the two input variables.

 As shown in the truth table, if enable input is 1

(EN= 1) only one of the outputs (Y0 – Y3), is
active for a given input.
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 DECODERS
2 : 4 Decoders

Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Truth table

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 DECODERS
2 : 4 Decoders

Logic Diagram
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 DECODERS
3 : 8 Decoders
 A 3-to-8 line decoder has three inputs (A, B, C)
and eight outputs (Y0- Y7). Based on the 3 inputs
one of the eight outputs is selected.

 This decoder is used for binary-to-octal

conversion. The input variables may represent a
binary number and the outputs will represent the
eight digits in the octal number system.

 The output line whose value is equal to 1

represents the minterm equivalent of the binary
number presently available in the input lines.
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 DECODERS
3 : 8 Decoders

Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Truth table

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 DECODERS
3 : 8 Decoders

Logic Diagram
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 DECODERS
Applications
 Instruction decoder is the part of the CPU

 Memory address decoding

 Decoder outputs can be used to drive a 7

segment display (TTL 74LS47)

 Binary Decoders such as binary or BCD ,decimal

or octal etc and commonly available decoder IC’s
(TTL 74LS138 3-to-8 line binary decoder or the
74ALS154 4-to-16 line decoder)
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 DECODERS
Cascading Decoders
 Example: Design a 4 to 16 line decoders
using 2 to 4 line decoders
 To implement 4:16 decoder we need five 2:4 line decoders.

 Decoder-1 is used to enable one of the decoder 2, 3, 4 and 5.

Inputs of the first decoders are A and B i.e. MSB inputs of 4:16
decoders.

 The inputs of decoders are connected together forming C and

D inputs of 4:16 decoders.

 When AB=00 decoder-1 is enabled, for AB=01 decoder-2 is

enabled, for AB=10 decoder-3 is selected, and for AB=11
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 DECODERS
Cascading Decoders

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 DECODERS
Realization of Boolean Expression using Decoders
 The combination of decoder and external logic
gates can be used to implement single or multiple
output function. The decoder can have one of the
two output states either active or active high.
 For active high output :
 SOP function implementation
 When the decoder output is active high it generates
minterms for input variables (i.e) it makes the selected
output logic1. In such cases to implement the sop
function we have to take sum of selected product
terms generated by decoder. This can be implemented
by ORing the selected decoder output.
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 DECODERS
Realization of Boolean Expression using Decoders

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 DECODERS
Realization of Boolean Expression using Decoders
 POS function implementation: When the decoder
output is active high POS function in similar manner as
per SOP function except function output is complemented.
This can be achieved by connecting NOR gates instead of
OR gates .

Single output function implementation using decoder and gate

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 ENCODERS

 An encoder is a combinational circuit that

converts binary information from 2n input lines to
a maximum of ‘n’ unique output lines.
 An encoder is a digital circuit that performs the
inverse operation of a decoder. Hence, the
opposite of the decoding process is called
encoding. The general structure of encoder circuit
is,

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 ENCODERS

 Generally, digital encoders produce outputs of 2-

bit, 3-bit or 4-bit codes depending upon the
number of data input lines.

 An "n-bit" binary encoder has 2n input lines and n-

bit output lines with common types that include 4-
to-2, 8-to-3 and 16-to-4 line configurations.

 The output lines of a digital encoder generate the

binary equivalent of the input line whose value is
equal to “1”.
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 ENCODERS
4 to 2 Encoder

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 ENCODERS
Priority Encoder

 One of the main disadvantages of standard digital

encoders is that they can generate the wrong
output code when there is more than one input
present at logic level "1".

 For example, if we make inputs D1 and D2 HIGH

at logic "1" both at the same time, the resulting
output is neither at "01" or at "10" but it will be at
"11" which is an output binary number that is
different to the actual input present.
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 ENCODERS
Priority Encoder

 One simple way to overcome this problem is to

"Priorities" the level of each input pin and if there
was more than one input at logic level "1" the
actual output code would only correspond to the
input with the highest designated priority.

 Then this type of digital encoder is known

commonly as a Priority Encoder or P-encoder
for short.

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 ENCODERS
Priority Encoder
 A priority encoder is an encoder circuit that includes
the priority function.

 In priority encoder, if two or more inputs are equal to

1 at the same time, the input having the highest
priority will take precedence. The higher the subscript
number, higher the priority of the input.
 Input D3, has the highest priority. So, regardless of
the values of the other inputs, when D3 is 1, the
output for xy is 11. D2 has the next priority level. The
output is 10, if D2= 1 provided D3= 0. The output for
D1 is generated only if higher priority inputs are 0, and
so on down the pr o
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209
 ENCODERS
4 to 2 Priority Encoder

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 ENCODERS
4 to 2 Priority Encoder

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 ENCODERS
4 to 2 Priority Encoder

4-Input Priority Encoder

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 ENCODERS
8 to 3 Priority Encoder

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 ENCODERS
Encoder Applications
(i) Keyboard Encoder
 Priority encoders can be used to reduce the number
of wires needed in a particular circuits or application
that have multiple inputs.

 For example, assume that a microcomputer needs to

read the 104 keys of a standard QWERTY keyboard
where only one key would be pressed either “HIGH”
or “LOW” at any one time.
 One way would be to connect all 104 wires from the
individual keys on the keyboard directly to the
computers input but this would be impossible for a
small home PC.
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 ENCODERS
Encoder Applications

 Another alternative and better way would be to

interface the keyboard to the PC using a priority
encoder.

 The 104 individual buttons or keys could be encoded

into a standard ASCII code of only 7-bits (0 to 127
decimal) to represent each key or character of the
keyboard and then input as a much smaller 7-bit
B.C.D code directly to the computer.

 Keypad encoders such as the 74C923 20-key

encoder are available to do just that.
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Decoder 2x4 (GL)
 2x4 decoder using Gate level model
module decoder_2_to_444(a,en,y);
input [1:0] a;
input en;
output [3:0]y;
wire [5:0]w;

not n1(w[0],a[0]);
not n2(w[1],a[1]);
and (w[2],w[0], w[1]);
and (w[3],w[1], a[0]);
and (w[4],a[1], w[0]);
and (w[5],a[0],a[1]);
and (y[0],en, w[2]);
and (y[1],en, w[3]);
and (y[2],en, w[4]);
and (y[3],en, w[5]);
endmodule
 2x4 decoder using Gate level model TB
////////////////////////////////

module decoder2x4gatelevel_tb();
reg [1:0]a;
reg en;
wire [3:0]y;
decoder2x4 uut (.y(y),.a(a),.en(en));
initial
begin
en=0; a= 2'b00; #100;
en=1; a = 2'b00; #100;
en=1; a = 2'b01; #100;
en=1; a = 2'b10; #100;
en=1; a = 2'b11; #100;
end
endmodule
 2x4 decoder using Data flow model

module decoder(d0,d1,d2,d3,e,a0,a1);
input e,a0,a1;
output d0,d1,d2,d3;
assign d3= (e&a1&a0);
assign d2= (e&a1&~a0);
assign d1= (e&~a1&a0);
assign d0= (e&~a1&~a0);
endmodule
Decoder 2x4 ( Data flow TB)
//////////////////
module test();
reg e,a0,a1;
wire d0,d1,d2,d3;
decoder mydecoder(d0,d1,d2,d3,e,a0,a1);
initial
begin
e=0; a0= 1'b1;a1=1'b1;
#100
e=1; a0= 1'b0;a1=1'b0;
#100
e=1; a0= 1'b0;a1=1'b1;
#100
e=1; a0= 1'b1;a1=1'b0;
#100
e=1; a0= 1'b1;a1=1'b1;
end
endmodule
Decoder 2x4 using behavioural level
module decoder2x4(y,a,en);
input [1:0]a;
output [3:0]y;
input en;
reg [3:0]y;
always @ (a, en)
if (en==0)
y=1'b0;
else
case (a)
2'b00:y=4'b0001;
2'b01:y=4'b0010;
2'b10:y=4'b0100;
2'b11:y=4'b1000;
default : y=1'bx;
endcase
endmodule
2x4 decoder using behavioural level test bench
////////////
module decoder2x4beh_tb;
reg [1:0]a;
reg en;
wire [3:0]y;
decoder2x4 uut (.y(y),.a(a),.en(en));
initial
begin
en=0; a= 2'b00; #100;
en=0; a = 2'b00; #100;
en=0; a = 2'b01; #100;
en=0; a = 2'b10; #100;
en=0; a = 2'b11; #100;

end
endmodule
 3x8 decoder using behavioural level

//Declare the Verilog module - The inputs and output port names.
module decoder3to8( Data_in, Data_out );
//what are the input ports and their sizes.
input [2:0] Data_in;
//what are the output ports and their sizes.
output [7:0] Data_out;
//Internal variables
reg [7:0] Data_out;
//Whenever there is a change in the Data_in, execute the always block.
always @(Data_in)
case (Data_in) //case statement. Check all the 8 combinations.
3'b000 : Data_out = 8'b00000001; 3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100; 3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000; 3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000; 3'b111 : Data_out = 8'b10000000;
//To make sure that latches are not created create a default value for output.
default : Data_out = 8'b00000000;
endcase
endmodule
3x8 decoder using behavioural level test ben

module tb_decoder;
// Declaring Inputs
reg [2:0] Data_in;
// Declaring Outputs
wire [7:0] Data_out;
// Instantiate the Unit Under Test (UUT)
decoder3to8 uut (
.Data_in(Data_in),
.Data_out(Data_out)
);
initial begin
//Apply Input and wait for 100 ns
Data_in = 3'b000; #100; Data_in = 3'b001; #100;
Data_in = 3'b010; #100; Data_in = 3'b011; #100;
Data_in = 3'b100; #100; Data_in = 3'b101; #100;
Data_in = 3'b110; #100; Data_in = 3'b111; #100;
end
endmodule
8x3 decoder using behavioural level
module encoder8to31122( Data_in,Data_out);

output reg [2:0] Data_out;

input [7:0] Data_in;

always @(Data_in)
case (Data_in)
8'h01 : Data_out = 3'b000;
8'h02 : Data_out = 3'b001;
8'h04 : Data_out = 3'b010;
8'h08 : Data_out = 3'b011;
8'h10 : Data_out = 3'b100;
8'h20 : Data_out = 3'b101 ;
8'h40 : Data_out = 3'b110;
8'h80 : Data_out = 3'b111;
default : Data_out = 3'bxxx;
endcase
endmodule
 Multiple Sources Selector Single Destination

MP3 Player
Docking Station

D0
Laptop
D1

MUX
Sound Card Y
D2

D3
Surround Sound System

Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
66
 De-Multiplexer

The De-Multiplexer is a combinational logic circuit that

performs the reverse operation of multiplexer (Several
output lines, one input line).
De -Multiplexer means one to many. A De-Multiplexer
is a circuit with one input and many output. By applying
control signal, we can steer any input to the output. Few
types of De -Multiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to
16 De -Multiplexer .
De-Multiplexer is the process of taking information
from one input and transmitting the same over one of
several outputs.
Verilog Code for 8:1 multiplexer
Structural Modeling
module m81(input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2, output
out);
wire T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11;
not(T1, S0);
not(T2, S1);
not(T3, S2);
and(T4, D0, T1, T2, T3), (T5, D1, S0, T2, T3);
and(T6, D2, T1, S1, T3), (T7, D3, S0, S1, T3);
and(T8, D4, T1, T2, S2), (T9, D5, S0, T2, S2);
and(T10, D6, T1, S1, S2), (T11, D7, S0, S1, S2);
or(out, T4, T5, T6, T7, T8, T9, T10, T11);
endmodule
Data Flow Modeling
module m81(output out, input D0, D1, D2, D3, D4,
D5,
D6, D7, S0, S1, S2);
assign S1bar=~S1;assign S0bar=~S0;assign
S2bar=~S2;
assign out = (D0 & S2bar & S1bar & S0bar) | (D1 &
S2bar & S1bar & S0) |
(D2 & S2bar & S1 & S0bar)
+ (D3 & S2bar & S1 & S0) + (D4 & S2 & S1bar &
S0bar) +
(D5 & S2 & S1bar & S0) + (D6 & S2 & S1 & S0bar) +
(D7 & S2 & S1 & S0);
endmodule
Behavioral Modeling
module m81(out, D0, D1, D2, D3, D4, D5, D6, D7,
S0, S1, S2);
input wire D0, D1, D2, D3, D4, D5, D6, D7, S0,
S1, S2;
output reg out;always@(*)begincase(S0 & S1 &
S2)3'b000: out=D0;
3'b001: out=D1;3'b010: out=D2;3'b011:
out=D3;3'b100: out=D4;
3'b101: out=D5;3'b110: out=D6;3'b111: out=D7;
default: out=1'b0;endcase
endendmodule
Verilog Code for Demultiplexer
module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);
always @(Y, A) begin case (A) 2'b00 : begin Y[0] = din;
Y[3:1] = 0; end 2'b01 : begin Y[1] = din; Y[0] = 0;
end 2'b10 : begin Y[2] = din; Y[1:0] = 0;
end 2'b11 : begin Y[3] = din; Y[2:0] = 0;
end
endcase
end
endmodule
Dataflow modeling
module Demultiplexer_1_to_4_assign(output [3:0] Y, input [1:0] A, input din);
assign Y[0] = din & (~A[0]) & (~A[1]);
assign Y[1] = din & (~A[1]) & A[0];
assign Y[2] = din & A[1] & (~A[0]);assign Y[3] = din & A[1] & A[0];
endmodule