Received: 30 September 2020 Revised: 13 December 2020 Accepted: 2 January 2021

DOI: 10.1002/cta.2944

O R I G I N A L PA P E R

Implementation of cascaded asymmetrical multilevel

inverter for renewable energy integration

Vishal Anand Varsha Singh

Department of Electrical Engineering,

National Institute of Technology Raipur, Summary
Raipur, India
This paper aims to develop a new cascaded asymmetrical multilevel inverter
Correspondence with less number of switches for photovoltaic power generation. The structure
Varsha Singh, Department of Electrical contains three sources and 11 switches. A design of proposed structure is sug-
Engineering, National Institute of
Technology Raipur, Raipur, Chhattisgarh
gested for PV application. A few more algorithms for cascade extension are also
492010, India. proposed to obtained maximum voltage levels using least numbers of switching
Email: [email protected] devices. PD LS-PWM modulation is used to control gate pulses of the switches.
The structure produce 15 levels using one inverter, whereas 85 levels using a
cascaded inverter. The magnitude of sources in cascade inverter is governed
by algorithms. A comparative assessment for optimal algorithm is developed
considering, sources, switches, and other performance parameters. The simula-
tion and hardware is performed for 15-level and 85-level asymmetrical inverter
for variation in modulation index and frequency. The efficiency of multilevel
inverter is evaluated using PSIM tool. The performance indices, power loss anal-
ysis, switching stresses, and blocking voltages across the switches are simulated
and validated. The cascade structure, 85 levels produce high quality waveform,
for which THD is less than 5%. Thus, this structure suits series combination of
various PV panels and achieve power utilising renewable energy sources.

K E Y WO R D S
cascaded multilevel inverter, cost function, harmonic minimization, power loss, reduced switches,
standing voltage, voltage stress

1 I N T RO DU CT ION

The multilevel inverter (MLI) gained its presence in industrial research and has found an excellent alternative for han-
dling the high-power circuits using nominal silicon semiconductor devices.1 An MLI is an electronic configuration of
semiconductor switches that provides desired alternating voltage utilizing a combination of switches in such a way that it
has low switching stresses. It enhances reliability and reduces the current ripple and voltage across the load that makes it
suitable for motor drives and renewable energy integration. This improves the harmonic profile and reduction in the size
of the filter in comparison to the normal two-level inverter.2 However, asymmetrical MLIs is capable to produce higher
voltage levels using basic unit. The cascaded structure provides a higher staircase output with minimal lower order har-
monics. Thus, these inverters find their applicability in electric drives/vehicles, reactive power compensation, and active
filter in renewable integration.3 The industrial loads like fans, blowers, and compressors are critical load. The hybrid MLIs
are the best way of meeting the load requirements.4 It is necessary to condense stresses, blocking voltages, and switching
losses. In any grid-tied inverter, proper synchronism is required along with high efficiency, low THD, high-quality power,
and low dv/dt stress across power switches.5,6 The MLI is conventionally classified into CHB, FC, and NPC. FC and NPC

Int J Circ Theor Appl. 2021;1–19. wileyonlinelibrary.com/journal/cta © 2021 John Wiley & Sons, Ltd. 1
2 ANAND AND SINGH

increase output voltage levels using floating capacitors and clamping diode, respectively. However, the shortcomings of
these topologies are the balancing and utilization of capacitors. In NPC structure, clamping is achieved by a diode that
has more reverse recovery time and leakage current as compared to power switches. These topologies are still preferred
in motor drive applications by both industries and academicians as it offers a low cost, have higher efficiency, and are
easy to control. CHB eliminates the drawbacks of NPC and FC by offering modular structure and high-quality output,
which utilizes isolated DC sources and results in being bulky and costly. The CHB half-bridge is widely used in HVDC
transmissions and motor drives. The drawbacks for CHB is a requirement for isolated power supplies. In order to fix the
issues as mentioned above, modern researchers have put desperate efforts to improve these conventional topologies with
hybrid topologies for MLI.7 However, this prototype suits high-frequency operation and renewable energy integration.
These hybrid inverters require a proper controlling PWM signal. The PWM technique that yields less THD is preferred.
The hybrid inverters aim for reduction in the cost of the inverter by a reduction in the semiconductor components devices
that are driven by the excellent control logic and advanced modulation schemes.8 The modern hybrid topologies use
capacitors as a source, few of which are self-balanced. In contrast, in others, a separate control algorithm is needed to
control voltage across capacitors using voltage sensors. The limitations for these topologies are higher capacitor ripples at
low switching frequency.9,10 These topologies are not preferred in high-power applications because increasing switching
frequency reduces the voltage ripples instead of reducing the efficiency of the inverter.
The symmetrical MLIs appear to be advantageous, offering lesser switching stresses, more redundant paths for achiev-
ing any particular levels, and easier to balance voltages across the switches. The asymmetrical MLIs have its benefits like
higher voltage levels and better harmonic profile, whereas it has higher blocking voltages, unequal stress across switches,
and nearly nil redundant paths in most of the cases suitable for renewable energy integration application.11,12 Thus, it
helps in obtaining highly efficient, excellent power quality with maximum output power. Traditional inverters used power
transformers that switches at low switching frequencies resulting in use of filters to lessen the lower order harmonics.13
The complexity and losses are significantly less; however, they need larger space and installation/maintenance cost for
medium voltage applications ranging from 6 to 36 kV.
The hybrid MLIs achieve higher output voltage levels either through increment in basic structure or cascaded repetition
of the particular structure. The cascaded structure with the outer H-bridge appears to be disadvantageous as the stresses
on these switches are very high. This limits its utility only for medium voltage applications.14 In Babaei et al.15 and Elias
et al.,16 multiple DC source-based multilevel converters are proposed that have lesser control complexity but lack the
ability to maintain higher efficiency at higher switching frequencies. These topologies can be extended but result in more
losses due to increase in switching devices. Another possible hybrid MLIs topologies have repetition in the basic unit.
The topologies with basic units help in increasing the number of levels with an increase in stress on arm switches. The
topologies mentioned above comprises the utilization of multiple sources to generate voltage levels. Proper loss analysis
and stresses across the switches are simulated and validated. However, the stresses across the switches is different. Thus,
it is necessary to have switches with higher blocking voltages for these topologies.17,18 In Choupan et al.19 and Samadaei
et al.,20 hybrid multilevel converters are proposed. These topologies mostly use critical research for extension of topology
using DC supply as well as switch capacitor subcell. These structures offer better cascade hybrid MLI extensions. However,
these topologies removed either have unequal stresses across switching devices or face difficulty in balancing power for AC
drive applications. The comparative study is done for many hybrid inverters and symmetrical and asymmetrical structures
with respect to the number of switches, DC sources, levels, maximum stress across switch, blocking voltages, and cost
function.21-31
With an eye to alleviate the drawback mentioned above, a new basic unit is proposed, and its algorithm is developed
for cascaded MLI to meet excellent quality waveform maintaining harmonic profile well under 5% for both voltage and
current waveform. The cascaded MLI is designed with reduced device count. Moreover, the cascaded inverter without
H-bridge has a greater number of switches, but there is a significant reduction in power loss and total blocking voltage. The
number of on-state switches is very less which helps in reducing the total loss of the proposed MLI. The proposed topology
can be used with renewable energy sources like photovoltaic (PV) power generation and fuel cell to get high-quality output
power. The salient features of the proposed topology are mentioned as follows:
1. The number of power devices used for generating 85 levels are 22 switches and six DC sources.
2. The voltage stress on the switches is reduced significantly, even at a higher rating.
3. The voltage THD of the cascaded structure is 0.34%, and the current THD is 0.13%, which adheres to IEEE 519
harmonic guidelines.
4. The arm switches operate at 50 Hz, which minimize the switching loss.
ANAND AND SINGH 3

The arrangement of research is presented in six sections. The proposed topology with its functionality, modes of oper-
ation, its extension, and comparison is presented in Section 2. Section 3 describes the modulation strategy. Section 4
describes the simulated results for the proposed basic unit for symmetrical, asymmetrical, and cascaded asymmetrical
MLI. Section 5 describes the power loss, efficiency, and hardware results, followed by a conclusion in Section 6.

2 ST RU CTURE O F ASYMMETRICAL MLI

The structure of the proposed basic unit is illustrated in Figure 1. This structure has three DC sources, seven unidirec-
tional switches, and two bidirectional switches. The bidirectional switch comprises of two IGBTs with anti-parallel diodes
connected back-to-back. This topology can generate seven levels with equal (symmetrical) sources, whereas it is possible
to generate more levels using asymmetrical sources in the same circuit. For symmetrical structures, all voltage sources
are the same, and redundant paths are available. For asymmetrical structure, there is no redundant path for peak levels,
as optimal utilization of DC sources and switches are preferred here to get higher output voltage levels.

2.1 Functionality of topology

The switching table for the proposed structure is described in Table 1. The basic topology and its switching pattern
for inverted negative cycle for the proposed are exemplified in Figure 1A,B respectively, and its modes of operation are
described in Figure 2. This topology has eight possible modes of operation using power switches and DC sources to gen-
erate several output voltages levels. In case of asymmetrical configuration, there are three possibilities where the DC
sources are configured as V1 :V2 :V3 = 1:2:2, V1 :V2 :V3 = 1:2:3, and V1 :V2 :V3 = 1:2:4 which generates 11, 13, and 15 levels,
respectively. The redundant paths for the first and second cases for DC sources are possible for lower voltage, whereas
there is no possibility for redundancy for 15 levels. The modes of operation is described in Figure 2. The corresponding
ON switches for each level generation is shown in Table 1. The bidirectional switches are made using the back-to-back
connection of switches in common emitter mode. This topology provides equal switching stress across complementary
pairs T1 and T6 , T2 and T5 , and T3 and T4 . Thus, the cascaded extended structure of proposed MLI has a constant cycle
of switching stress for attaining output voltage levels. There is no chance of an imbalance in voltage stresses across the
switches with proposed topology. Thus, it enhances the reliability of MLI.

2.2 Application of 15-level asymmetrical MLI

The industrial relevance/application of projected MLI structure in renewable energy system is preferable over the con-
ventional MLI, owing to its advantages like lesser components requirement, higher LCR (level per component ratio), and
lower standing voltage. Figure 3 shows that PV panels are interfaced to get 15 levels using above-mentioned topology. This
topology comprises of only DC sources; thus, the harmonic content of topology remain healthy. The PV sources are inte-
grated with DC–DC converters to get desired boost output voltage to build the DC link. The controller designed checks
the voltage of DC link and maintains constant voltage across it with the help of duty ratio control for DC–DC converter.
This methodology is inspired by high penetration of PVs as a renewable clean power generation. The overall efficiency

FIGURE 1 (A) Topology for asymmetrical multilevel inverter. (B) Switching pattern for 15 levels (inverted negative cycle) [Colour figure
can be viewed at wileyonlinelibrary.com]
4 ANAND AND SINGH

TABLE 1 Switching table for maximum Switching states Conducting switches VMagnitude Voltage levels
output voltage 1. T6 − T5 − T7 − T3 +(V1 + V2 + V3 ) +7VDC
2. T1 − T5 − T7 − T3 +(V2 + V3 ) +6VDC
3. T6 − T5 − P2 − T7 − T3 +(V1 + V3 ) +5VDC
4. T1 − T5 − P2 − T7 − T3 +(V3 ) +4VDC
5. T6 − T5 − P2 − T4 +(V1 + V2 ) +3VDC
6. T1 − T5 − P2 − T4 +(V2 ) +2VDC
7. T6 − T5 − T4 +(V1 ) +1VDC
8. T1 − T5 − T4 - 0VDC
9. T6 − T2 − T3 - 0VDC
10. T1 − T2 − T3 −(V1 ) −1VDC
11. T6 − T2 − P1 − T7 − T4 −(V2 ) −2VDC
12. T1 − T2 − P1 − T7 − T4 −(V1 + V2 ) −3VDC
13. T6 − T2 − T7 − P2 − T4 −(V3 ) −4VDC
14. T1 − T2 − T7 − P2 − T4 −(V1 + V3 ) −5VDC
15. T6 − T2 − T7 − T4 −(V2 + V3 ) −6VDC
16. T1 − T2 − T7 − T4 −(V1 + V2 + V3 ) −7VDC

FIGURE 2 Attainment of all levels for the proposed topology [Colour figure can be viewed at wileyonlinelibrary.com]

of the system is high by both the power converters. First, an efficient DC–DC converter maintains the desired DC link
voltage. Second, the DC link voltage is used in proposed MLI with efficient control strategy to harness maximum power
from renewable energy sources. In addition, the structure is compact, modular in comparison to CHB-MLI and many
other topologies. Moreover, the parameters like regulation of each DC link voltage, the operation of PV source at thresh-
old power point, power balancing throughout PV mismatch, and evaluation of real-time switching angles, all should be
taken into consideration during application of MLI. The operation uses V1 , V2 , V3 in the ratio of 1:2:4. Thus, adequate
power rating of panels are designed with MPPT algorithm and DC–DC converter with a closed loop controller helps to
maintain DC link voltage as required by the MLI topology.

2.3 Extension of proposed topology

The extension of the proposed topology can be done in two ways: first, increasing the inner subcell and second, cascad-
ing of the whole unit. The extension using the inner subcell increases the stress on the arm switches (T1 –T6 ) whereas
extending the whole cascaded unit provides better switching stress on arm switches. Therefore, the cascaded unit of the
proposed inverter is preferred over the increment in subcell. The cascaded unit extension of the proposed structure is
ANAND AND SINGH 5

FIGURE 3 Photovoltaic application for the asymmetrical multilevel inverter, analogy, and control strategy [Colour figure can be viewed at
wileyonlinelibrary.com]

FIGURE 4 Cascaded extension of the

proposed topology

exemplified in Figure 4. Each cascaded structure is considered as one basic cell. Similarly, the basic cascaded cell which
when repeated forms n basic cells. The switching table for the cascaded unit is listed in Table 2.
The notation used in this article for the number of sources is NSource , the number of switches is denoted by NSwitch , and
the number of the gate driver is NDriver .
NSource = 3n, (1)

NSwitch = 11n, (2)

NDriver = 9n, (3)

where n represents the number of basic cells.
The standing voltage or blocking voltage is significant constraint for estimating the cost of the MLI. Blocking voltage is
expressed as voltage that a switch can withstand during the OFF state. Thus, if the blocking voltage of a particular inverter
is low, the rating of switch required for the design of the inverter also reduces. In the generalized structure depicted in
 6

TABLE 2 Switching table for maximum output voltage for cascaded extension
T11 T12 T13 T14 T15 T16 T17 P11 P12 … Tn1 Tn2 Tn3 Tn4 Tn5 Tn6 Tn7 Pn1 Pn2 VO
∑n
0 0 1 0 1 1 1 0 0 … 0 0 1 0 1 1 1 0 0 k=1 (V1,k + V2,k + V3,k )
… … … … … … … … … … … … … … … … … … … …
0 0 1 0 1 1 1 0 0 … 0 0 1 0 1 1 1 0 0 V1 + V2 + V3
1 0 1 0 1 0 1 0 0 … 1 0 1 0 1 0 1 0 0 V2 + V3
0 0 1 0 1 1 1 0 1 … 0 0 1 0 1 1 1 0 1 V1 + V3
1 0 1 0 1 0 1 0 1 … 1 0 1 0 1 0 1 0 1 V3
0 0 0 1 1 1 0 0 1 … 0 0 0 1 1 1 0 0 1 V1 + V2
1 0 0 1 1 0 0 0 1 … 1 0 0 1 1 0 0 0 1 V2
0 0 0 1 1 1 0 0 0 … 0 0 0 1 1 1 0 0 0 V1
1 0 0 1 1 0 0 0 0 … 1 0 0 1 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0 … 1 1 1 0 0 0 0 0 0 −(V1 )
0 1 0 1 0 1 1 1 0 … 0 1 0 1 0 1 1 1 0 −(V2 )
1 1 0 1 0 0 1 1 0 … 1 1 0 1 0 0 1 1 0 −(V1 + V2 )
0 1 0 1 0 1 1 0 1 … 0 1 0 1 0 1 1 0 1 −(V3 )
1 1 0 1 0 0 1 0 1 … 1 1 0 1 0 0 1 0 1 −(V1 + V3 )
0 1 0 1 0 1 1 0 0 … 0 1 0 1 0 1 1 0 0 −(V2 + V3 )
1 1 0 1 0 0 1 0 0 … 1 1 0 1 0 0 1 0 0 −(V1 + V2 + V3 )
… … … … … … … … … … … … … … … … … … … …
∑n
1 1 0 1 0 0 1 0 0 … 1 1 0 1 0 0 1 0 0 − k=1 (V1,k + V2,k + V3,k )
ANAND AND SINGH
ANAND AND SINGH 7

Figure 4, the configuration has symmetric blocking voltages across pairs of switches T1, 1 and T6, 1 , T2, 1 and T5, 1 , and T3, 1
and T4, 1 . Similarly, the blocking voltages across the switches in cascade configuration will vary according to the choice in
the magnitude of input voltage. The blocking voltages across T1, 1 and T6, 1 , T2, 1 and T5, 1 , and T3, 1 and T4, 1 are represented
as
VT1,1 = VT6,1 = V1,1 , (4)

VT2,1 = VT5,1 = V3,1 + V2,1 + V1,1 , (5)

VT3,1 = VT4,1 = V2,1 + V1,1 , (6)

V3,1 + V2,1
VT7,1 = , (7)
2
VP1,1 = V2,1 , (8)

VP2,1 = V3,1 . (9)

Total blocking voltage for symmetrical and asymmetrical MLI is computed as

VBV,1 = BV of(VT1,1 + VT2,1 + VT3,1 + VT4,1 + VT5,1 + VT6,1 + VT7,1 + VP1,1 + VP2,1 ). (10)

For symmetrical structure,

V1,1 = V2,1 = V3,1 = 1 V, (11)

VBV,1 = (1 + 3 + 2 + 2 + 3 + 1 + 1 + 1 + 1) = 15 V. (12)
For asymmetrical structure,
V1,1 ∶ V2,1 ∶ V3,1 = (1:2:4) V, (13)

VBV,1 = (1 + 7 + 6 + 6 + 7 + 1 + 3 + 2 + 4) = 38 V. (14)
Similarly, the blocking voltages for the “nth” cascaded structure are represented as

VT1,n = VT6,n = V1,n , (15)

VT2,n = VT5,n = V3,n + V2,n + V1,n , (16)

VT3,n = VT4,n = V2,n + V1,n , (17)

V3,n + V2,n
VT7,n = , (18)
2
VP1,n = V2,n , (19)

VP2,n = V3,n . (20)

Total blocking voltage for symmetrical and asymmetrical MLI is computed as

VBV,1 = BV of(VT1,n + VT2,n + VT3,n + VT4,n + VT5,n + VT6,n + VT7,n + VP1,n + VP2,n ), (21)

(TBV) = (VBV,1 + VBV,2 + … + VBV,n ). (22)

In demand of a greater number of levels, it is very essential to choose the magnitude of DC supply for maximum voltage
levels. Table 3 lists algorithms for different combinations of DC sources that yields all possible number of levels from the
proposed circuit. This table also presents an analytical expression for a generalized variety of DC sources represented by
(NVariety ), blocking voltages by (TBV), the maximum output voltage (Vo, max ), and the number of levels (NLevels ).
In Figure 5, the percentage stress across the switches in seven-level inverter (symmetrical) and 15-level inverter (asym-
metrical) is exemplified, respectively. The switching stresses across switches for the same topology varies when operated
in symmetrical and asymmetrical conditions. The switching stress are more in asymmetrical condition, but it is tolerable
as switches used in the inverter are capable to withstand that blocking voltages during off state. The primary objective of
presenting the cascaded MLI is to increase the output voltage levels utilizing minimal number of power semiconductor
devices. Although there are numerous options of cascading the structure, this cascade structure uses lesser number of
8 ANAND AND SINGH

TABLE 3 Algorithms proposed for generalized asymmetrical MLI

Algorithm Variety Magnitude of DC sources Nlevels Vo, max TBV
A1 1 V1𝑗 = V2𝑗 = V3𝑗 = 1 V 6n + 1 (3n)V (15n)V
𝑗 = 1, 2, 3 … , n
A2 2 V11 = V21 = V31 = 1 V 12n − 5 (6n − 3)V 15(2n − 1)V
V1𝑗 = V2𝑗 = V3𝑗 = 2 V
𝑗 = 2, 3 … , n
A3 2 V11 = V21 = V31 = 1 V 18n − 11 (9n − 6)V 15(3n − 1)V
V1𝑗 = V2𝑗 = V3𝑗 = 3 V
𝑗 = 2, 3 … , n
A4 3 V1𝑗 = 1V, V2𝑗 = 2V, V3𝑗 = 4 V 14n + 1 (7n)V (38n)V
𝑗 = 1, 2, 3 … , n
7(3n −1)
A5 3n V11 = 1V, V21 = 2V, V31 = 4 V 7(3n − 1) + 1 2
V 19(3n − 1 )V
V1𝑗 = 3V1( 𝑗−1) , V2𝑗 = 3V2( 𝑗−1) , V3𝑗 = 3V3( 𝑗−1)
𝑗 = 2, 3 … n
14(4n −1)+3 14(4n −1) 38 n
A6 3n V11 = 1V, V21 = 2V, V31 = 4 V 3 3
V 3
(4 − 1)V
V1𝑗 = 4V1( 𝑗−1) , V2𝑗 = 4V2( 𝑗−1) , V3𝑗 = 4V3( 𝑗−1)
𝑗 = 2, 3 … n
7(5n )−5 7(5n −1) 38 n
A7 3n V11 = 1V, V21 = 2V, V31 = 4 V 2 4
V 3
(5 − 1)V
V1𝑗 = 5V1( 𝑗−1) , V2𝑗 = 5V2( 𝑗−1) , V3𝑗 = 5V3( 𝑗−1)
𝑗 = 2, 3 … n

FIGURE 5 Percentage stress

across switches in seven-level
(symmetrical) and 15-level
(asymmetrical) inverter [Colour
figure can be viewed at
wileyonlinelibrary.com]

switches, gate drivers, DC sources, and blocking voltages within the permissible limit. Therefore, it is possible to obtain
improved output voltage waveform and maintaining excellent power quality using cascaded structure.
Figure 6A exhibits a relative usage of sources for several proposed algorithms vis-a-vis the number of levels. It appears
that A1 (symmetrical) algorithm utilizes the maximum number of sources, whereas the A7 algorithm uses the minimum
number of sources to attain the same output levels. Figure 6B exhibits a relative usage of switches for several proposed
algorithms concerning the number of levels. It appears that A1 (symmetrical) algorithm utilizes the maximum number
of switches, whereas the A7 algorithm uses the minimum number of switches to attain the same output levels. Figure 6C
exhibits a maximum output voltage for several proposed algorithms based upon the number of levels. It appears that
A1 (symmetrical) algorithm has a lesser maximum output voltage, whereas the A5 and A7 algorithms have a much bet-
ter maximum output voltage to attain the same output levels. Figure 6D exemplifies a total standing voltage for several
proposed algorithms with respect to the number of levels. It appears that the number of levels is dependent on the loga-
rithmic function of voltage sources. Choosing the best one out of the proposed algorithms is a tough choice to make other
than choosing A5. It can be seen that variety of DC sources for algorithms A5, A6, and A7 is more to generate higher out-
put voltage levels. Thus, only few cascade extension is preferred, after which switches cannot withstand these standing
voltages.

2.4 Optimal considerations

The optimal consideration for multilevel converter depends on the design parameters. This section emphasizes on
consideration about DC sources, switches, and gate drivers to get best optimal benefits. The optimal utilization of
ANAND AND SINGH 9

FIGURE 6 (A) Algorithm comparison for DC sources versus levels. (B) Algorithm comparison for switches versus levels. (C) Algorithm
comparison for maximum output voltage versus levels. (D) Algorithm comparison for standing voltage versus levels [Colour figure can be
viewed at wileyonlinelibrary.com]

above-mentioned parameters helps to make the multilevel converter modular. It strictly depends upon user and its appli-
cations to operate the inverter with symmetrical or asymmetrical configuration. For symmetrical multilevel converter, A1
produces output voltage levels using the same voltage sources. The number of switches, DC sources, and gate drivers for
the operation of the converter are listed in Equations (1)–(3), respectively.

2.4.1 Optimal parameters for symmetrical configuration

This consideration mainly aims to determine the number of basic units n using the minimum number of switches for
obtaining a specific number of levels.
NSwitch = 2(NLevels ) − (n − 2). (23)

This equation shows that the number of switches are dependent on the number of levels and the number of basic units
used in proportion to the number of switches and the number of gate driver is another parameter that helps the switches
in attaining the desired voltage levels.
NDriver = NLevels − (3n − 1), (24)

The total standing voltage based on number of basic units and number of levels is expressed as

Vstanding,n = 2(NLevels ) − (3n + 2). (25)

The normalized standing voltage can give an overview of relationship to yield maximum output voltage levels using
minimum number of voltage sources.
[ ]
2(NLevels ) − 2
Normalized(Vstanding,total ) = (Vstanding,1 ). (26)
Vstanding,1 − 3

Figure 7A shows the comparative parameter for the design of inverter with optimal parameters when all the DC sources
are equal. This figure clearly shows that a higher number of basic units produce more voltage levels. This also shows
a comparative analysis for the normalized gate driver and normalized total standing voltage. It is clear that with an
increase in the magnitude of voltage sources, there is a significant increase in the standing voltage. This voltage must
be within the maximum permissible blocking voltage of the switch. The maximum output voltage levels obtained using
10 ANAND AND SINGH

FIGURE 7 (A) Optimal structures and comparative parameters for symmetrical structure using A1. (B) Optimal structures and
comparative parameters for asymmetrical structure using A4. (C) Optimal structures and comparative parameters for asymmetrical cascaded
structure using A7 [Colour figure can be viewed at wileyonlinelibrary.com]

fixed parameters like number of levels or number of basic units is expressed as

(NLevels − 1)
Vo,max = = 3n. (27)
2

2.4.2 Optimal parameters for asymmetrical configuration

There are many possibilities for number of levels using asymmetrical DC sources. Considering asymmetrical DC sources
as in A4, the objective is to achieve maximum voltage levels using constant number of switches and gate drivers.
The maximum number of levels obtained with constant number of switches can be expressed as

NSwitch = NLevels − (3n + 1). (28)

The maximum number of levels obtained with constant number of drivers can be expressed as

NDrivers = (NLevels − 1) − 5n. (29)

Similarly, the number of DC sources is another important parameter that fixes the maximum number of levels. The
maximum number of levels using number of DC sources is expressed as

[ ]
(NLevels − 1)
Nsource = (3n). (30)
14
ANAND AND SINGH 11

3(N −1)
This expression gets minimum value when the factor Levels 14
is minimum. The total standing voltage based on the
number of basic units and the number of levels is expressed as

Vstanding,n = 2(NLevels ) + (10n − 2). (31)

The normalized total standing voltage is expressed as

[ ]
2(NLevels ) − 2
Normalized(Vstanding,total ) = (Vstanding,1 ). (32)
Vstanding,1 − 10

Figure 7B shows the comparative parameter for the design of inverter with optimal parameters when the DC sources
varies as stated in A4. This concludes that higher levels are obtained with minimal increment in basic unit with utilization
of switches to get better output waveform.

2.4.3 Optimal parameters for cascaded asymmetrical configuration

The optimal cascaded asymmetrical structure for A7 attains the maximum number of levels using a number of switches,
gate drivers, and so on. The maximum number of levels obtained with constant number of switches can be expressed as

[ ( )]
2(NLevels ) + 5
NSwitch = 11 log5 . (33)
7

The maximum number of levels obtained with constant number of drivers can be expressed as

[ ( )]
2(NLevels ) + 5
Ndrivers = 9 log5 . (34)
7

Similarly, the minimum number of sources used to produce maximum voltage levels are expressed as

[ ( )]
2(NLevels ) + 5
Nsources = 3 log5 . (35)
7

The maximum output voltage levels can be expressed with maximum voltage levels as

( )
⎛ log2 2(NLevels )+5 ⎞
7
⎜ −1⎟
⎜ log5 ⎟
5⎝ ⎠
Vo,max = 7 × . (36)
4

The normalized voltage for obtaining maximum voltage level is expressed as

( )
1
Normalized(Vstanding,total ) = (5n − 1).(Vstanding,1 )
4 ( )
2(NLevels )+5
⎛ log2 7 ⎞ (37)
1
= × ⎜5 − 1⎟ × Vstanding,1 .
log 5

4 ⎜ ⎟
⎝ ⎠

Figure 7C shows the comparative parameter for the design of inverter with optimal parameters when the DC sources
varies as stated in A7. It is concluded that higher levels are obtained with very little increment in basic unit, but the
standing voltage is increasing at a very fast rate. Thus, it is desirable to use this algorithm with only two to three basic
units.
12 ANAND AND SINGH

FIGURE 8 (A) Comparison of switches versus levels. (B) Comparison of drivers versus levels. (C) Comparison of sources versus levels. (D)
Comparison of total standing voltage versus levels [Colour figure can be viewed at wileyonlinelibrary.com]

3 CO MPARING WITH EXISTING TO POLOGIES

The comparative analysis signifies the potential of the proposed multilevel converter with the recently developed topolo-
gies. CHB structure has equal blocking voltage stresses on each switch. The same levels can be obtained by utilizing
comparatively more switches though the switches have minimal stress. The circuit complexity and cost of these inverters
increases due to usage of more number of switches, gate drivers, and other peripherals.
Figure 8A exemplifies the comparison between the number of levels versus a number of switches. It is inferred that the
conventional topologies, CHB, use more switches to attain the levels. The topologies13,14,17,20,23,24,27-31 uses more number
of switches than the proposed inverter to attain the same number of voltage levels.
Figure 8B exemplifies the number of a gate drivers versus the number of levels. The gate driver is significant, as it builds
the required voltage across the power switches during turn ON and OFF of switches due to sudden change in the PWM
signal from the user-defined control logic. A circuit must use a lesser gate driver to reduce the complexity in the design of
a multilevel converter. The proposed topology has two bidirectional switches. These switches have bidirectional voltage
blocking and conduction capabilities. The control of the bidirectional switch requires only one gate-driver circuit. Thus,
reducing the circuit complexity. The structure14,15,17,20,23,24,27,28,30 uses relatively more drivers than proposed circuit.
Figure 8C exemplifies the number of sources versus the number of levels. The switched capacitor topologies have a
lesser number of DC sources than the topologies with only DC sources. But the advantage of using DC sources is main-
taining constant voltage across the output. This indicates low voltage ripples for both low switching frequencies and high
switching frequencies for the operation of the multilevel converter. It is evident that some topologies uses more number
of DC sources to attain the same number of voltage levels.14,17,20,22-24,27,28,30
Figure 8D exemplifies the total standing voltage versus the number of levels. The cost of the MLI depends upon the uti-
lization of power switches to its standing voltage capabilities. It is administered that the standing voltage of the proposed
inverter is less than that existing in literature.14,20-22,24,27-30
The cost of the MLI depends upon the number of components (switches, gate drivers, sources, and DC link) and blocking
voltage of power switches used in the design. The other important parameter that rules the investment cost in the design
of MLI is the current coefficient. The current coefficient factor signifies the amount of current flowing through the power
switches. The current coefficient is denoted by 𝛿. Usually, the value of 𝛿 is taken to be between 0.5 and 1.5 for low current
and high current applications, respectively. The cost function of a multilevel is expressed as

[ ( )]
NSource
CF = NSwitch + NDriver + 𝛿 × TBV × , (38)
NLevels
ANAND AND SINGH 13

where NSwitch is the number of switches, NDriver is the number of drivers, NSource is the number of DC sources, NLevels is the
number of levels, and TBV is the total blocking voltage.
The comparative analysis for the proposed multilevel and its performance parameter is visible from Table 4. It is seen
that generating 15 levels29-31 uses more than three DC supply. The number of switch to level ratio signifies the utilization
of switch for generating each level. It found that the proposed topology has very less switch to level ratio for almost all
the cited references. Since the number of switch used for topology is less, the gate driver requirement also decreases. The
DC link requirement for the topology is nearly the same as existing topology. The total blocking voltage is also very less.
The cost function at 𝛼 = 0.5 and 𝛼 = 1.5 is 7.8 and 15.4, respectively. This suggests that cost for generating level for the
cost function parameters 𝛼 = 0.5 and 𝛼 = 1.5 is better.23-31

4 S I M UL ATION R E SU LT S

The proposed asymmetrical MLI topology is simulated in MATLAB. The inverter performance is checked for both low
switching frequency, high switching frequency, and change in modulation index. The simulation result for asymmetrical
structure for 15 levels is exemplified in Figure 9A when DC sources are chosen as V1 = 8 V, V2 = 16 V, and V3 = 32 V,
respectively. The load current and voltage waveform for the variation in frequency from 100 Hz to 5 kHz is observed at
t = 0.01 s for pure resistive load, 50 Ω and inductive load, 50 Ω and 220 mH (Power Factor 0.6), respectively. The change
in modulation index is simulated at resistive load, R = 50 Ω. The MI is maintained as 1.0 from t = 0 to 0.04 s; 0.8 from
t = 0.04 to 0.08 s; 0.6 from t = 0.08 to 0.12 s; 0.4 from t = 0.12 to 0.16 s; and 0.2 from t = 0.16 to 0.2 s. It is seen that the
output voltage and current vary proportionately according to the change in modulating wave. The performance of MLI
topologies is observed in waveform and harmonic profile of the output voltage and current. The LS-PWM has different
schemes that yields different output voltage. The PD yields best results for RMS voltages and has better harmonic profile.
The same modulation scheme is applied for the asymmetrical cascade structure that yields 85 levels, which is exemplified
in Figure 9B when DC source is chosen as V11 = 8 V, V21 = 16 V, V31 = 32 V, V21 = 40 V, V22 = 80 V, and V32 = 160 V for
load R = 50 Ω and inductive load, R = 50 Ω and L = 220 mH (Power Factor 0.6). These condition are simulated under
variation in frequency from 100 Hz to 5 kHz at t = 0.1 s. The change in modulation index is simulated by change MI as
1.0, 0.8, 0.6, 0.4, and 0.2 for R = 50 Ω at 100 Hz. Thus, the simulation results produce better quality waveform which is
validated on experimental prototype to find its applicability and feasibility.
The MLI design depends on voltage and current rating of power switches. A high-power inverter design requires several
switches that are connected in series, but this is not feasible due to uneven voltage stresses on switches. Thus, for the
design of a high-power inverter, it is necessary to choose switches with higher operating voltages. The voltage and current
rating of the inverter are determined such that switches operate safely. The safety factor (𝛽) is usually considered 10–20%
of the rating of the inverter. Considering the safety factor (𝛽) to be 10%. The VA rating of the inverter is given as

( ) ( )
Vm,inverter Im,inverter
Sm,inverter = ×
𝛽 𝛽
( ) (39)
Vm,inverter × Im,inverter
= .
𝛽2

TABLE 4 Performance comparison with existing literature

21 22 23 24 25 26 27 28 29 30 31
Parameters Proposed
NLevels 7 7 7 11 13 13 13 13 15 15 15 15
NSources 2 2 3 5 2 3 6 4 4 4 7 3
NSwitches
NLevels
0.857 0.857 2.14 1.10 0.92 1.23 1.07 0.76 1.33 0.83 1.2 0.73
NDriver
NLevels
0.857 0.857 2.14 1.10 0.46 0.61 1.07 0.61 0.8 0.73 1.2 0.6
NDC
Link
NLevels
0.285 0.285 0.14 0.10 0.15 0.23 0.08 0.30 0.267 0.2 0.67 0.2
BVMax 3 3 7 8 3 7 7 57 15 7 7 7
TBV 12 12 38 40 24 42 58 20 90 44 42 38
CF (𝛿 = 0.5) 5.14 5.14 21.00 20 4.61 10.38 26.30 8.61 20.53 15.14 26.60 7.8
CF (𝛿 = 1.5) 8.57 8.57 37.29 38.182 8.30 20.07 46.20 14.76 44.53 28.57 46.20 15.4
14 ANAND AND SINGH

FIGURE 9 (A) Simulation results for asymmetrical 15-level inverter using combination (V1 :V2 :V3 = 8 V:16 V:32 V) at switching frequency
100Hz and 5 kHz: (i) pure resistive load 50 Ω, (ii) inductive load 50 Ω and 220 mH, and (iii) modulation index varies from 1.0, 0.8, 0.6, 0.4, and
0.2. (B) Simulation results for asymmetrical cascaded 85-level inverter using combination (V11 :V21 :V31 = 8 V:16 V:32 V;
V21 :V22 :V32 = 40 V:80 V:160 V) at switching frequency 100 Hz and 5 kHz afterwards: (i) pure resistive load 50 Ω, (ii) inductive load 50 Ω and
220 mH, and (iii) modulation index varies from 1.0, 0.8, 0.6, 0.4, and 0.2 [Colour figure can be viewed at wileyonlinelibrary.com]

FIGURE 10 Power loss (in %) across various switches for a 15-level

inverter [Colour figure can be viewed at wileyonlinelibrary.com]
ANAND AND SINGH 15

FIGURE 11 (A) Performance of PSIM versus hardware prototype. (B) Efficiency and power with respect to change in modulation index.
(C) Efficiency comparison for other 15-level inverter [Colour figure can be viewed at wileyonlinelibrary.com]

Switches PSwitching (W) PConduction (W) Total losses (W) TABLE 5 Power loss for a 15-level inverter in PSIM
T1 2.761 3.150 5.911
T2 2.100 0.240 2.340
T3 0.725 0.634 1.359
T4 0.735 0.643 1.378
T5 0.217 0.246 0.463
T6 2.771 3.167 5.938
T7 0.664 0.241 0.905
P1 0.670 0.243 0.913
P2 0.657 0.239 0.896
Total losses 20.103
Output power 1000
Efficiency 97.98%

TABLE 6 Equipment used for hardware justification

Component Name Specifications
Gate driver HPCL-3120E
IGBT FGH25N120FTDS
Controller d-SPACE 1104
Mixed digital oscilloscope TEKTRONIX MDO-58
Regulated DC power supply RS-HMP4030P (V11 = 8 V; V21 = 16 V; V31 = 32 V) Keysight-N8900 (V12 = 40 V; V22 = 80 V; V32 = 160 V)
Load 50 Ω (Unity Power Factor); 50 Ω, 220 mH (0.6 Lagging Power Factor)
Switching frequency 100 Hz and 5 kHz
Prototype levels 15 and 85
Rated power 1.2 and 6.7 kW

For the switch used in the experiment, the maximum drain to source voltage is 1200 V and drain to source current is
25 A. Considering safety factor 𝛽 = 1.1. The calculated rating of proposed inverter is given below:
( )
1200 × 25
Sm,inverter = = 24.793 kVA.
(1.1)2

5 POWER LOSS, EFFICIENCY, AND H ARDWARE VALIDATION

The power loss and efficiency of the proposed MLI is computed considering both the switching and conduction losses.
The conduction losses have three stages, namely, ON to OFF state, OFF to ON state, and conduction state. The percentage
of loss by each switch for 15-level inverters is exhibits in Figure 10.

PLoss = PConduction + PSwitching , (40)

16 ANAND AND SINGH

( ) ( )
2
PConduction = Vt × ICE,avg + RCE,ON × IDS,rms , (41)

PSwitching = PSwitch,ON + PSwitch,OFF , (42)

( )
VBV × ICE,ON × TON × 𝑓Switching
PSwitch,ON = , (43)
6
( )
VBV × ICE,OFF × TOFF × 𝑓Switching
PSwitch,OFF = . (44)
6
The expression for efficiency is
( )
Po
𝜂= , (45)
Po + losses
where Po is the output power.
The power loss of the proposed MLI is computed in PSIM considering V1 = 8 V, V2 = 16 V, and V3 = 32 V at unity MI.
The comparative study for the efficiency of simulation and hardware results can be seen in Figure 11A. The experiment
for PD-LSPWM is repeated at different modulation index. The power ratings for both input and outputs are monitored
on an experimental setup to evaluate the efficiency of the proposed inverter. Thus, the power rating and efficiency of
MLI is dependent upon the modulation index. The power rating and efficiency of MLI is exemplified in Figure 11B. It
is inferred that the MLI has 97.98% efficiency in PSIM whereas the efficiency on experimental prototype is close to 95%.
The efficiency of the proposed structure is higher than existing 15-level inverter listed in Figure 11C (Table 5).

FIGURE 12 (A) Waveform for load current and voltage for 15-level asymmetrical inverter for pure resistive load of 50 Ω. (B) Waveform for
load current and voltage for 15-level asymmetrical inverter for inductive load of 50 Ω, 220 mH, or PF = 0.6. (C) Voltage harmonic profile is
15-level asymmetrical inverter at R = 50 Ω, L = 220 mH, or PF = 0.6. (D) Current harmonic profile is 15-level asymmetrical inverter at
R = 50 Ω, L = 220 mH, or PF = 0.6. (E) Waveform for load current and voltage for change in MI for 15-level asymmetrical inverter at
R = 50 Ω [Colour figure can be viewed at wileyonlinelibrary.com]
ANAND AND SINGH 17

The experimental prototype is composed of IGBT and its gate driver and other experimental equipment listed in Table 6.
The logic for SPWM is developed using d-SPACE 1104 RTI controller. The hardware results for asymmetrical (15 levels)
inverter is exemplified in Figure 12. This experiment is performed at V1 = 8 V; V2 = 10 V, and V3 = 32 V. The result for the
asymmetrical inverter for resistive load R = 50 Ω, inductive load R = 50 Ω and L = 220 mH, and change in MI = 1.0 to 0.2
after every 0.04 s for two cycles successively for pure resistive load R = 50 Ω is exemplified in Figure 12A,B,E, respectively.
The voltage and current THD for R = 50 Ω and L = 220 mH are 6.3% and 2.3%, which is exemplified in Figure 12C,D,
respectively. The cascaded asymmetrical MLI (85 levels) is exemplified in Figure 13. The cascaded asymmetrical structure
for the proposed inverter is realized using voltage source as in A7 V11 = 8 V; V21 = 16 V; V31 = 32 V; V12 = 40 V; V22 = 80 V;
and V32 = 160 V. The result for the asymmetrical cascaded inverter for resistive load R = 50 Ω, inductive load R = 50 Ω
and L = 220 mH, and modulation index varied from MI = 1.0 to 0.2 after every 0.04 s for two cycles successively for pure
resistive load R = 50Ω is exemplified in Figure 13A,B,E, respectively. The voltage and current THD for R = 50 Ω and
L = 220 mH are exemplified in Figure 13C,D, respectively. The voltage THD is 0.3%, whereas current THD is 0.1% within
IEEE 519 guidelines. In the FFT analysis, the harmonic order that are impacted are labeled as red whereas as green for
healthy condition. The experimental prototype is shown in Figure 14. Thus, the performance of the proposed MLI is
validated for both resistive and inductive loads on a manual varying load for 1 kW. The efficiency for the MLI varies from
94% to 96% on experimental setup at different load conditions.

FIGURE 13 (A) Waveform for load current and voltage for 85-level asymmetrical inverter for pure resistive load of 50 Ω. (B) Waveform for
load current and voltage for 85-level asymmetrical inverter for inductive load of 50 Ω, 220 mH, or PF = 0.6. (C) Voltage harmonic profile is
85-level asymmetrical inverter at R = 50 Ω, L = 220 mH, or PF = 0.6. (D) Current harmonic profile is 85-level asymmetrical inverter at
R = 50 Ω, L = 220 mH, or PF = 0.6. (E) Waveform for load current and voltage for change in MI for 85-level asymmetrical inverter at
R = 50 Ω [Colour figure can be viewed at wileyonlinelibrary.com]
18 ANAND AND SINGH

FIGURE 14 Experimental prototype [Colour figure can be viewed at wileyonlinelibrary.com]

6 CO N C LU S I O N

A novel single-phase cascaded MLI has been proposed. The proposed topology can be operated with low and high switch-
ing frequency. There are various algorithms for the cascaded asymmetrical structure that can be integrated with multiple
renewable energy sources. The key advantages of the proposed topology states that while the device count is reduced,
higher number of levels and better harmonic profile is achieved. This can be seen from the comparative analysis. The
cascaded structure is validated under experimental setup, and the waveform quality, harmonic profile for both current
and voltage is under harmonic standards. It is found that efficiency for simulation is 97.8% whereas it varies on the
experimental setup from 94% to 96% at 1000-W power at load.

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How to cite this article: Anand V, Singh V. Implementation of cascaded asymmetrical multilevel inverter for
renewable energy integration. Int J Circ Theor Appl. 2021;1-19. https://doi.org/10.1002/cta.2944