GAT_EEE_NBA_MC_15EE52_CO_2017-18
GAT_EEE_NBA_MC_15EE52_CO_2017-18
GAT_EEE_NBA_MC_15EE52_CO_2017-18
COURSE OUTCOMES
CO. Bloom’s No. of
Course Outcomes Program Outcomes
NO. Levels Sessions
On completion of this course, students are able to
CO Understand the features of 8051 family members and the internal architecture Understand PO1,PO2,PSO3
10
1 of the 8051.
Describe 8051 assembler, the stack and the flag register, loop, jump, and call Understand
CO PO1,PO2,PO5, PSO3
instructions, addressing modes, accessing data and I/O port programming, 10
2
arithmetic, logic instructions, and programs.
Understand 8051 programs for time delay, I/O operations, I/O bit Understand 10
CO PO1,PO2,PO5, PSO3
manipulation, logic and arithmetic operations, data conversion and data
3
serialization.
Interpret the hardware connection of the 8051 chip, its timers, serial data Understand 10 PO1,PO2,PO5,PO12
CO
communication and its interfacing of 8051 to the RS232 and detail 8051 PSO3
4
interrupts and writing interrupt handler programs.
Interface 8051 with real-world devices such as LCDs and keyboards, ADC, DAC Understand 10 PO1,PO2,PO5,PO12
CO
chips and sensors, 8051 with external memories, 8255 chip to add ports and PSO3
5
relays, opt isolators and motors.
CO-PO Mapping
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 3 2 1
CO2 3 2 2 2
CO3 3 2 2 2
CO4 3 2 2 1 2
CO5 3 2 2 1 2
15EE52 3 2 2 1 2