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    Model Co Paper Mae

    Uploaded by

    Shashank Rao
    The document is a model question paper for the subject Computer Organization. It contains 20 multiple choice or short answer questions in Part A and 5 long answer questions in Part B with internal choice. Part A is compulsory and carries 20 marks while Part B questions carry 16 marks each and students must answer all of them. The questions in Part A cover topics like CPU registers, memory addressing, data representation, instruction execution, cache performance, I/O devices, assembly language programming and logic design. Part B questions require explanations of computer architecture concepts like functional units, instruction execution, bus structures, assembly directives, stacks, memory organization, cache mapping, DMA and floating point representation.

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    Model Co Paper Mae

    Uploaded by

    Shashank Rao
    82 views4 pages
    The document is a model question paper for the subject Computer Organization. It contains 20 multiple choice or short answer questions in Part A and 5 long answer questions in Part B with internal choice. Part A is compulsory and carries 20 marks while Part B questions carry 16 marks each and students must answer all of them. The questions in Part A cover topics like CPU registers, memory addressing, data representation, instruction execution, cache performance, I/O devices, assembly language programming and logic design. Part B questions require explanations of computer architecture concepts like functional units, instruction execution, bus structures, assembly directives, stacks, memory organization, cache mapping, DMA and floating point representation.

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    The document is a model question paper for the subject Computer Organization. It contains 20 multiple choice or short answer questions in Part A and 5 long answer questions in Part B with internal choice. Part A is compulsory and carries 20 marks while Part B questions carry 16 marks each and students must answer all of them. The questions in Part A cover topics like CPU registers, memory addressing, data representation, instruction execution, cache performance, I/O devices, assembly language programming and logic design. Part B questions require explanations of computer architecture concepts like functional units, instruction execution, bus structures, assembly directives, stacks, memory organization, cache mapping, DMA and floating point representation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    82 views4 pages

    Model Co Paper Mae

    Uploaded by

    Shashank Rao
    The document is a model question paper for the subject Computer Organization. It contains 20 multiple choice or short answer questions in Part A and 5 long answer questions in Part B with internal choice. Part A is compulsory and carries 20 marks while Part B questions carry 16 marks each and students must answer all of them. The questions in Part A cover topics like CPU registers, memory addressing, data representation, instruction execution, cache performance, I/O devices, assembly language programming and logic design. Part B questions require explanations of computer architecture concepts like functional units, instruction execution, bus structures, assembly directives, stacks, memory organization, cache mapping, DMA and floating point representation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Department of Computer Science and Engineering R.V.

    College of Engineering, Bangalore Computer Organization (Model question paper)


    Time:3 Hrs Subject Code: 10CS34 Max Marks:100 Part A includes Question No 1 consisting of fill up the blanks/short type question only, it is compulsory and it carries 20 marks Part B consists of 5 questions each carrying 16 marks with internal choice, answer all of them.

    PART A
    1. 2. For SPEC 95, the reference computer for evaluation is ______________ (1 marks)

    If the value stored in R1 = 1300, which is a memory address of LOCA. If the contents of PC is 1200 at point executing branch instruction. Calculate the effective address to be load in PC which branch condition is true. Assume that every instruction takes a word length in memory. LOOP : MUL R3, #10 ADD R3, #3030 Mov (R1), R4 Branch >0 LOOP (1 marks)

    3. 4.

    Using 2s Complement, subtraction, of (1010)2 from (0011)2 is

    (1 marks)

    If the ASCII code for A is 1000001, B is 1000010, and C is 1000011 then the string 100001110000011000010 represents: (1 marks)

    5.

    When a subroutine is called, the address of the instruction following the CALL instructions stored in__________________ (1 marks)

    6.

    If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving an average memory access of 2 cycles? (1 marks)

    7.

    How many 32K x 1 RAM chips are needed to provide a memory capacity of 256 K bytes (1 marks) (1 marks)

    8. 9.

    CPU to handles the interrupt by executing interrupt service routine

    The branch logic that provides decision making capabilities in the control unit is known as (1 marks)

    10. 11.

    Lines that can only transmit in one direction are called ___________

    (1 marks)

    What is it called when no I/O is in progress and the CPU has all the bus to itself and a running I/O requests and is granted the bus when it needs it? (1 marks)

    12.

    The -5 number is storing in memory in one byte. Represent it in memory for little endian (2s complement) -_______________ (1 marks)

    13.

    What is the average access time of a system having three levels of memory hierarchy: a cache memory, a semiconductor main memory, and magnetic disk secondary memory. The access times of these memories are 20 ns, 200 ns, and 2 ms, respectively. The cache hit ratio is 80 per cent and the main memory hit ratio is 99 per cent.
    (1 marks)

    14. 15. 16. 17.

    What is the data transfer rate for USB 2.0. Perform the subtraction on the number : 12 and 8 Represent 0.0023 x 10^-3 using single precision format.

    (1 marks) (1 marks) (1 marks)

    The branch logic that provides decision making capabilities in the control unit is known as (1 marks)

    18.

    Using longhand method, perform the operation A x B on the given 5-bit unsigned number A=10101 ,B=00101 (1 marks) (1 marks)

    19.

    Write the following sequence of code into MIPS assembler: x = x + y + z - q; Assume that x, y, z, q are stored in registers Consider the following assembly code r1 = 99 Loop: r1 = r1 1 branch r1 > 0, Loop halt

    20.

    (1 marks)

    During the execution of the above code, how many dynamic instructions are executed?

    PART B 1. a. Explain different functional units of a digital computer. b. List the steps needed to execute the machine instruction Add LOCA, R0 c. What is bus ? Explain single bus structure in an architecture
    OR

    (5 marks) (6 marks) (5 marks)

    2. a. Convert the following pairs of decimal numbers to 5-bit,signed,2s complement, binary Numbers and add them. State whether or not overflow occurs in each case. i) -14 and 11 ii) -10 and -13 (2*2 marks) b. Write assembly language program to solve the expression Ax^2+Bx+c (6 marks) c. An integer of 32 bit size is stored in memory location in the little endian fashion. Indicate using a pseudo program, how a big endian 16 bit processor could rearrange the number and store it properly for its use, back in the same location. (6 marks) 3. a. What are assembler directives? Explain different addressing (6 marks) b. Explain with an assembly language program , usage of stacks in nested subroutine call. (4 marks) c. Register R1 and R2 of a computer contains the decimal value 1300 and 4700.What is the effective address of the memory operand in each of the following instruction. (3*2 marks) i) Load 20(R1),R5 ii) Move #3000,R5 iii) Subtract (R1)+,R5 OR 4. a. Explain how interrupt request from several I / O devices can be communicated to a processor through a single INTR line. (6 marks) b. Differentiate between subroutine and interrupt service routine. (4 marks) c. Explain the hardware registers that are required in a DMA controller chip? Explain the bus arbitration process used for DMA (6 marks) 5. a. Explain the general features of interfacing a parallel I/O port to a processor. (10 marks) b. Explain the significant features of the following buses. (3*2 marks) i) PCI ii) SCSI OR 6. a. How read and write operation takes place in 1K x 1 memory? (6 marks) b. Describe SDRAM and DDR SDRAM operations for data transfer between main memory and cache memory systems. (10 marks ) 7. a. Explain any two cache mapping functions. (6 marks) b. Design a 4M x 32 module using 512K x 8 memory chips. Show the address lines and control signals required . ( 10 marks) OR

    8. a. Explain about Single-bus organization of processor. ( 8 marks) b. Write the control sequence for the operation Sub R2, R3, R4 for three bus organization of the processor. ( 8 marks ) 9. a. Show how to implement a full adder using half-adders and external logic gates.(10 marks) b. Explain the IEEE standards for floating point number. Represent the following decimal numbers using IEEE standard floating point notation . i) +1.725 ii) -25.125 iii) -0.08125 (6 marks) OR 10. a. Explain about IEEE standard representation of floating -point numbers. b. Explain how to build 16 bit carry-look ahead (adder) from 4 bit adders.

    . (8 marks)
    (8 marks )

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