Course Code : MCS-012

Course Title : Computer Organization and Assembly

Language Programming
Assignment Number : BCAOL(II)/012/Assignment/2023-24
Maximum Marks : 100
Weightage : 25%
Last Dates for Submission : 31st October, 2023 (For July Session)
30th April, 2024 (For January Session)

There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for
viva voce. You may use illustrations and diagrams to enhance the explanations. Please go
through the guidelines regarding assignments given in the Programme Guide for the
format of the presentation. The answer to each part of the question should be confined to
about 300 words. Make suitable assumptions, if any.

Q1. (a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of the Instruction execution example.
Assuming a similar machine is to be used for the execution of the following three consecutive
instructions:

LODA A ; Load the content of Memory location A into the Accumulator Register.
ADD B ; Add the content of memory location B from Accumulator Register.
STOR C ; Stores the content of Accumulator register to memory location C.
However, this machine is different from the example of Figure 4 in the following ways:

Each memory word of this new machine is of 16 bits in length.

Each instruction is of length 32 bits with 16 bits for operation code (opcode) and 16 bits for
specifying one direct operand.
The Main Memory of the machine would be of size 216 words.
The three consecutive instructions are placed starting from memory location (11FE)h ;
operand A is at location (1FFF)h and contains a value (4321)h, Operand B is at location
(2000)h and contains a value (1FFE)h and operand C is at location (2001)h and contains a
value (0000)h.
The AC, PC, MAR and MBR registers are of size 16 bits, whereas IR register is of size 32
bits. The initial content of the PC register is (11FE)h.

Draw the diagrams showing the following information:

(i) Initial State of the machine with the addresses and content of memory locations in
hexadecimal. Show only those address locations of the memory that store the instruction and
data. Also show content of all the stated registers. (2)

(ii) Draw three more diagrams, each showing the state of machine after execution of every
instruction viz. LOAD, ADD and STOR. Show the changes in the values of Registers and
memory locations, if any, due to execution of instruction. Show all the addresses and values
in hexadecimal notations. (3)

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(b) Perform the following conversion of numbers: (2)
i) Decimal (345654398)10 to binary and hexadecimal
ii) Hexadecimal (FFEEDDCBA)h into Octal.
Computer Organisation
iv) Octal (6754632)O into Decimal
(c) Simplify the following function using K- 1, 3, 4, 7, 11, 13)
Draw the circuit for the resultant function using NAND gates. (2)
(d) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how
this circuit will perform subtraction (A-B), if the value of A is 1011 and B is 0011. You must list
all the bit values including Cin and Cout and overflow, if any. (1)

(e) Explain the functioning of a 3 × 8 decoder with the help of logic diagram and example input. (2)

(f) Assume that a source data value 1011 was received at a destination as 1010. Show how
Hamming's Error-Correcting code bits will be appended to source data to identified and correct
the error of one bit at the destination. You may assume that transmission error occurs only in the
source data and not the source parity bits. (2)

(g) Explain the functioning of the D flip-flop and the T flip-flop with the help of a logic diagram and
characteristic table. Also, explain the excitation table of this flip-flop. (2)

(h) Explain the functioning of the edge-triggered flip-flop with the help of a diagram. (2)

(i) Represent (-121.25)10 and (0.0625)10 in IEEE 754 single precision and double precision formats. (2)

Q2. (a) Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of an
8×8 RAM. Explain all the Input and Output of this organisation. Also answer the following:
(2)

(i) How many data input and data output lines does this RAM needs? Explain your answer.
(ii) How many address lines are needed for this RAM? Give reason in support of your answer.
(b) A computer has 64 K Word RAM with each memory word of 16 bits. It has cache memory
having 32 blocks having a size of 32 bits (2 memory words). Show how the main memory
address (1AFC)h will be mapped to the cache address, if (3)
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii)Two way set associative cache mapping is used.
You should show the size of tag, index, main memory block address and offset in your answer.

(c) What is an Interrupt? Why are interrupts used in a computer? Explain different kinds of
interrupts. Also, explain the process of interrupt processing. (3)

(d) What is an I/O processor? Explain the selector channel structure in the context of the I/O
processor. How is an I/O processor different from DMA? (2)

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 (e) Assume that a disk has 32 tracks, with each track having 16 sectors and each sector is of size
512 Kilobytes. The cluster size in this system can be assumed to be as 2 sectors. A file having
the name mcs012.txt is of size 16 MB. Assume that it is a new disk, and the first 8 clusters are
occupied by the Operating System. Rest all the clusters are free. How can this file be allotted
space on this disk? Also, show the content of FAT after the space allocation to this file. You
may make suitable assumptions. (4)

(f) Explain the following, giving their uses and advantages/disadvantages, if needed. (6)
(Word limit for answer of each part is 50 words ONLY)
(i) Rotational Latency in disks
(ii) Programmed I/O
(iii) Resolution of Display and Printer
(iv) Zip Drive
(v) Power Supply
(vi) Keyboard and Mouse

Q3. (a) A single-core uniprocessor system has 8 General purpose registers. The machine has RAM of
size 64K memory words. The size of every general-purpose register and memory word is 16
bits. The computer uses fixed-length instructions of size 32 bits each. An instruction of the
machine can have two operands. One of these operands is a direct memory operand and the
other is a register operand. An instruction of a machine consists of bits for operation code, bits
for memory operand and bits of register operand. The machine has about 128 different
operation codes. The special purpose registers, which are other than general purpose registers,
are - Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag
registers (FR). The first register among the general-purpose registers can be used as
Accumulator Register. The size of Integer operands on the machine may be assumed to be
equal to the size of the accumulator register. To execute instructions, the machine has another
special register called Instruction Register (IR) of size 32 bits, as each instruction is of this
size. Perform the following tasks for the machine. (Make and state suitable assumptions, if
any.)

(i) Design suitable instruction formats for the machine. Specify the size of different fields that are
needed in the instruction format. Also, indicate how many bits of the instructions are unused for
this machine. Explain your design of the instruction format. Also, indicate the size of each
register. (3)

(ii) Demonstrate two valid instructions of the machine; put some valid data values in registers and
memory locations and show these two instructions. (2)

(iii) Assuming that the instructions are first fetched to the Instruction Register (IR), the memory
operand is brought to the DR register and the result of an operation is stored in the Accumulator
register; write and explain the sequence of micro-operations that are required to fetch and
execute an addition instruction that adds the contents of the memory and register operands of
the instruction. The result is stored in the accumulator register. Make and state suitable
assumptions, if any. (5)

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 (b) Assume that you have a machine, as shown in section 3.2.2 of Block 3 having the micro-
operations given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8-bit
registers and contain 11100111 and 00111100 respectively. What will be the values of select
inputs, carry-in input, and the result of the operation (including carry-out bit) if the following
micro-operations are performed? (For each micro-operation you may assume the initial value
of R1 and R2 as given above) (2)
(i) Decrement R1
(ii) Add R1 and R2 with Carry
(iii) Exclusive OR of the registers R1 and R2
(iv) Shift right R1

(c) Consider that an instruction pipeline has three stages namely instruction fetch and decode (FD),
Operand Fetch (OF) and Instruction Execute and store results (ES). Draw an instruction
pipeline diagram showing the execution of five sequential instructions using this pipeline. What
are the problems with this instruction pipelining? (3)

(d) Explain the functioning of the Wilkes Control Unit. Also, explain the format of the control
memory with the help of a diagram. (2)

(e) Explain the characteristics of RISC? Also, explain the RISC pipelining. (3)

Q4. (a) Write a program using 8086 assembly Language (with proper comments) that accepts three
different digits as input from the keyboard. Each digit is first converted to a binary equivalent.
The binary values of these three digits are compared and the middle value is put in the AL
register. This AL register is multiplied with each value of a byte array of size 6, which is stored
in the memory. The result of the multiplication is stored in the same memory location. You may
assume the byte array has the values 02h, 06h, 08h, 03h, 01h, 05h. Make suitable assumptions,
if any. (7)

(b) Write a NEAR subroutine using 8086 assembly Language (with proper comments) that returns
the average value of the values stored in a byte array of length 3. All three values of the byte
array are passed to the subroutine in the stack. You should write both the calling program and
subroutine. (7)

(c) Explain the following in the context of 8086 Microprocessor with the help of an example or a
diagram: (6)
(i) Use of code segment and stack segment registers for computing the respective 20-bit
addresses.
(ii) Any 4 flags of the flag register of 8086 micro-processor
(iii) Any four shift instructions of 8086 micro-processor

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