Ordering number : ENN7900B

Bi-CMOS IC

LV23002M For Radio Cassette and Mini Component System

1-chip Tuner IC Incorporating PLL
Overview
The LV23002M is a one-chip tuner IC incorporating PLL for radio cassette and mini component system.

Features
• AM
• FM-FE
• FM-IF
• MPX
• PLL

Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VCC max VCC 7.0 V
VDD max VDD 5.0 V
Maximum input voltage VIN1 max CE, DI, CL 5.0 V
VIN2 max XIN VDD+0.3 V
Maximum output voltage VO1 max DO 6.0 V
VO2 max XOUT, PD VDD+0.3 V
VO3 max BO1, BO2, AOUT 12.0 V
Allowable power dissipation Pd max Ta≤70°C Mounted on a glass epoxy board.
400 mW
Board size : 114.3 mm×76.1mm = 1.6mm
Operating temperature Topr -20 to +70 °C
Storage temperature Tstg -40 to +125 °C
Note : This product should be handled with care because the resistance of one pin against electrostatic discharge damage is
low.

72905 MS IM B8-8314,B8-6787 / 81004 JO IM No.7900-1/13

 LV23002M
Operating Condition at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage VCC 5.0 V
VDD 3.0 V
Operating supply voltage range VCC op 4.0 to 6.0 V
VDD op 2.5 to 3.6 V
Note : Use the product with the supply voltage applied to VCC and VDD.

PLL block Allowable Operating Range at Ta = -20 to +70°C, VSS = 0V

Ratings
Parameter Symbol Conditions Unit
min typ max
Supply voltage VDD 2.5 3.6 V
Input high level voltage VIH CE, CL, DI 0.7VDD 5.0 V
Input low level voltage VIL CE, CL, DI 0 0.3VDD V
Output voltage VO1 DO 0 6.0 V
VO2 BO1, BO2, AOUT 0 10 V
Operating frequency fIN1 XIN ; VIN1 75 kHz
fIN2 FMIN ; VIN2 10 160 MHz
fIN3 AMIN (SNS = 1) ; VIN3 2 40 MHz
fIN4 AMIN (SNS = 0) ; VIN4 0.5 10 MHz
Note : Due attention must be paid on leak because the XIN pin has an extremely high input impedance.

Operating Characteristics at Ta = 25°C, VCC = 5.0V, VDD = 3.0V, See the specified circuit.
Ratings
Parameter Symbol Conditions Unit
min typ max
[FM-FE characteristics] : fc = 98MHz, fm = 1kHz, 22.5kHzdev.
3dB sensitivity 3dB LS 60dBµV EMF, 30%mod output reference, dBµV
3
-3dB input EMF
Actual sensitivity QS S/N = Input at S/N = 30dB dBµV
10
EMF
[FM-IF monaural characteristics] : fc = 10.7MHz, fm = 1kHz, 75kHzdev.
Demodulation output VO 100dBµV, 12pin output 270 330 400 mVrms
Channel balance CB 100dBµV, 13pin output /12pin output -1.5 0 +1.5 dB
Signal-to-noise ratio S/N 100dBµV, 12pin output 68 75 dB
Total harmonic distortion THD 100dBµV, 12pin output
0.3 1.5 %
(Monaural)
3dB sensitivity 3dB LS VO reference, Input level at which VO
38 44 dBµV
reference is -3dB.
IF count sensitivity IF-C3 SDC0 = 1, SDC1 = 0,18pin(DO) output 47 52 58 dBµV
Mute attenuation Mute-Att 100dBµV, 12pin output 68 dB
[FM-IF stereo characteristics] : fc = 10.7MHz, fm = 1kHz, L+R = 90%, Pilot = 10%, VIN = 100dBµV
Separation SEP L-mod, 12pin output /13pin output 28 40 dB
Total harmonic distortion (Main) THD Main-mod, 12pin output 0.5 1.5 %
Continued on next page.

No.7900-2/13
 LV23002M
Continued from preceding page.
Ratings
Parameter Symbol Conditions Unit
min typ max
[AM characteristics] : fc = 1000kHz, fm = 1kHz, 30%mod
Detection output 1 VO1 23dBµV, 12pin output 25 40 80 mVrms
Detection output 2 VO2 80dBµV, 12pin output 80 110 145 mVrms
Signal-to-noise ratio 1 S/N1 23dBµV, 12pin output 15 20 dB
Signal-to-noise ratio 2 S/N2 80dBµV, 12pin output 47 54 dB
Total harmonic distortion THD 80dBµV, 12pin output 1.2 3.0 %
IF count sensitivity IF-C 18pin (DO) output 22 28 33 dBµV
Low-range attenuation LOW-CUT VO2 reference, Pin 12 output at fm = 100Hz 5 8 11 dB
[Current dissipation]
Current dissipation ICCFM No input in FM mode 20 30 40
ICCAM No input in AM mode 10 20 30 mA
IDD fr = 83MHz, X’tal = 75kHz, No input to tuner 1 2 5
[PLL characteristics]
Internal return resistance Rf XIN 8 MΩ
Built-in output resistance Rd XOUT 250 kΩ
Hysteresis width VHIS CE, CL, DI 0.1VDD V
Output high level voltage VOH PD ; IO = -1mA VDD-1.0 V
Output low level voltage VOL1 PD ; IO = 1mA 1.0 V
VOL2 BO1, BO2 ; IO = 1mA 0.25 V
BO1, BO2 ; IO = 5mA 1.25 V
VOL3 DO ; IO= 1mA 0.25 V
VOL4 AOUT ; IO = 1mA, AIN = 2.0V 0.5 V
Input high level current IIH1 CE, CL, DI ; VI = 6.0V 5.0 µA
IIH2 XIN ; VI = VDD 0.16 0.9 µA
IIH3 AIN ; VI = 6.0V 200 nA
Input low level current IIL1 CE, CL, DI ; VI = 0V 5.0 µA
IIL2 XIN ; VI = 0V 0.16 0.9 µA
IIL3 AIN ; VI = 0V 200 nA
Output off-leak current IOFF1 BO1, AOUT, BO2 ; VO = 10V 5.0 µA
IOFF2 DO ; VO = 6.0V 5.0 µA
“H” level 3-state off-leak current IOFFH PD ; VO = 6.0V 0.01 200 nA
“L” level 3-state off-leak current IOFFL PD ; VO = 0V 0.01 200 nA

No.7900-3/13
 3263

DI

DI
unit : mm

(1) IN mode

(2) IN2 mode

0 P0
1 P1
0 P2
(9)O-PORT BO1 P3
(4)IFSW IFSW P4
Package Dimensions

Address
Address
(9)O-PORT B02 P5
(5)BDSW BDSW1 P6

1 0 0 1 0 1 0 0
0 0 0 1 0 1 0 0
(14)STSW STSW P7
(15)SDC0 SDC0 P8
DOC0 (1)P-CTR P9
(6)DO-C DOC1 P10
DOC2 P11
UL0 P12
(7)UNLOCK
UL1 P13
DZ0 P14
(8)DZ-C
DZ1 P15
GT0 SNS
(3)IF-CTR
GT1 DVS
LV23002M

Composition of DI control data (serial data input)

(16)SDC1 SDC1 (3)IF-CTR CTE
(10)PD-C DLC (13)Don’t care DNC
(11)IFS IFS R0
TEST0 R1
(2)R-CTR
(12)TEST TEST1 R2
TEST2 R3

No.7900-4/13
 LV23002M
Description of DI control Data
No. Control block data Description Related data
(1) Programmable • Data to set the dividing number of programmable divider
divider data Binary value with P15 assued to be MSB. LSB varies according to DVS and SNS.
(*: don’t care)
P0 to P15
DVS, SNS DVS SNS LSB Set dividing number(N) Actual dividing number

1 * P0 272 to 65535 Twice the set value

0 1 P0 272 to 65535 Set value
0 0 P4 4 to 4095 Set value

* P0 to P3 invalid when LSB:P4

• To select the signal input (FMIN, AMIN) to the programmable divider and to change the
input frequency range.
(*: don’t care)

DVS SNS Input Operation frequency range

1 * FMIN 10 to 160MHz
0 1 AMIN 2 to 40MHz
0 0 AMIN 0.5 to 10MHz

(2) Reference divider • Reference frequency (fref) selection data

data R3 R2 R1 R0 Reference frequency
0 0 0 0 25kHz
R0 to R3 0 0 0 1 25kHz
0 0 1 0 25kHz
0 0 1 1 25kHz
0 1 0 0 12.5kHz
0 1 0 1 6.25kHz
0 1 1 0 3.125kHz
0 1 1 1 3.125kHz
1 0 0 0 5kHz
1 0 0 1 5kHz
1 0 1 0 5kHz
1 0 1 1 1kHz
1 1 0 0 3kHz
1 1 0 1 15kHz
1 1 1 0 PLL INHIBIT+X’tal OSC STOP
1 1 1 1 PLL INHIBIT

* PLL INHIBIT
• The programmable divider and IF counter stop, with FMIN, AMIN, and IFIN inputs being in
the pull-down condition (GND), and the charge pump has the high impedance.
(3) IF counter control • IF counter counting start data
data CTE = 1: Counting start
= 0: Counting reset
CTE • Determines the counting time of universal counter
GT0, GT1
GT1 GT0 Counting time Wait time IFS
0 0 4ms 3 to 4ms
0 1 8 3 to 4
1 0 16 3 to 4
1 1 32 3 to 4

Continued on next page.

No.7900-5/13
 LV23002M
Continued from preceding page.
No. Control block data Description Related data
(4) MUTE control data • Data to determine the output of output port IFSW, controlling the MUTE function.
IFSW “Data” = 0: at receiving
1: MUTE
(5) FM/AM BAND • Data to determine the output of output port BDSW, controlling selection of BAND.
selection “Data” = 0: AM
control data 1: FM
BDSW
(6) DO pin control data • Data to control DO pin output
DOC2 DOC1 DOC0 DO pin condition
DOC0
0 0 0 Open
DOC1
0 0 1 Low when unlock is detected.
DOC2 end-UC (See the item with asterisk below)
0 1 0
0 1 1 Open

1 0 0 Open
1 0 1 Low when SDON
1 1 0 Low when stereo
1 1 1 Open

• The open condition is selected at power ON/reset.

UL0, UL1
* IF counter counting end check
CTE

DO pin

(2)Counting end (3)CE: HI

(1)Counting start

(1) With end-UC set and IF counter starting (CTE=0→1), DO pin opens automatically.
(2) At end of counting of the IF counter, DO pin goes LOW and check on counting end can be
made.
(3) DO pin opens when serial data is entered/output (CE pin: Hi)
Note: DO pin is always in the open condition during data input (IN1 and IN2 modes, during
CE: Hi period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition
during data output (OUT mode, CE-Hi period), the content of internal DO serial data is
output in synchronization with CL, regardless of DO pin control data (DOC).
(7) Unlock detection • Phase error (φE) detection width selection data to judge if PLL is locked.
data Phase error exceeding the detection width is judged that PLL is locked
(*:don’t care)
DOC0
UL0, UL1 UL1 UL0 φE Detection width Detection output
DOC1
0 0 Stop Open
DOC2
0 1 0 Direct output of φE
1 * ±6.67µ φE extended by 1 to 2ms
* DO pin is LOW. Serial data output: UL = 0.
(8) Phase comparator • Data to control the dead zone of phase comparator
control data DZ1 DZ0 Dead zone mode
0 0 DZA
DZ0, DZ1 0 1 DZB
1 0 DZC
1 1 DZD
Dead zone width: DZA<DZB<DZC<DZD
(9) Output port data • Data to determine the output of output ports BO1 and BO2
“Data” = 0: OPEN
BO1, BO2 1: Low

Continued on next page.

No.7900-6/13
 LV23002M
Continued from preceding page.
No. Control block data Description Related data
(10) Charge pump control • Data to enforce control of charge pump output
data DLC Charge pump output
0 Normal
DLC 1 Forced to LOW
In case of dead lock because of VCO oscillation stop when the VCO control voltage (Vtune)
is 0V, it is possible to clear dead lock by setting the charge pump output to LOW and V tune
to VCC. (Dead lock clear circuit)
(11) IFS • Normally, set Data = 1. Setting Data = 0 causes the input sensitivity worsening mode and
the sensitivity decreases by about 10 to 30mVrms.
(12) LSI test data • LSI test data
TEST0 to 2 TEST0
TEST1 All to be set to “0”
TEST2
All set to zero at power ON/reset
(13) DNC • Set data = 0.
(14) Forced monaural • Data to determine the output of output port STSW, controlling the forced stereo functions.
control data “Data” = 0: MONO
1: STEREO
STSW
(15) SD sensitivity control • Data to determine the output of output ports SDC0 and SDC1, controlling the SD sensitivity
(16) data “Data” = SDC0: 0, SDC1: 0 → SD sensitivity = 42dBµV (typ)
SDC0: 0, SDC1: 1 → SD sensitivity = 45dBµV (typ)
SDC0 SDC0: 1, SDC1: 0 → SD sensitivity = 51dBµV (typ)
SDC1 SDC0: 1, SDC1: 1 → SD sensitivity = 56dBµV (typ)

DO control data (serial data output) composition

(1) OUT mode

Address

DI 0 1 0 1 0 1 0 0
SDIND
STIND

DO
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
UL

C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
0
(1)IN-PORT

(3)IF-CTR

Description of the DO output data

No. Control block data Description Related data
(1) Stereo and SD • Data latching stereo and SD indicator conditions.
indicators Latching made in the data output (OUT) mode.
control data STIND←Stereo indicator condition 0: ST ON, 1: ST OFF
SDIND←SD indicator condition 0: SD ON, 1: SD OFF
STIND, SDIND
(2) PLL unlock data • Data latching the content of unlock detection circuit
UL0
UL ← 0: At unlock
UL1
UL 1: At lock or detection stop mode
(3) IF counter, binary • Data latching the content of IF counter (20-bit binary counter)
CTE
counter C19 ← MSB of binary counter
GT0
C0 ← LSB of binary counter
GT1
C19 to C0

No.7900-7/13
 LV23002M
Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75µs tLC < 0.75µs

(1) CL: Normally HI

tEL tES tEH

CE

CL

tSU tHD
DI B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3
tLC
Internal data

(2) CL: Normally LOW

tEL tES tEH

CE

CL

tSU tHD
DI B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3
tLC
Internal data

Serial data output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75µs tDC, tDH < 0.35µs

(1) CL: Normally Hi

tEL tES tEH

CE

CL

tSU tHD
DI B0 B1 B2 B3 A0 A1 A2 A3
tDC tDC tDH
DO I2 I1 UL C3 C2 C1 C0

No.7900-8/13
 LV23002M
(2) CL: Normally low

tEL tES tEH

CE

CL
tSU tHD
DI B0 B1 B2 B3 A0 A1 A2 A3
tDC tDC tDH
DO I2 I1 UL C3 C2 C1 C0

(Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up
resistance and substrate capacity.

Serial data timing

VIH
CE VIL
tCH tCL
VIH VIH VIH
CL VIL VIL VIL

VIH VIH tEL tES tEH

DI
VIL VIL
tSU tHD tDC tDC tDH

DO

tLC
Internal data latch Old New

<< When CL stops at the “L” level >>

VIH
CE VIL
tCH tCL

VIH VIH VIH

CL VIL VIL

VIH VIH tEL tES tEH

DI
VIL VIL
tSU tHD tDC tDH

DO

tLC
Internal data latch Old New

<< When CL stops at the “H” level >>

No.7900-9/13
 LV23002M

Parameter Symbol Pin Conditions min typ max unit

Data setup time tSU DI, CL 0.75 µs

Data hold time tHD DI, CL 0.75 µs
Clock “L” level time tCL CL 0.75 µs
Clock “H” level time tCH CL 0.75 µs
CE wait time tEL CE, CL 0.75 µs
CE setup time tES CE, CL 0.75 µs
CE hold time tEH CE, CL 0.75 µs
Data latch change time tLC 0.75 µs
tDC DO, CL Differs depending on the pull-up resistance and
Data output time 0.35 µs
tDH DO, CE substrate capacity

No.7900-10/13
 +B

FM
Block Diagram

VDD

B.P.F

AM
Low-cut
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

LPF POWER ON
GND2 VCC2 VDD
FM AM RESET
OSC OSC
FM
PHASE DETECTOR REFERENCE
RF CHARGE PUMP DEVIDER
SD ST TRIG ST SW FF VCO
OSC
BUFFER PROGRAMMABLE SW AL LOW
DIVIDER COUNTER UNLOCK
FM PILOT FF FF PHASE MUTE DETECTOR
AGC
S-METER DET COMP

DATA SHIFTREGISTOR
LATCH
LV23002M

AM AM AM FM
RF MIX DET DET
FM UNIVERSAL
MIX COUNTER
AM FM IF CCB
REG GND1 IF IF DECODER
VCC1 BUFFER VSS I/F

VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
AM ANT
L-OUT R-OUT

µ-COM
450kHz 10.7MHz

VCC

No.7900-11/13
 Vt=8V

100kΩ

0.047µF
0.047µF
0.01µF
VDD =3.0V

1kΩ
1kΩ
5.1kΩ

0.01µF

100kΩ

100kΩ
0.047µF
10Ω SVC346
1000pF 10kΩ 1000pF 390pF +
16pF
100µF
4.7µF +

SA-151
10pF
10pF

10pF
SA-149
FM IN GFWB3

100kΩ
Test Circuit Diagram

CFV-206

22pF
+

10kΩ 0.33µF
4.7kΩ

100pF
0.1µF

51kΩ
51kΩ
100kΩ

12pF
SA-181

1000pF
SVC201
SVC201
10kΩ 10000pF
S10 S9 S8 S7 S6 S5 S4
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
FM GND2 FM VCC2 FM AM BO2 BO1 A-OUT A-IN PD AM DET MPX VDD X-OUT X-IN
RFIN RFOUT OSC OSC AGC LOWCUT OUT IN
LV23002M

AM REG FM GND1 AM VCC1 AM FM P-DET P-COMP FM L-OUT R-OUT VSS CE DI CL DO

RFIN MIX MIX IFIN IFIN DET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0.047µF L-OUT R-OUT
AM IN S1 S2 S3

51Ω
51kΩ
0.01µF
0.01µF

39mH
1µF
µ-COM
3.3kΩ

4.7µF

+ +

SA-164
+

U2B-B0
7FA00-B0
SFELA 10M
1µF

10µF
+

SFULA450K

0.047µF
CDALA10M7GE001-B0

100µF

0.047µF
VCC=5.0V
300Ω
FM IF IN
0.047µF
51Ω

No.7900-12/13
 LV23002M
Coil specifications (bottom view)
• FM BPF : GFWB3 (Soshin) 76MHz to 108MHz
• FM RF : SA-149 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 4.5T: US band
• FM OSC : SA-151 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 3.5T: US band
• FM IF filter:
SFELA10M7FA00-B0 (Murata)
• FM Ceramic-discriminator:
CDALA10M7GE001-B0 (Murata)
• AM OSC: SA-181 (Sumida) • AM MIX: SA-164 (Sumida)
S h-f 37T S S e - d 122T
VC 3 4 pin31 e-c 74T
pin5 3 4 CF f - h 9T
0.06UEW d - c 62T
2 VCC 2
fo=796kHz 0.06UEW

6 VCC Qo ≥ 80 fo=450kHz, Qo ≥ 65
GND 1 1 6 GND
S L=140µH 180pF internal
• AM IF filter: SFULA450KU2B-B0 (Murata)
• MW Bar-antenna: C8E-A0105 (Toko)
c-d 67T
e-f 9T
fo = 796kHz
S S
1 2 3 4 Qu = 180min
VC GND Pin1 Pin2 L = 260µH

PS No.7900-13/13