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    Octal 3-State Noninverting Buffer/Line Driver/Line Receiver: SL74HC244

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    José Adelino
    This document summarizes the SL74HC244 octal 3-state noninverting buffer/line driver/line receiver integrated circuit. It is a high-performance CMOS device with noninverting outputs and two active-low output enables that can directly interface with CMOS, NMOS, and TTL logic. It provides specifications for operating conditions, electrical characteristics, maximum ratings, pin assignments, and a logic diagram.

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    Octal 3-State Noninverting Buffer/Line Driver/Line Receiver: SL74HC244

    Uploaded by

    José Adelino
    135 views5 pages
    This document summarizes the SL74HC244 octal 3-state noninverting buffer/line driver/line receiver integrated circuit. It is a high-performance CMOS device with noninverting outputs and two active-low output enables that can directly interface with CMOS, NMOS, and TTL logic. It provides specifications for operating conditions, electrical characteristics, maximum ratings, pin assignments, and a logic diagram.

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    HC244

    Original Title

    HC 244

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    This document summarizes the SL74HC244 octal 3-state noninverting buffer/line driver/line receiver integrated circuit. It is a high-performance CMOS device with noninverting outputs and two active-low output enables that can directly interface with CMOS, NMOS, and TTL logic. It provides specifications for operating conditions, electrical characteristics, maximum ratings, pin assignments, and a logic diagram.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    135 views5 pages

    Octal 3-State Noninverting Buffer/Line Driver/Line Receiver: SL74HC244

    Uploaded by

    José Adelino
    This document summarizes the SL74HC244 octal 3-state noninverting buffer/line driver/line receiver integrated circuit. It is a high-performance CMOS device with noninverting outputs and two active-low output enables that can directly interface with CMOS, NMOS, and TTL logic. It provides specifications for operating conditions, electrical characteristics, maximum ratings, pin assignments, and a logic diagram.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    SL74HC244

    Octal 3-State Noninverting


    Buffer/Line Driver/Line Receiver

    High-Performance Silicon-Gate CMOS

    The SL74HC244 is identical in pinout to the LS/ALS244. The device


    inputs are compatible with standard CMOS outputs; with pullup
    resistors, they are compatible with LS/ALSTTL outputs.
    This octal noninverting buffer/line driver/line receiver is designed
    to be used with 3-state memory address drivers, clock drivers, and
    other bus-oriented systems. The device has noninverting outputs and
    two active-low output enables. ORDERING INFORMATION
    Outputs Directly Interface to CMOS, NMOS, and TTL SL74HC244N Plastic
    Operating Voltage Range: 2.0 to 6.0 V SL74HC244D SOIC
    Low Input Current: 1.0 A TA = -55 to 125 C for all packages
    High Noise Immunity Characteristic of CMOS Devices

    PIN ASSIGNMENT

    LOGIC DIAGRAM

    FUNCTION TABLE

    Inputs Outputs
    Enable A, A,B YA,YB
    Enable B
    L L L

    PIN 20=VCC L H H
    PIN 10 = GND H X Z
    X=dont care
    Z = high impedance

    System Logic
    SLS Semiconductor
    IN74HC244

    MAXIMUM RATINGS *

    Symbol Parameter Value Unit


    VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
    VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
    VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
    IIN DC Input Current, per Pin 20 mA
    IOUT DC Output Current, per Pin 35 mA
    ICC DC Supply Current, VCC and GND Pins 75 mA
    PD Power Dissipation in Still Air, Plastic DIP+ 750 mW
    SOIC Package+ 500
    Tstg Storage Temperature -65 to +150 C
    TL Lead Temperature, 1 mm from Case for 10 Seconds 260 C
    (Plastic DIP or SOIC Package)
    *
    Maximum Ratings are those values beyond which damage to the device may occur.
    Functional operation should be restricted to the Recommended Operating Conditions.
    +Derating - Plastic DIP: - 10 mW/C from 65 to 125C
    SOIC Package: : - 7 mW/C from 65 to 125C

    RECOMMENDED OPERATING CONDITIONS


    Symbol Parameter Min Max Unit
    VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
    VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
    TA Operating Temperature, All Package Types -55 +125 C
    tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V 0 1000 ns
    VCC =4.5 V 0 500
    VCC =6.0 V 0 400

    This device contains protection circuitry to guard against damage due to high static voltages or electric
    fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
    voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
    GND(VIN or VOUT)VCC.
    Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
    Unused outputs must be left open.

    System Logic
    SLS Semiconductor
    SL74HC244

    DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)


    VCC Guaranteed Limit
    Symbol Parameter Test Conditions V 25 C 85 125 Unit
    to C C
    -55C
    VIH Minimum High-Level VOUT= VCC-0.1 V 2.0 1.5 1.5 1.5 V
    Input Voltage IOUT 20 A 4.5 3.15 3.15 3.15
    6.0 4.2 4.2 4.2
    VIL Maximum Low -Level VOUT=0.1 V 2.0 0.5 0.5 0.5 V
    Input Voltage IOUT 20 A 4.5 1.35 1.35 1.35
    6.0 1.8 1.8 1.8
    VOH Minimum High-Level VIN=VIH 2.0 1.9 1.9 1.9 V
    Output Voltage IOUT 20 A 4.5 4.4 4.4 4.4
    6.0 5.9 5.9 5.9
    VIN=VIH
    IOUT 6.0 mA 4.5 3.98 3.84 3.7
    IOUT 7.8 mA 6.0 5.48 5.34 5.2
    VOL Maximum Low-Level VIN= VIL 2.0 0.1 0.1 0.1 V
    Output Voltage IOUT 20 A 4.5 0.1 0.1 0.1
    6.0 0.1 0.1 0.1
    VIN= VIL
    IOUT 6.0 mA 4.5 0.26 0.33 0.4
    IOUT 7.8 mA 6.0 0.26 0.33 0.4
    IIN Maximum Input VIN=VCC or GND 6.0 0.1 1.0 1.0 A
    Leakage Current
    IOZ Maximum Three-State Output in High-Impedance 6.0 0.5 5.0 10.0 A
    Leakage Current State
    VIN= VIL or VIH
    VOUT=VCC or GND
    ICC Maximum Quiescent VIN=VCC or GND 6.0 4.0 40 160 A
    Supply Current IOUT=0A
    (per Package)

    System Logic
    SLS Semiconductor
    IN74HC244

    AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)


    VCC Guaranteed Limit
    Symbol Parameter V 25 C to 85C 125C Unit
    -55C
    tPLH, t PHL Maximum Propagation Delay, A to YA or B to YB 2.0 96 115 135 ns
    (Figures 1 and 3) 4.5 18 23 27
    6.0 15 20 23
    tPLZ, t PHZ Maximum Propagation Delay , Output Enable to 2.0 110 140 165 ns
    YA or YB (Figures 2 and 4) 4.5 22 28 33
    6.0 19 24 28
    tPZL, t PZH Maximum Propagation Delay , Output Enable to 2.0 110 140 165 ns
    YA or YB (Figures 2 and 4) 4.5 22 28 33
    6.0 19 24 28
    tTLH, t THL Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
    (Figures 1 and 3) 4.5 12 15 18
    6.0 10 13 15
    CIN Maximum Input Capacitance - 10 10 10 pF
    COUT Maximum Three-State Output Capacitance - 15 15 15 pF
    (Output in High-Impedance State)

    Power Dissipation Capacitance (Per Buffer) Typical @25C,VCC=5.0 V


    CPD Used to determine the no-load dynamic power 34 pF
    consumption:
    PD=CPDVCC2f+ICCVCC

    Figure 1. Switching Waveforms Figure 2. Switching Waveforms

    Figure 3. Test Circuit Figure 4. Test Circuit

    System Logic
    SLS Semiconductor
    SL74HC244

    EXPANDED LOGIC DIAGRAM


    (1/8 of the Device)

    System Logic
    SLS Semiconductor

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