HDL II

concatenate operator {}
The concatenate operator is used to group signals to form an array.
Frecuency Divider
“clock edge detection"
Posedge prefix detects rising edge.
The negedge prefix detects the falling edge.
Instantiation
Instantiation refers to the process of creating an instance of a module within another module or
design.

TOP LEVEL

Module1 Module2

Module3
Frequency Divider
A frequency divider is a fundamental component in the design of digital circuits that reduces the
frequency of an input clock signal to generate an output clock signal with a lower frequency.
parameter
Constants can be defined within a module
localparam
In Verilog, a constant can be declared using the reserved word localparam (for local
parameters). For example, we can declare the width and range of a data bus as

To improve readability, we can use a symbolic

constant, "N", to represent the number of bits
in the adder.

The constant makes the code easier to

understand and maintain.
TOP Module with parameters
 Testbenches:
ADVANTAGES: DISADVANTAGES:
Flexibility and Power: Learning Curve:
• Customization: Detailed, tailored simulations. • HDL Knowledge: Requires familiarity with VHDL or
• Automation: Scripts for complex, repetitive tests save Verilog.
time. • Increased Complexity: Writing testbenches is more
complex and time-consuming.
Reusability and Portability:
• Reusable: Applicable to different projects and Initial Setup:
designs. • Time-Consuming: Initial setup takes longer than VWF
• Compatibility: Usable across various simulation tools. files.

Depth of Testing:
• Test Coverage: Handles a wide range of scenarios.
• Complex Signals: Can generate realistic, intricate test
signals.
Ejemplo TESTBENCH
Define the name of the testbench module.
Set the timescale for simulation.
Declare reg signals for inputs.
Declare wire signals for outputs.
Instantiate the module being tested.
Connect test signals to module ports.
Define an initial block to apply different values to inputs at
specific time intervals.
Use # to wait for a specified number of time units.
End simulation with $finish.
Define an initial block to monitor and display signal values.
Use $monitor to print values each time signals change.
Define the name of the testbench module.
Set the timescale for simulation.

Declare reg signals for inputs.

Declare wire signals for outputs.

Instantiate the module being tested.

Connect test signals to module ports.

Define an initial block to apply different values to inputs at

specific time intervals.
Use # to wait for a specified number of time units.
End simulation with $finish.

Define an initial block to monitor and display signal values.

Use $monitor to print values each time signals change.
•$monitor: Prints signal values whenever they change during simulation.

•$display: Prints signal values at specific points in simulation time.

•$strobe: Prints signal values only when a strobe event occurs.

•$stop: Halts simulation at a specific point based on a condition.

•$finish: Ends simulation at the point where the instruction is located.

•always block: Defines a block of code that continuously executes during simulation, triggered by
sensitivity conditions like changes in input signals.

•$time: Returns the current simulation time in units specified by the timescale.
University Program VWF:
In Quartus Prime Lite, the University Program VWF (Vector Waveform File) is a file format used
for simulating and verifying digital hardware designs.
Purposes and Functions of the University Program VWF:

•Timing Simulation: Create and run timing simulations to observe signal behavior over time.

•Input Signal Generation: Define input signals to test design responses.

•Signal Visualization: View input and output signals as waveforms to understand changes.

•Testing and Verification: Test and verify designs before hardware implementation to find and fix
errors.
University
Program VWF
University
Program VWF
University Program VWF:
ADVANTAGES: DISADVANTAGES:
Ease of Use: Complexity Limitations:
• Graphical Interface: Intuitive for beginners and • Complex Designs: Not suitable for highly
students. complex simulations.
• Quick Setup: Configure and run simulations • Limited Automation: Manual signal creation
without coding. can be tedious.
Immediate Visualization: Portability:
• Signal Waves: Easy-to-understand waveform • Quartus-Specific: VWF files are not easily
display. portable to other simulation environments.
• Interactivity: Modify and observe signal
changes in real-time.
Ideal for Education:
• Educational Resources: Designed for teaching
digital hardware design.
Example 2
Actividad
Realizar un divisor de frecuencia que sea parametrizable y crear un testbench para verificar su
funcionamiento.

Descripción
En esta actividad, se implementará un divisor de frecuencia parametrizable utilizando técnicas
digitales. Un divisor de frecuencia es un componente fundamental en muchos sistemas digitales,
ya que permite reducir la frecuencia de una señal de reloj a una fracción deseada. La
parametrización del divisor permitirá ajustar la frecuencia de salida según las necesidades
específicas del diseño.
Cascaded counters
Cascaded counters
One-hot Decoder
This decoder has for output only one high bit, hence its name 1-hot (if it is otherwise, its
name is 1-cold), which is shifted to the left as the binary word at the input increases, the
following image exemplifies its behavior with a truth table and the associated circuit.
One-hot Decoder
➢One-hot decoding is a process by which we ➢Learning by means of names is very
convert categorization variables into a simpler complicated for a machine, so we will use
prediction algorithm for machine learning One-hot coding to binarize the categories.
models.
Thermometer Decoder

➢In this decoder, the bit corresponding ➢Among the applications of this decoder
to the input combination and all other is to improve the performance of digital-
bits less significant than this one are 1. to-analog converters (DACs).
Finite State Machine
(FSM)
An FSM (finite state machine) is a sequential circuit that transits between a finite number of
internal states. Transitions depend on the current state and external input and have a simple,
"regular" pattern.

The basic block diagram of an FSM is the same as that of a normal sequential circuit, as shown in
the figure. This circuit consists of a state register, a following state logic, and an output logic.
State Diagram
Description: A visual diagram that shows the
states of the machine and the transitions
between them.
Key Components:
States: Represented by circles or ovals.
Transitions: Arrows connecting the states,
indicating the move from one state to another.
Transition Labels: Conditions that must be met
for a transition to occur.
Outputs (for Moore and Mealy):
Moore: Outputs are associated with states.
Mealy: Outputs are associated with transitions.

Advantages: Easy to understand and visualize the

logic of the state machine.
Moore machines
All outputs are fully synchronized with the circuit clock.

State Diagram: Each state of the machine specifies its output(s)

independent of circuit inputs.

Verilog Code of a Moore State Machine: Only circuit state

variables participate in the output expression of the circuit.
Exercise 1 Reference code →
Mealy machines

A Mealy machine differs from a Moore machine in that its outputs depend on both its current state and
the inputs while in that state.

The state transitions, clocking, and resetting of the machine are similar to those of a Moore machine,
and the same coding techniques are used to describe them.
A 101 Mealy Machine
Taller
Make a Mealy state diagram that detects the sequence 1101 and 1001.