Q1. Write a Verilog Code for D-Latch ?

Q2. What are the ways of writing FSM code?

• All input decoders, output decoders, and present states are combined in one process.
• Where sequential and combinational circuits are separated in different processes.
• Where input decoder and present state are combined, but output decoders are separated.
• Where all three inputs are separated into three processes.

Q3. What is Verilog used for?

Verilog is a hardware description language (HDL) used primarily to model, design, and simulate
digital systems, particularly at the register-transfer level (RTL) and gate level. It allows designer to
describe hardware components and systems in a textual form, which can then be simulated and
synthesized into actual hardware.

Primary Uses of Verilog:

1. Designing Digital Circuits: Verilog is widely used to design and specify the behavior of digital logic
circuits such as:
1. Combinational logic (e.g., adders, multiplexers, decoders).
2. Sequential logic (e.g., flip-flops, registers, counters).
3. Finite state machines (FSMs) for control systems.

2. RTL (Register Transfer Level) Design: Verilog allows for the description of hardware at the RTL level,
which defines how data is transferred between registers and the logic that operates on that data. RTL
 design is a key stage in the digital design process, allowing engineers to describe how hardware
components interact and function.

3. Simulation of Digital Systems: Before physically implementing a design on hardware, Verilog models
can be simulated to verify their functionality and behavior. This helps designers detect and correct errors
early in the development cycle, avoiding costly mistakes in actual hardware manufacturing.

4. Synthesis to Hardware: Verilog code can be synthesized into real hardware components, such as FPGAs
(Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits). The Verilog code
is translated into a netlist, which describes the connections between different logic gates in the actual
hardware.

5. FPGA Programming: Verilog is frequently used to program FPGAs, which are reconfigurable hardware
devices. Designers write Verilog code to describe the desired behavior of the FPGA, which is then loaded
into the device to implement specific digital logic functions.

6. ASIC Design: For ASICs, Verilog is used to describe the hardware at a high level. Once the design is
verified through simulation, the code is synthesized and converted into a gate-level representation,
eventually leading to the physical layout of the chip.

7. Verification and Testing: Verilog also includes features for testbench creation, where designers can write
test scenarios to validate that their hardware design behaves correctly under different conditions. This is
essential for ensuring reliability before fabrication.

8. Mixed-Signal and System Design: Although Verilog is primarily focused on digital circuits, Verilog-
AMS (an extension of Verilog) is used for designing mixed-signal systems that involve both digital and
analog components, making it useful for designing integrated circuits that require a combination of digital
and analog behavior.

Key Applications of Verilog:

• Microprocessors and CPU Design: Verilog is used to describe the architecture and functionality of
processors.
• Communication Protocols: It can model hardware implementations of communication protocols like
UART, SPI, or Ethernet.
• DSP (Digital Signal Processing): Verilog helps in designing DSP systems for audio, video, and other
signal processing applications.
• Memory Components: Designers use Verilog to model RAM, ROM, and cache memory.
• Automotive Electronics: Used in designing control systems for safety-critical applications in
automobiles.

Why Use Verilog?

• High-Level Abstraction: Verilog provides a way to describe complex hardware systems at a high level,
which can then be translated into gate-level designs.
• Tool Support: A wide range of simulation, synthesis, and verification tools are available for Verilog,
making it a preferred language in the industry.
• Portability: Verilog designs can be implemented across different platforms, including ASICs and FPGAs.
• Concurrent Modeling: Since hardware operates in parallel, Verilog allows you to describe concurrent
operations, making it more suitable for hardware modeling than traditional sequential programming
languages like C.
Verilog is fundamental in the hardware design process, enabling efficient, scalable, and testable digital
system design for both academic and industrial applications.

Q4. What is the Sensitivity list?

A sensitivity list is a key part of an always block, which specifies when the block should be triggered or
executed. The sensitivity list contains signals or events (like changes in signals) that the always block
should "respond" to. Whenever any signal in the sensitivity list changes value, the always block is re-
evaluated or executed.
The sensitivity list is placed after the keyword always and enclosed in @ parentheses:
verilog
always @(sensitivity_list)
begin // Code to be executed when sensitivity list is triggered
end

Q5. What is Parameter and Typedef in Verilog?

Parameters in Verilog are constants that allow you to define values that can be changed easily without
modifying the actual code. They are commonly used in modules to make the design more flexible and
reusable. You can set default values for parameters and override them during module instantiation.
Parameters are defined within a module using the parameter keyword:

module example #(parameter WIDTH = 8, parameter DEPTH = 16) ();

// WIDTH is set to 8 by default
// DEPTH is set to 16 by default
Endmodule

Example :

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, input [WIDTH-1:0] b, output

[WIDTH-1:0] sum);
assign sum = a + b;
endmodule

Advantages of Parameters

• Reusability: Modules can be reused with different configurations.

• Flexibility: Easily modify designs without changing the internal logic.
• Clarity: Makes the code more readable by naming specific values.
 Typedefs

Typedefs in Verilog are used to create new data types or aliases for existing types, making the code
clearer and easier to manage. While Verilog does not have a direct typedef keyword as in some
programming languages, you can create new data types or aliases using the localparam and generate
constructs, particularly in SystemVerilog.
You can define a new data type in SystemVerilog (an extension of Verilog) using the typedef keyword:
typedef logic [7:0] byte_t; // Defines a new type byte_t as 8-bit logic

Example :
module my_module;
byte_t data; // Uses the newly defined type // ...
endmodule

Advantages of Typedefs

• Clarity: Provides meaningful names for data types, improving code readability.
• Maintenance: Easier to update type definitions in one place if changes are needed.
• Type Safety: Helps avoid errors by explicitly defining types.