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    LAB#4

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    Unsa Jan Abdul Qayyum
    This document provides information about using constants and parameters in Verilog digital system design. It defines constants as fixed values that cannot be modified within a module, and recommends replacing "hard literals" with symbolic constants to improve code clarity and maintenance. Parameters are defined as a mechanism for passing information into a module to make it versatile and reusable, functioning like constants but allowing the default value to be modified when instantiated. The lab objectives are to learn using constants for effective coding and parameters to create scalable designs. Students are instructed to explore sample codes and write a testbench with test vectors.

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    LAB#4

    Uploaded by

    Unsa Jan Abdul Qayyum
    24 views3 pages
    This document provides information about using constants and parameters in Verilog digital system design. It defines constants as fixed values that cannot be modified within a module, and recommends replacing "hard literals" with symbolic constants to improve code clarity and maintenance. Parameters are defined as a mechanism for passing information into a module to make it versatile and reusable, functioning like constants but allowing the default value to be modified when instantiated. The lab objectives are to learn using constants for effective coding and parameters to create scalable designs. Students are instructed to explore sample codes and write a testbench with test vectors.

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    This document provides information about using constants and parameters in Verilog digital system design. It defines constants as fixed values that cannot be modified within a module, and recommends replacing "hard literals" with symbolic constants to improve code clarity and maintenance. Parameters are defined as a mechanism for passing information into a module to make it versatile and reusable, functioning like constants but allowing the default value to be modified when instantiated. The lab objectives are to learn using constants for effective coding and parameters to create scalable designs. Students are instructed to explore sample codes and write a testbench with test vectors.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    24 views3 pages

    LAB#4

    Uploaded by

    Unsa Jan Abdul Qayyum
    This document provides information about using constants and parameters in Verilog digital system design. It defines constants as fixed values that cannot be modified within a module, and recommends replacing "hard literals" with symbolic constants to improve code clarity and maintenance. Parameters are defined as a mechanism for passing information into a module to make it versatile and reusable, functioning like constants but allowing the default value to be modified when instantiated. The lab objectives are to learn using constants for effective coding and parameters to create scalable designs. Students are instructed to explore sample codes and write a testbench with test vectors.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Department of

    Electrical Engineering

    Digital System Design (ESE-412)

    Handout#04
    Use of Constants and Parameters in Verilog
    Instructor: Irsa Jan

    Lab Learning Objectives:

    After completing this session, student should be able to:


    • Use constants for effective coding in HDL.
    • Use parameters to make scalable code designs.
    Note: Submit the lab report (solved activities and exercises) before the next lab.

    Lab Hardware and Software Required:

    1. Desktop/Laptop Computer with internet connection.

    Background Theory:
    Constant
    HDL code frequently uses constant values in expressions and array boundaries. These
    values are fixed within the module and cannot be modified. One good design practice is
    to replace the "hard literals" with symbolic constants. It makes code clear and helps future
    maintenance and revision. In Verilog, a constant can be declared using the localparam
    (for "local parameter") keyword. For example, we can declare the width and range of a
    data bus as

    localparam DATA-WIDTH = 8,
    DATA-RANGE = 2**DATA_WIDTH – 1;

    The expression in the declaration, such as 2**DATA-WIDTH-1, is evaluated during


    preprocessing and thus infers no physical circuit.

    Parameter
    A Verilog module can be instantiated as a component and becomes a part of a larger
    design, as discussed in previous labs. Verilog provides a construct, known as a
    parameter, to pass information into a module. This mechanism makes the module
    versatile and reusable. A parameter cannot be modified inside the module and thus
    functions like a constant. A parameter declaration section can be added in the header,
    before the port declaration. Its simplified syntax is

    module [module-name]
    #(
    parameter [parameter-name] = [default-value] ,
    ...
    [parameter-name] = [default-value] ;
    )
    (
    . . . // I/O port declaration
    );

    A parameter provides a mechanism to create scalable code, in which the "width" of a


    circuit can be adjusted to meet a specific need. This makes code more portable and
    encourages design reuse.

    Lab Activity:
    Explore sample HDL codes given in listings 3.9, 3.10, 3.11 and 3.12 in your textbook. You
    may write a testbench code with some test vectors of your own choice.

    Exercise:

    1. Explain in your own words how Parameters and Constants are different.
    2. A parameter is declared with a constant value inside a module. Is it possible to
    modify the default value when the module is instantiated? Please explain with a
    programming example.

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