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    Testing

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    sangeethabg
    Testing and verification ensure the functional correctness of hardware designs and manufactured devices. Verification checks the design prior to manufacturing through simulation or formal methods. Testing verifies manufactured hardware through functional testing of logic and silicon debugging. Testing occurs at various levels from wafer to system and includes fault testing using techniques like automatic test pattern generation and delay fault testing.

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    Testing

    Uploaded by

    sangeethabg
    97 views23 pages
    Testing and verification ensure the functional correctness of hardware designs and manufactured devices. Verification checks the design prior to manufacturing through simulation or formal methods. Testing verifies manufactured hardware through functional testing of logic and silicon debugging. Testing occurs at various levels from wafer to system and includes fault testing using techniques like automatic test pattern generation and delay fault testing.

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    Testing and verification ensure the functional correctness of hardware designs and manufactured devices. Verification checks the design prior to manufacturing through simulation or formal methods. Testing verifies manufactured hardware through functional testing of logic and silicon debugging. Testing occurs at various levels from wafer to system and includes fault testing using techniques like automatic test pattern generation and delay fault testing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    97 views23 pages

    Testing

    Uploaded by

    sangeethabg
    Testing and verification ensure the functional correctness of hardware designs and manufactured devices. Verification checks the design prior to manufacturing through simulation or formal methods. Testing verifies manufactured hardware through functional testing of logic and silicon debugging. Testing occurs at various levels from wafer to system and includes fault testing using techniques like automatic test pattern generation and delay fault testing.

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    © All Rights Reserved
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    of 23

    MODULE – 5B

    Testing and Verification


    • Testing : Functionality check.
    • Verification is a process used to demonstrate
    the functional correctness of a design.
    Testing verification
    Verifies correctness of manufactured Verifies correctness of design.
    hardware.
    Two-part process: Performed by simulation, hardware
    Test generation: software process executed emulation, or formal methods.
    once during design
    Test application: Electrical tests applied to
    hardware

    Test application performed on every Performed once prior to manufacturing.


    manufactured device.
    Responsible for quality of devices. Responsible for quality of design.
    Categories of Testing:
    • Functionality tests or logic verification : verifies that the chip
    performs its intended functions.

    • Silicon debug: tests run on first batch of chips that return from
    fabrication. This test confirms that the chip operates as it was
    intended and help debug any discrepancies.

    • Manufacturing tests: checks every transistor, gate and storage


    element in the chip functions correctly. These tests are conducted on
    every manufactured chip before shipping to the customer to verify that
    the silicon is completely intact.
    Various Levels of Testing a Si die:
    • Wafer level
    • Packaged chip level
    • Board level
    • System level
    • Field level
    Logic
    verification

    Functional equivalence at
    various levels of abstraction
    • FPGA
    • Verilog/vhdl
    Logic Verification Principles:

    • Test Bench and Harness: Piece of HDL code that is placed as a


    wrapper around a core piece of HDL.
    • Regression Testing : To check the bug fixes and enhancement
    (large test benches so high level language)
    • Version Control: orderly management of different design
    iterations. Unix/Linux tools such as CVS or Subversion are used.
    • Bug Tracking: the management of a wide variety of bugs.
    1. Entry of bug.
    2. bug location.
    3. Nature of bug.
    4. Severity of the bug.
    TEST PATTERN GENERATION
    Test vectors:
    • 0x00000000 all zeros
    • 0xFFFFFFFF All ones
    • 0x00000001 One in the LSB
    • 0x80000000 One in the MSB
    • 0x55555555 Alternating 0’s and 1’s
    • 0xAAAAAAAA Alternating 1’s and 0’s
    • 0x7A39D281 a random value
    Manufacturing Test Principles:
    • Fault Model
    • Observability
    • Controllability
    • Fault Coverage
    • Automatic Test Pattern Generation
    • Delay Fault Testing
    Fault analysis

    Stuck at 0 or 1:
    faulty gate input
    Occur Due to gate oxide shorts
    (the nMOS gate to GND
    or the pMOS gate to VDD)
    or metal-to-metal shorts.
    Short-Circuit and Open-Circuit Faults:
    • Shorting of input to ground or to vdd or to output
    • Open circuit indicates the discontinuity in the interconnects.
    Observability:
    Observability is the ability to observe, either directly or indirectly, the
    state of any node in the circuit.
    Controllability:
    • The controllability of an internal circuit node within a chip is a
    measure of the ease of setting the node to a 1 or 0 state (Input pad)
    Fault Coverage:
    • Goodness of a set of test vectors. 0 to 1 (stuck at)
    • When a discrepancy in faulty machine. It is compared with good
    machine, the fault is marked as detected and the simulation is
    stopped.
    Automatic Test Pattern Generation:
    • In the IC industry, logic and circuit designers implemented the
    functions at the RTL or schematic level, mask designers completed
    the layout, and test engineers wrote the tests. (vectors)
    • Most of the burden for generating tests has fallen on the designer.
    • To deal with this burden, Automatic Test Pattern Generation
    (ATPG) methods have been invented.

    Delay Fault Testing:


    • Delay fault occurs with the parasitic generation of metal wire
    interconnects.
    • It affects the timing.
    Design for testability
    • Adhoc testing

    • Scan based design

    • Built in self test


    Adhoc Testing
    • Collections of ideas aimed at reducing the combinational explosion of
    testing.
    • Useful for small designs where scan, ATPG, and BIST are not available.
    • Common techniques for ad hoc testing:
    Partitioning large sequential circuits
    Adding test points
    Adding multiplexers
    Providing for easy state reset
    Scan Design
    • In normal mode, they behave as
    expected.
    • In scan mode, they are
    connected to form a giant shift
    register called a scan chain
    spanning the whole chip.
    • By applying N clock pulses in scan
    mode, all N bits of state in the
    system can be shifted out and
    new N bits of state can be shifted
    in.
    • The serial scan chains can become quite long, and the loading and
    unloading can dominate testing time.
    • A fairly simple idea is to split the chains into smaller segments.
    • This can be done on a module-by-module basis or completed
    automatically to some specified scan length.
    • Extending this to the limit yields an extension to serial scan called
    random access scan.
    Parallel Scan
    • The figure shows a two-by-two
    register section.
    • Each register receives a column
    (column<m>) and row (row<n>)
    access signal along with a row data
    line (data<n>).
    • A global write signal (write) is
    connected to all registers.
    • By asserting the row and column
    access signals in conjunction with
    the write signal, any register can be
    read or written in exactly the same
    method as a conventional RAM.
    Build in Self Test (BIST)
    • One method of testing a module is to use signature analysis or cyclic redundancy
    checking. This involves using a pseudo-random sequence generator (PRSG) to
    produce the input signals for a section of combinational circuitry and a signature
    analyzer to observe the output signals

    • A PRSG of length n is constructed from a linear feedback shift register (LFSR), which in
    turn is made of n flip-flops connected in a serial fashion, as shown in figure (a). The
    XOR of particular outputs are fed back to the input of the LFSR
    • A complete feedback shift register (CFSR), shown in figure (b), includes the zero state
    that may be required in some test situations.
    BILBO (Built-In Logic Block
    Observation)
    • The combination of signature
    analysis and the scan
    technique creates a structure
    known as BILBO
    • The 3-bit BIST register shown
    in figure is a scannable,
    resettable register that also
    can serve as a pattern
    generator and signature
    analyzer
    Memory Self-test:
    • Testing large memories on a production tester can be expensive
    because they contain so many bits and thus require so many test
    vectors.
    • Embedding the self-test circuits with the memories can reduce the
    number of external test vectors that have to be run.
    IDDQ Testing:
    • Method of testing for bridging faults is called IDDQ test (VDD supply
    current Quiescent) or supply current monitoring.
    • This relies on the fact that when a CMOS logic gate is not switching, it
    draws no DC current (except for leakage).
    • When a bridging fault occurs, then for some combination of input
    conditions, a measurable DC IDD will flow.
    • Testing consists of applying the normal vectors, allowing the signals to
    settle, and then measuring IDD.
    Design for Manufacturability:
    Circuits can be optimized for manufacturability to increase their yield. This can be done in
    a number of different ways.
    • Physical
    • Increase the spacing between wires where possible––this reduces the chance of a defect causing a
    short circuit.
    • Increase the overlap of layers around contacts and vias––this reduces the chance that a
    misalignment will cause an aberration in the contact structure.
    • Increase the number of vias at wire intersections beyond one if possible––this reduces the chance
    of a defect causing an open circuit.
    • Redundancy
    • Power: Elevated power can cause failure due to excess current in wires, which in turn
    can cause metal migration failures
    • Process Spread: process simulations can be carried out at different process corners
    • Yield Analysis: When a chip has poor yield or will be manufactured in high volume, dice
    that fail manufacturing test can be taken to a laboratory for yield analysis to locate the
    root cause of the failure.

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