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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;
entity Counter is port( clk : in std_logic; clk_out: out std_logic; -- Reloj de entrada reset: in std_logic; count_in: in std_logic; seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); digit: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end Counter;
architecture Behavioral of Counter is
signal clk_1hz: std_logic := '0';
signal count_divider: UNSIGNED(31 downto 0) := (others => '0');
begin process(clk, reset) begin if reset = '1' then count_divider <= (others => '0'); clk_1hz <= '0'; elsif rising_edge(clk) then if count_divider >= div_value then count_divider <= (others => '0'); clk_1hz <= not clk_1hz; else count_divider <= count_divider + 1; end if; end if; end process;
process(clk_1hz, reset) begin if reset = '1' then total_counter <= 0; count_in_last <= '1'; elsif rising_edge(clk_1hz) then if count_in_last = '1' and count_in = '0' then -- Detección de flanco de bajada total_counter <= total_counter + 1; if total_counter = 15 then total_counter <= 0; end if; end if; count_in_last <= count_in; -- Actualiza el estado anterior de count_in end if; end process; seg <= seg_codes(total_counter); digit <= "11111110";
