 Autómata duración

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity aut_duracion is
Port ( CLK : in STD_LOGIC; -- reloj de 1 ms
LIN : in STD_LOGIC; -- lnea de entrada de datos
VALID_INT : out STD_LOGIC; -- salida de validacin de
intervalo
DATO : out STD_LOGIC; -- salida de dato (0 o 1)
DURACION : out STD_LOGIC_VECTOR (15 downto 0)); -- salida de
end aut_duracion; -- duracin del
intervalo

architecture a_aut_duracion of aut_duracion is

type STATE_TYPE is (CONTAR,VALIDAR,RESET);

signal ST : STATE_TYPE := RESET;

signal cont : unsigned (15 downto 0):="0000000000000000";

signal dato_act : STD_LOGIC:= '0';

begin

process (CLK) -- Autmata digital sncrono

begin
if (CLK'event and CLK='1') then
case ST is
when RESET =>
cont<="0000000000000010";
dato_act<=LIN;
ST<=CONTAR;
when CONTAR =>
cont<=cont+"0000000000000001";
if cont>"0000001001011000" then
ST<=VALIDAR;
elsif LIN/=dato_act then
ST<=VALIDAR;
else
ST<=CONTAR;
end if;
when others =>
ST<=RESET;
end case;
end if;
end process;

-- CABLEADOS DE LAS SALIDAS

VALID_INT <='1' when ST=VALIDAR else '0';

DATO <= dato_act;
DURACION <= STD_LOGIC_VECTOR(cont);

end a_aut_duracion;
 Autómata control
Para umbral0 y umbral1 (300 + 100)/2 ms

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity aut_control is

Port ( CLK : in STD_LOGIC; -- reloj

VALID_INT : in STD_LOGIC; -- entrada de intervalo vlido

DATO : in STD_LOGIC; -- dato (0 o 1)

DURACION : in STD_LOGIC_VECTOR (15 downto 0); -- duracin del

intervalo

CODIGO : out STD_LOGIC_VECTOR (7 downto 0); -- cdigo morse

obtenido

VALID_COD : out STD_LOGIC); -- validacin del

cdigo

end aut_control;

architecture a_aut_control of aut_control is

constant UMBRAL0 : integer := 200; -- umbral para los 0

constant UMBRAL1 : integer := 200; -- umbral para los 1

type STATE_TYPE is (ESPACIO,RESET,SIMBOLO,ESPERA);

signal ST : STATE_TYPE := RESET;

signal s_ncod : unsigned (2 downto 0):="000";

signal s_cod : STD_LOGIC_VECTOR (4 downto 0):="00000";

signal n : INTEGER range 0 to 4;

begin

process (CLK) -- Autmata digital sncrono

begin

if (CLK'event and CLK='1') then

case ST is

when RESET =>

n <= 4;

s_ncod<="000";

s_cod<="00000";

if (VALID_INT='1' and DATO='1') then

ST<=SIMBOLO;

else

ST<=RESET;

end if;

when SIMBOLO =>

if (to_integer(unsigned(DURACION))>UMBRAL1) then
s_cod(n)<='1';
s_ncod<=s_ncod+1;
n<=n-1;
ST<=ESPERA;
else
s_cod(n)<='0';
s_ncod<=s_ncod+1;
n<=n-1;
ST<=ESPERA;
end if;

when ESPERA =>

if(VALID_INT = '1' and DATO = '0' and
(to_integer(unsigned(DURACION)) > UMBRAL0)) then
ST<=ESPACIO;
elsif(VALID_INT = '1' and DATO = '1') then
ST<=SIMBOLO;
else
ST<=ESPERA;
end if;

when others =>

ST<=RESET;
 end case;

end if;

end process;

-- CABLEADOS DE LAS SALIDAS

VALID_COD<='1' when ST = ESPACIO else '0';

CODIGO(4 downto 0)<= s_cod ; -- Complete las asignaciones

CODIGO(7 downto 5)<= STD_LOGIC_VECTOR(s_ncod) ;

end a_aut_control ;

 Registro
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity registro is
Port ( CLK : in STD_LOGIC; -- Reloj
ENABLE : in STD_LOGIC; -- Enable
D : in STD_LOGIC_VECTOR (7 downto 0); -- Entradas
Q : out STD_LOGIC_VECTOR (7 downto 0)); -- Salidas
end registro;

architecture a_registro of registro is

 signal reg : STD_LOGIC_VECTOR (7 downto 0):="00000000"; -- Contenido del
registro

begin

process(CLK)
begin
if (CLK' event and CLK= '1') then

if (ENABLE = '1') then

reg <= D;
else
end if;

end if;
end process;

Q<= reg;
end a_registro;

 Receptor
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity receptor is
Port ( CLK : in STD_LOGIC; -- Entrada de reloj del sistema
LIN : in STD_LOGIC; -- Entrada de lnea
CARACTER : out STD_LOGIC_VECTOR (7 downto 0)); -- Salida:
caracteres
end receptor;

architecture a_receptor of receptor is

component aut_duracion is
Port ( CLK : in STD_LOGIC; -- reloj de 1 ms
LIN : in STD_LOGIC; -- lnea de entrada de
datos
VALID_INT : out STD_LOGIC; -- salida de validacin de
intervalo
DATO : out STD_LOGIC; -- salida de dato (0 o 1)
DURACION : out STD_LOGIC_VECTOR (15 downto 0)); -- Duracin
intervalo
end component;

component aut_control is
 Port ( CLK : in STD_LOGIC; -- reloj

VALID_INT : in STD_LOGIC; -- entrada de intervalo vlido

DATO : in STD_LOGIC; -- dato (0 o 1)

DURACION : in STD_LOGIC_VECTOR (15 downto 0); -- duracin del

intervalo

CODIGO : out STD_LOGIC_VECTOR (7 downto 0); -- cdigo morse

obtenido

VALID_COD : out STD_LOGIC);

end component;

component ROM is
Port (
MORSE : in STD_LOGIC_VECTOR (7 downto 0);
ASCII : out STD_LOGIC_VECTOR (7 downto 0));
end component;

component registro is
Port (
CLK : in STD_LOGIC; -- Reloj
ENABLE : in STD_LOGIC; -- Enable
D : in STD_LOGIC_VECTOR (7 downto 0); -- Entradas
Q : out STD_LOGIC_VECTOR (7 downto 0)); -- Salidas

end component;

signal m1, m2, m4: STD_LOGIC;

signal m3: STD_LOGIC_VECTOR (15 downto 0);
signal m5, m6: STD_LOGIC_VECTOR (7 downto 0);

begin

U1 : aut_duracion port map (CLK, LIN, m1, m2, m3);

U2 : aut_control port map (CLK, m1, m2, m3, m5, m4);
U3 : ROM port map (m5, m6);
U4 : registro port map (CLK, m4, m6, CARACTER);

end a_receptor;

 TB receptor
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_receptor IS
END tb_receptor;

ARCHITECTURE behavior OF tb_receptor IS

COMPONENT receptor -- Declaracin del componente que se va a

simular
PORT(CLK : IN std_logic;
LIN : IN std_logic;
CARACTER : OUT std_logic_vector(7 downto 0));
END COMPONENT;
-- Seales correspondientes a las entradas y salidas del componente
signal CLK : std_logic := '0';
signal LIN : std_logic := '0';
signal CARACTER : std_logic_vector(7 downto 0);

-- Periodo del reloj = 1 ms

constant CLK_period : time := 1 ms;

BEGIN
-- Cableado del componente bajo prueba
uut: receptor PORT MAP (
CLK => CLK,
LIN => LIN,
CARACTER => CARACTER );

-- Proceso que genera la seal de reloj CLK

CLK_process :process
begin
CLK <= '0'; -- Flanco de bajada
wait for CLK_period/2;
CLK <= '1'; -- Flanco de subida
wait for CLK_period/2;
end process;

-- Proceso que genera la seal LIN

LIN_process: process
begin
LIN<='0'; -- ESPACIO INICIAL
wait for 300 ms;

-- CODIFIQUE EL ARCHIVO DE SIMULACIN SEGN SU APELLIDO, NOMBRE Y DNI

-- CARACTER R
LIN<='1'; --punto
wait for 100 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; --punto
wait for 100 ms;
LIN<='0'; -- ESPACIO
wait for 300 ms;

-- CARACTER G
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; --punto
 wait for 100 ms;
LIN<='0'; -- ESPACIO
wait for 300 ms;

-- EJEMPLO CARCTER A (-)

LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; -- ESPACIO
wait for 300 ms;
-- FIN EJEMPLO CARCTER A (-)

-- Caracter 0
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --espacio
wait for 300 ms;

-- Caracter 2
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --pausa
wait for 100 ms;
LIN<='1'; -- RAYA
wait for 300 ms;
LIN<='0'; --espacio
wait for 300 ms;
 -- Caracter 5
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- PAUSA
wait for 100 ms;
LIN<='1'; -- PUNTO
wait for 100 ms;
LIN<='0'; -- espacio
wait for 300 ms;

wait;
end process;
END;

La duración total se calculó sumando todos los 100 y 300 ms más los
primeros 300 ms, más 1 s para que salga el último símbolo.