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    Sec 2

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    Anuradha Khalkho
    1. The document describes a design to generate a 1 second clock signal from a global clock on a Basys 3 board and display the seconds count on two 7-segment displays from 0 to 60. 2. The design is implemented using both VHDL and Verilog. A timing report is generated to find the hold and setup times. 3. A constraint file is written for the design. A push button is used for reset, a switch to turn the display off, two 7-segment displays are used, and an LED indicates the 1 second clock signal.

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    Sec 2

    Uploaded by

    Anuradha Khalkho
    31 views6 pages
    1. The document describes a design to generate a 1 second clock signal from a global clock on a Basys 3 board and display the seconds count on two 7-segment displays from 0 to 60. 2. The design is implemented using both VHDL and Verilog. A timing report is generated to find the hold and setup times. 3. A constraint file is written for the design. A push button is used for reset, a switch to turn the display off, two 7-segment displays are used, and an LED indicates the 1 second clock signal.

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    1. The document describes a design to generate a 1 second clock signal from a global clock on a Basys 3 board and display the seconds count on two 7-segment displays from 0 to 60. 2. The design is implemented using both VHDL and Verilog. A timing report is generated to find the hold and setup times. 3. A constraint file is written for the design. A push button is used for reset, a switch to turn the display off, two 7-segment displays are used, and an LED indicates the 1 second clock signal.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    31 views6 pages

    Sec 2

    Uploaded by

    Anuradha Khalkho
    1. The document describes a design to generate a 1 second clock signal from a global clock on a Basys 3 board and display the seconds count on two 7-segment displays from 0 to 60. 2. The design is implemented using both VHDL and Verilog. A timing report is generated to find the hold and setup times. 3. A constraint file is written for the design. A push button is used for reset, a switch to turn the display off, two 7-segment displays are used, and an LED indicates the 1 second clock signal.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 6

    SECTION II

    1. Design module to generate 1 second clock signal (clock period = 1 sec )


    from global clock available on Basys 3 Board. 2. Display the second count on
    two 7-segment LED display. The count must start from 0 and must be finish at
    60. 3. Implement design using both VHDL and Verilog. Also generate timing
    report and find hold and setup time for system. 4. Write constraint file for
    above design. Use push button for reset of module; use switch to off the
    display (in off condition display should how 00); use two 7-segment display;
    use LED for 1 second clock signal. Make detailed report and upload it. Report
    can be document file or pdf file. You can add hand calculation and block
    diagram to justify your result.

    1.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity clockmodule is
    port (clk1 : in std_logic;
    seconds : out std_logic_vector(5 downto 0));
    end clockmodule;

    architecture behavioral of clockmodule is


    signal sec : integer range 0 to 60 :=0;
    signal count : integer :=1;
    signal clk : std_logic :='0';

    begin
    seconds <= conv_std_logic_vector(sec,6);

    --clk generation.For 100 MHz clock this generates 1 Hz clock.


    process(clk1)
    begin
    if(clk1'event and clk1='1') then
    count <=count+1;
    if(count = 50000000) then
    clk <= not clk;
    count <=1;
    end if;
    end if;
    end process;

    process(clk) --period of clk is 1 second.


    begin

    if(clk'event and clk='1') then


    sec <= sec+ 1;
    if(sec = 59) then
    sec<=0;
    end if;
    end if;
    end process;
    end behavioral;

    output waveform:

    2. Display the second count on two 7-segment LED display. The count must
    start from 0 and must be finish at 60.
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity clockmodule is
    port (clk1 : in std_logic;
    clks :in std_logic;
    bt_min0, bt_min1, bt_hour : in std_logic;
    An: out std_logic_vector(3 downto 0);
    disp : out std_logic_vector(6 downto 0);
    end clockmodule;

    architecture behavioral of digi_clk is


    signal sec : integer range 0 to 60 :=0;
    signal min0, hour0 : integer range 0 to 13 := 0;
    signal min1 : integer 0 to 6 := 0;
    signal count : integer :=0;
    signal acount : integer range 0 to 3 :=0;
    signal tmp_an : std_logic_vector (3 downto 0);

    begin
    realclock: process (clks, bt_min0, bt_min1, bt_hour )
    begin
    if (rsisng_edge(clks)) then
    min0 <= min0 + 1;
    sec <= 0;
    if (min0 =10) then
    min1 <= min1 +1;
    min0 <= 0;
    if (min1 = 6) then
    hour0 <= hour0 +1;
    min0 <=0;
    min1 <= 1;
    hour0 <= 0;
    end if;
    end if;
    end if;
    elsif(bt_min1 = '1') then
    min1 <= min1 +1;
    elsif (bt_hour ='1') then
    hour0 <= hour0 +1;
    end if;
    end if;
    end process;

    anode_clk : process (count, acount, clk1)


    begin
    count <= count +1;
    if(count <= 24999) then
    acount <= acount +1;
    count <= 0;
    end if;
    end if;
    end process;

    anode_disp : process (acounter)


    begin
    An <= tmp_an;
    case acount is
    when 0 =>
    tmp_an <= "1110";
    if (min0 = 0) then
    disp <= ""1000000";
    elsif min0= 1 then
    disp <= "1111001";
    elsif min0= 2 then
    disp <= "0100100";
    elsif min0= 3 then
    disp <= "0110000";
    elsif min0= 4 then
    disp <= "0011001";
    elsif min0= 5 then
    disp <= "0010010";
    elsif min0= 6 then
    disp <= "0000010";
    elsif min0= 7 then
    disp <= "1111000";
    elsif min0= 8 then
    disp <= "0000000";
    elsif min0= 9 then
    disp <= "0011000";
    end if;

    when 1 =>
    tmp_an <= "1101";
    if (min1 = 0) then
    disp <= ""1000000";
    elsif min1= 1 then
    disp <= "1111001";
    elsif min1= 2 then
    disp <= "0100100";
    elsif min1= 3 then
    disp <= "0110000";
    elsif min1= 4 then
    disp <= "0011001";
    elsif min1= 5 then
    disp <= "0010010";
    elsif min1= 6 then
    disp <= "10000000";
    end if;

    when 2 =>
    tmp_an <= "1011";
    if (min0 = 0) then
    disp <= ""1000000";
    elsif hour0= 1 then
    disp <= "1111001";
    elsif hour0= 2 then
    disp <= "0100100";
    elsif hour0= 3 then
    disp <= "0110000";
    elsif hour0= 4 then
    disp <= "0011001";
    elsif hour0= 5 then
    disp <= "0010010";
    elsif hour0= 6 then
    disp <= "0000010";
    elsif hour0= 7 then
    disp <= "1111000";
    elsif hour0= 8 then
    disp <= "0000000";
    elsif hour0= 9 then
    disp <= "0011000";
    elsif hour0= 10 then
    disp <= "1000000";
    elsif hour0= 11 then
    disp <= "1111001";
    elsif hour0= 12 then
    disp <= "0100100";
    elsif hour0= 13 then
    disp <= "1000000";
    end if;
    when 3 =>
    tmp_an <= "0111";
    if hour0= 10 then
    disp <= "1111001";
    elsif hour0= 11 then
    disp <= "1111001";
    elsif hour0= 12 then
    disp <= "1111001";
    else
    disp <= "10000000";
    end if;
    end case;
    end process;

    end behavioral;

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