PIC16F84A

2.2 Data Memory Organization FIGURE 2-2: REGISTER FILE MAP -

PIC16F84A
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the File Address File Address
second is the General Purpose Registers (GPR) area. 00h Indirect addr.(1) Indirect addr.(1) 80h
The SFRs control the operation of the device.
01h TMR0 OPTION_REG 81h
Portions of data memory are banked. This is for both
02h PCL PCL 82h
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general 03h STATUS STATUS 83h
purpose RAM. The banked areas of the SFR are for the 04h FSR FSR 84h
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection. 05h PORTA TRISA 85h
These control bits are located in the STATUS Register. 06h PORTB TRISB 86h
Figure 2-2 shows the data memory map organization. 07h — — 87h
Instructions MOVWF and MOVF can move values from 08h EEDATA EECON1 88h
the W register to any location in the register file (“F”), 09h EEADR EECON2(1) 89h
and vice-versa.
0Ah PCLATH PCLATH 8Ah
The entire data memory can be accessed either
0Bh INTCON INTCON 8Bh
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR) 0Ch 8Ch
(Section 2.5). Indirect addressing uses the present
value of the RP0 bit for access into the banked areas of
data memory. 68
General Mapped
Data memory is partitioned into two banks which Purpose (accesses)
contain the general purpose registers and the special Registers in Bank 0
(SRAM)
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers, implemented as static RAM. 4Fh CFh
50h D0h
2.2.1 GENERAL PURPOSE REGISTER
FILE
Each General Purpose Register (GPR) is 8-bits wide
and is accessed either directly or indirectly through the
FSR (Section 2.5).
7Fh FFh
The GPR addresses in Bank 1 are mapped to Bank 0 Bank 1
addresses in Bank 0. As an example, addressing loca- Unimplemented data memory location, read as ’0’.
tion 0Ch or 8Ch will access the same GPR.
Note 1: Not a physical register.

DS35007B-page 6  2001 Microchip Technology Inc.

PIC16F84A
TABLE 7-2: PIC16CXXX INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status

Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1 (2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1 (2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).

DS35007B-page 36  2000 Microchip Technology Inc.