Adv7280a 7281a 7282a Ug 1176

ADV7280A/ADV7281A/ADV7282A Device Manual
UG-1176
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADV7280A/ADV7281A/ADV7282A Functionality and Features

SCOPE The automatic gain control (AGC) and clamp restore circuitry
This user guide provides a detailed description of the functionality allow an input video signal peak-to-peak range of 1.0 V at the
and features of the ADV7280A, ADV7280A-M, ADV7281A-M, analog video input pin of the ADV7280A, ADV7281A, and
ADV7282A, and ADV7282A-M video decoders. ADV7282A devices. Alternatively, these can be bypassed for
manual settings.
All features, functionality, and specifications are shared by the
ADV7280A, ADV7280A-M, ADV7281A-M, ADV7282A, and AC coupling of the input video signals provides short to battery
ADV7282A-M models, unless otherwise noted. They are referred (STB) protection. On the ADV7281A, ADV7282A, and
to as the ADV7280A, ADV7281A, and ADV7282A devices in this ADV7281A devices, STB diagnostics can be carried out on two
user guide. input video signals.
The ADV7280A, ADV7280A-M, ADV7281A-M, ADV7282A, The ADV7280A, ADV7281A, and ADV7282A devices are
and ADV7282A-M automatically detect and convert standard programmed via a 2-wire, serial, bidirectional port (I2C
composite analog baseband video signals compatible with compatible). The ADV7280A, ADV7281A, and ADV7282A
worldwide National Television System Committee (NTSC), devices support a number of functions including 8-bit to 6-bit
phase alternating line (PAL), and sequential color with memory downdither mode and adaptive contrast enhancement (ACE).
(SECAM) standards. These video recorders accept composite video The advanced interlaced to progressive (I2P) function allows the
signals (CVBS) as well as S-Video (Y/C) and YPbPr video signals, ADV7280A, ADV7281A, ADV7282A, and ADV7282A-M devices
supporting a wide range of consumer and automotive video to convert an interlaced video input into a progressive video output.
sources. The ADV7281A-M, ADV7282A, and ADV7282A-M This function is performed without the need for external memory.
models can also accept pseudo differential and true differential Edge adaptive technology minimizes video defects on low angle
CVBS inputs. lines.
The ADV7280A, ADV7281A-M, and ADV7282A models convert The ADV7280A, ADV7281A, and ADV7282A devices are
the analog video inputs into a YCrCb 4:2:2 component video data fabricated in a 1.8 V complementary metal-oxide semiconductor
stream that is compatible with the 8-bit ITU-R BT.656 interface (CMOS) process. Its monolithic CMOS construction ensures
standard. greater functionality with lower power dissipation. The
The ADV7280A-M, ADV7281A-M, and ADV7282A-M models ADV7280A, ADV7281A, and ADV7282A devices are available in
convert the analog video inputs into an 8-bit YCrCb 4:2:2 video a variety of temperature ranges making them suitable for a range of
stream, and output over an MIPI CSI-2 (referred to as MIPI Tx) industrial and automotive applications.
interface. This MIPI Tx output interface connects to a wide range See Table 2 for a descriptive list of these video decoder models.
of video processors and field programmable gate arrays (FPGAs). A full description of the ADV7280A, ADV7281A, and ADV7282A
is available in the ADV7280A, ADV7281A, and ADV7282A data
sheets and should be consulted in conjunction with this hardware
reference manual.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 81
UG-1176 ADV7280A/ADV7281A/ADV7282A Device Manual
TABLE OF CONTENTS
Scope ................................................................................................... 1 Video Processor .............................................................................. 16
Revision History ................................................................................. 3 SD Luma Path ............................................................................. 16
General Description ......................................................................... 4 SD Chroma Path ......................................................................... 16
Overview of Analog Front End .................................................. 4 ACE, I2P, and Dither Processing Blocks .................................. 17
Overview of SDP .......................................................................... 4 Sync Processing .......................................................................... 17
Input Networks ............................................................................. 4 VBI Data Recovery..................................................................... 17
STB Diagnostics ............................................................................ 4 General Setup .............................................................................. 17
Video Decoder Models .................................................................... 5 Color Controls ............................................................................ 19
Video Input Pins Column ........................................................... 5 Free Run Operation ................................................................... 20
Differential AFE Column ............................................................ 5 Clamp Operation........................................................................ 21
Output Format Column .............................................................. 5 Luma Filter .................................................................................. 23
Diagnostic Pins Column ............................................................. 5 Chroma Filter.............................................................................. 26
GPO Pins Column........................................................................ 5 Gain Operation ........................................................................... 27
Sync Output Pins Column .......................................................... 5 CTI ............................................................................................... 30
ACE Column ................................................................................. 5 Digital Noise Reduction (DNR) and Luma Peaking Filter ... 30
2
I P Column .................................................................................... 5 Comb Filters ................................................................................ 31
Package Column ........................................................................... 5 IF Filter Compensation ............................................................. 33
Interrupts and STB Functionality................................................... 6 ACE .............................................................................................. 33
Programming Diagnostic Interrupt ........................................... 6 Dither Function .......................................................................... 35
Programming the INTRQ Hardware Interrupt ........................ 7 I2P Function ................................................................................ 35
Analog Front End ............................................................................. 8 Output Video Format..................................................................... 36
Input Configuration ..................................................................... 8 Swap Color Output .................................................................... 36
Manual Muxing Mode ................................................................. 9 Output Format Control ............................................................. 36
Antialiasing Filters .......................................................................... 12 ITU-R BT.656 Output .................................................................... 37
Antialiasing Filter Configuration ............................................. 12 ITU-R BT.656 Output Control Registers ................................ 37
Global Control Registers ............................................................... 13 MIPI CSI-2 Tx Output ................................................................... 39
Power Saving Mode and Reset Control ................................... 13 Ultra Low Power State ............................................................... 39
Global Pin Control ..................................................................... 13 Power Supply Requirements ......................................................... 41
GPO Controls ............................................................................. 13 I2C Register Maps ........................................................................... 42
Global Status Register .................................................................... 15 User Sub Map Description ........................................................ 48
Identification ............................................................................... 15 User Sub Map 2 Description ..................................................... 67
Status 1 ......................................................................................... 15 Interrupt/VDP Sub Map Description ...................................... 69
Status 2 ......................................................................................... 15 VPP Map Description ................................................................ 77
Status 3 ......................................................................................... 15 MIPI CSI-2 Tx Map Description ............................................. 77
Autodetection Result.................................................................. 15
Rev. A | Page 2 of 80
ADV7280A/ADV7281A/ADV7282A Device Manual UG-1176
REVISION HISTORY
6/2018—Rev. 0 to Rev. A Change to Dither Function Section .......................................................35
Changes to DIAG_TRI1_L1_MSK, Address 0x55, Bit 1, Changed 0x42 to 0x43 in Hex Column, Address 0x11,
Interrupt/VDP Sub Map Section and DIAG_TRI2_L1_MSK, Table 87 ............................................................................................. 42
Address 0x55, Bit 3, Interrupt/VDP Sub Map Section ........................6 Changes to Register Name Column, Address 0x20, Table 91..........47
Changed AA_FILT_EN[3], Address 0xF3, Bit 2 Section to Changed 0x42 to 0x43 in Comments Column, Address 0x11,
AA_FILT_EN[3], Address 0xF3, Bit 3 Section................................... 12 Table 92 .........................................................................................................51
Changed 0x42 to 0x43 in Address Column, Table 18 ................15 Changes to Functionality Column, Address 0x39, Table 92 and Bit
Changed FSCLE, Address 0x51, Bit 6, User Sub Map Section to Description Column, Address 0x3A, Table 92 ....................................58
FSCLE, Address 0x51, Bit 7, User Sub Map Section.......................... 19 Changes to Register Name Column, Address 0xDE, Table 93 ........68
Change to Table 35 Title ........................................................................... 21
Changes to Figure 12 ................................................................................. 22 9/2017—Revision 0: Initial Version
GENERAL DESCRIPTION
OVERVIEW OF ANALOG FRONT END Video user controls, such as brightness, contrast, saturation, and
The analog front end (AFE) of the ADV7280A, ADV7281A, and hue, are also available with these video decoders.
ADV7282A devices consists of a single high speed, 10-bit analog- The ADV7280A, ADV7281A, and ADV7282A devices implement
to-digital converter (ADC) that digitizes the analog video signal a patented Adaptive Digital Line Length Tracking (ADLLT™)
before applying it to the standard definition processor (SDP). algorithm to track varying video line lengths from sources such as a
The front end also includes a 4-channel input mux that enables VCR. ADLLT enables the devices to track and decode poor quality
multiple composite video signals applied to the ADV7280A, video sources, such as VCRs and noisy sources, from tuner outputs
ADV7281A, and ADV7282A devices. Clamp restore circuitry is and camcorders. The ADV7280A, ADV7281A, and ADV7282A
positioned in front of the ADC to ensure the video signal remains devices contain a chroma transient improvement (CTI) processor
within the range of the converter. Place an external resistor and that sharpens the edge rate of chroma transitions, resulting in
capacitor circuit before each analog input channel to ensure the sharper vertical transitions.
input signal is kept within the range of the ADC (see the Input ACE offers improved visual detail using an algorithm to
Networks section). Fine clamping of the video signal is performed automatically vary contrast levels to enhance picture detail. This
downstream by digital fine clamping within the ADV7280A, algorithm increases the brightness of dark regions of an image
ADV7281A, and ADV7282A devices. without saturating bright areas of the image.
Table 1 shows the three ADC clocking rates that are determined Downdithering converts the output of the ADV7280A,
by the video input format to be processed—that is, INSEL[4:0]. ADV7281A, and ADV7282A devices from 8-bit outputs to 6-bit
These clock rates ensure 4× oversampling per channel for the outputs.
CVBS, Y/C, and YPbPr modes. The I2P block on the ADV7280A, ADV7280A-M, ADV7282A, and
Table 1. ADC Clock Rates ADV7282A-M converts the interlaced video input into a
progressive video output. This conversion is done without a need
Oversampling
Input Format ADC Clock Rate (MHz)1 Rate per Channel for external memory.
CVBS 57.27 4× The ADV7280A, ADV7281A, and ADV7282A devices can process
Y/C (S-Video) 114 4× a variety of vertical blanking interval (VBI) data services, such as
YPbPr 172 4× closed captioning (CCAP), widescreen signaling (WSS), and copy
generation management systems (CGMS). VBI data is transmitted
1
Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.
as ancillary data packets.
OVERVIEW OF SDP
The ADV7280A, ADV7281A, and ADV7282A devices are fully
The ADV7280A, ADV7281A, and ADV7282A devices are capable Rovi compliant (formerly Macrovision® and now rebranded as
of decoding a large selection of baseband video signals in TiVo® upon acquisition of the same); detection circuitry identify
composite, S-Video, and component formats. The ADV7281A-M, and report Type I, Type II, and Type III protection levels. The
ADV7282A and ADV7282A-M are also capable of receiving decoder is also fully robust to all Rovi signal inputs.
pseudo differential and fully differential CVBS inputs. The video
standards supported by the video processor include PAL B/ PAL D/ INPUT NETWORKS
PAL I/PAL G/PAL H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/ An input network (external resistor and capacitor circuit)
NTSC J, NTSC 4.43, and SECAM B/SECAM D/SECAM G/ is required on the AINx input pins of the ADV7280A, ADV7281A,
SECAM K/SECAM L. The ADV7280A, ADV7281A, and and ADV7282A devices. The components of the input network
ADV7282A devices can automatically detect the video standard depend on the video format selected for the analog input.
and process it accordingly. The available input networks include a single-ended input network
The ADV7280A, ADV7281A, and ADV7282A devices have a and a differential input network. Refer to the ADV7280A,
five-line, adaptive, 2D comb filter that gives superior chrominance ADV7281A, and ADV7282A data sheets for more information.
and luminance separation when decoding a composite video STB DIAGNOSTICS
signal. This highly adaptive filter automatically adjusts its
processing mode according to the video standard and signal STB diagnostic pins are only available on the ADV7281A-M,
quality without requiring user intervention. ADV7282A, and ADV7282A-M models. See the ADV7281A and
ADV7282A data sheets for more information.
VIDEO DECODER MODELS

Table 2 lists the Analog Devices, Inc., video decoders described in this reference manual. Select columns are described in full in the
sections that follow.
Table 2. Description of Models of ADV7280A, ADV7281A, and ADV7282A Devices

Model Video Differential Output Diagnostic GPO Sync Output
Number Input Pins AFE Format Pins Pins Pins ACE I2P Package
ADV7280A 4 No ITU-R None None Yes Yes Yes 32-lead LFCSP,
BT.656 5 mm × 5 mm
ADV7280A-M 8 No MIPI Tx None 3 No Yes Yes 32-lead LFCSP,
5 mm × 5 mm
ADV7281A-M 6 Yes MIPI Tx 2 3 No Yes No 32-lead LFCSP,
5 mm × 5 mm
ADV7282A 4 Yes ITU-R 2 None No Yes Yes 32-lead LFCSP,
BT.656 5 mm × 5 mm
ADV7282A-M 6 Yes MIPI Tx 2 3 No Yes Yes 32-lead LFCSP,
5 mm × 5 mm
VIDEO INPUT PINS COLUMN DIAGNOSTIC PINS COLUMN

The video input pins column indicates how many analog video The diagnostic pins column indicates if the ADV7280A,
inputs pins are available on each model of the ADV7280A, ADV7281A, and ADV7282A devices have diagnostic pins and
ADV7281A, and ADV7282A devices. The following section how many diagnostic pins they have. Diagnostic pins monitor
outlines the number of pins required for each type of video input: analog video input lines for STB events.
• One analog video input pin is required for single-ended CVBS GPO PINS COLUMN
inputs. The GPO pins column indicates if the ADV7280A, ADV7281A,
• Two analog video input pins are required for pseudo and ADV7282A devices have general-purpose output (GPO) pins
differential and fully differential CVBS inputs. and how many GPO pins they have. GPO pins are outputs from the
• Two analog video input pins are required for S-Video (Y/C) ADV7280A, ADV7281A, and ADV7282A devices that can control
inputs. external devices.
• Three analog video input pins are required for component
SYNC OUTPUT PINS COLUMN
(YPbPr) inputs.
The sync output pins column indicates if the video decoder has
DIFFERENTIAL AFE COLUMN synchronization output pins and how many synchronization
The differential AFE column indicates if the ADV7280A, output pins they have. Examples of synchronization output pins
ADV7281A, and ADV7282A devices have a differential analog include horizontal synchronization (HS), vertical synchronization
front end (AFE). A differential AFE is needed to process pseudo (VS), and subcarrier frequency lock (SFL).
differential and fully differential CVBS inputs. ACE COLUMN
OUTPUT FORMAT COLUMN The ACE column indicates if the ADV7280A, ADV7281A, and
The output format column indicates the digital video output format ADV7282A devices have the ability to perform the ACE function.
output from each ADV7280A, ADV7281A, and ADV7282A The ACE function allows dark areas of the video to brighten
model. without saturating bright areas. This is useful for automotive
• ITU-R BT.656 means that the ADV7280A, ADV7281A, or applications.
ADV7282A model outputs 8-bit YUV video data bus. I2P COLUMN
• MIPI Tx indicates that the ADV7280A-M, ADV7281A-M,
The I2P column indicates if the ADV7280A, ADV7281A, and
and ADV7282A-M models output 8-bit YUV video data over
ADV7282A devices have a built in I2P, or a deinterlacer. The I2P
a MIPI Tx bus. This MIPI Tx bus consists of one differential
core converts the interlaced video formats of NTSC (480i) or PAL
data channel (composed of the D0P and D0N signals) and one
(576i) into progressive standards (480p or 576p).
differential clock channel (composed of the CLKP and CLKN
signals). PACKAGE COLUMN
The package column indicates the package in which the video
decoder is available. See the ADV7280A, ADV7281A, and
ADV7282A data sheets for the corresponding functional block
diagrams.
INTERRUPTS AND STB FUNCTIONALITY

This section describes the interrupt operation of the Diagnostic Interrupt Status
ADV7280A, ADV7281A, and ADV7282A using the STB feature.
The DIAG_TRI1_L1 and DIAG_TRI2_L1 bits give the status of the
The ADV7281A and ADV7282A data sheets include an diagnostic interrupt (that is, if a STB event occurs or not).
overview of the STB capabilities available in the ADV7281A-M,
DIAG_TRI1_L1, Address 0x53, Bit 1, Interrupt/VDP
ADV7282A, and ADV7282A-M models. Use this section in
conjunction with the ADV7281A and ADV7282A data sheets
Sub Map
when using the STB feature. Diagnostic Interrupt 1 status. This read only register shows the
status of the interrupt for Diagnostic Pin 1, that is, if a STB event
PROGRAMMING DIAGNOSTIC INTERRUPT
has occurred on the DIAG1 pin. An STB event is deemed to have
This section describes how to program software interrupt bits to occurred when the voltage on the DIAG1 pin exceeds the
toggle when STB events are detected on the diagnostic pins. A diagnostic slice level; see the ADV7281A and ADV7282A data
hardware interrupt indicated by the INTRQ pin also triggers when sheets for more information. When triggered, the DIAG_
a software interrupt activates. Details on how to control the INTRQ TRI1_L1 bit remains high until cleared (see the Clearing
pin hardware interrupt are given in the Programming the Diagnostic Interrupts section).
Hardware Interrupt section.
Table 5. DIAG_TRI1_L1 Function
Before programming the software diagnostic interrupts, the
Setting Description
diagnostic circuitry must first be activated and the diagnostic slice
0 Voltage higher than DIAG1_SLICE_LEVEL not detected on
level must be programmed; see the ADV7281A and ADV7282A DIAG1 pin
data sheets for more information. 1 Voltage higher than DIAG1_SLICE_LEVEL detected on DIAG1
Unmask the diagnostic interrupts (that is, activate) using the pin
DIAG_TRI1_L1_MSK and DIAG_TRI2_L1_MSK bits.
DIAG_TRI2_L1, Address 0x53, Bit 3, Interrupt/VDP
When a STB event is detected, the interrupt status bits Sub Map
DIAG_TRI1_L1 and DIAG_TRI2_L1 toggles from 0 to 1.
Diagnostic Interrupt 2 status. This read only register, shows the
The DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts remains at 1 status of the interrupt for Diagnostic Pin 2, that is, if a STB event
until they are cleared. has occurred on the DIAG2 pin. An STB event is deemed to have
DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts are cleared by occurred when the voltage on the DIAG2 pin exceeds the
writing 1 to the DIAG_TRI1_L1_CLR and DIAG_TRI2_ diagnostic slice level; see the ADV7281A and ADV7282A data
L1_CLR bits. sheets for more information. When triggered, the DIAG_
Unmasking Diagnostic Interrupts TRI2_L1 bit remains high until cleared (see the Clearing
Diagnostic Interrupts section).
The DIAG_TRI1_L1_MSK and DIAG_TRI2_L1_MSK bits
unmask (that is, activate) the diagnostic interrupts. Table 6. DIAG_TRI2_L1 Function
Setting Description
DIAG_TRI1_L1_MSK, Address 0x55, Bit 1, Interrupt/VDP
0 Voltage higher than DIAG2_SLICE_LEVEL not detected on the
Sub Map DIAG2 pin
Unmask Diagnostic Interrupt 1.This unmasks (that is, activates) 1 Voltage higher than DIAG2_SLICE_LEVEL detected on the
the STB interrupt for Diagnostic Pin 1 (DIAG1). DIAG2 pin
Table 3. DIAG_TRI1_L1_MSK Function Clearing Diagnostic Interrupts

Setting Description The DIAG_TRI1_L1_CLR and DIAG_TRI2_L1_CLR bits clear the
0 (default) Masks DIAG_TRI1_L1 interrupt diagnostic interrupts.
1 Unmasks DIAG_TRI1_L1 interrupt
DIAG_TRI1_L1_CLR, Address 0x54, Bit 1,
DIAG_TRI2_L1_MSK, Address 0x55, Bit 3, Interrupt/VDP Interrupt/VDP Sub Map
Sub Map Clear Diagnostic Interrupt 1. This bit clears the interrupt for
Diagnostic Pin 1 (DIAG1).
Unmask Diagnostic Interrupt 2.This unmasks (that is, activates)
the STB interrupt for Diagnostic Pin 2 (DIAG2). The DIAG_TRI1_L1_CLR is a self clearing, write only bit.
Table 4. DIAG_TRI2_L1_MSK Function Table 7. DIAG_TRI1_L1_CLR Function

Setting Description DIAG_TRI1_L1_CLR Description
0 (default) Masks DIAG_TRI2_L1 interrupt 0 (default) Do not clear DIAG_TRI1_L1
1 Unmasks DIAG_TRI2_L1 interrupt 1 Clear DIAG_TRI1_L1
DIAG_TRI2_L1_CLR, Address 0x54, Bit 3, In drive low when in active mode, the INTRQ pin is at DVDDIO
Interrupt/VDP Sub Map voltage when not active and drives low when active. The INTRQ
Clear Diagnostic Interrupt 2. This bit clears the interrupt for pin does not require a pull-up resistor to DVDDIO.
Diagnostic Pin 2 (DIAG2). In drive high when in active mode, the INTRQ pin is at ground
The DIAG_TRI2_L1_CLR is a self clearing, write only bit. (GND) when not active and drives high to DVDDIO when active. The
INTRQ pin does not require a pull-up resistor to DVDDIO.
Table 8. DIAG_TRI2_L1_CLR Function
Setting Description Table 9. INTRQ_OP_SEL[1:0] Function
0 (default) Do not clear DIAG_TRI2_L1 Setting Description
1 Clear DIAG_TRI2_L1 00 (default) Open drain
01 Drive low when active
PROGRAMMING THE INTRQ HARDWARE 10 Drive high when active
INTERRUPT 11 Reserved
When a software interrupt is unmasked and triggered, a hardware

INTRQ_DUR_SEL[1:0], Address 0x40, Bits[7:6],
interrupt indicated by the INTRQ pin also automatically triggers. Interrupt/VDP Sub Map
An example of how to program a software interrupt is given in the The INTRQ_DUR_SEL[1:0] bits set the duration of the INTRQ
Programming Diagnostic Interrupt section. Other software interrupt output.
interrupts can be programmed in a similar manner. See Table 94
for other software interrupts available on the ADV7280A, The duration of the INTRQ interrupt output is given in terms of
ADV7281A-M, and ADV7282A devices. crystal clock periods. A 28.63636 MHz crystal corresponds to a
clock period of approximately 35 ns.
The INTRQ_OP_SEL[1:0] bits program the INTRQ hardware
interrupt to drive out in a variety of ways (for example, drive the The INTRQ interrupt output can also be set to be active until
INTRQ pin high, drive the INTRQ pin low, or make the INTRQ cleared. In this mode of operation, the INTRQ pin is active until
pin open drain). every active software interrupt clears.
The INTRQ_DUR_SEL[1:0] bits set the duration of the INTRQ Table 10. INTRQ_DUR_SEL[1:0] Function
interrupt output. Setting Description
INTRQ_OP_SEL[1:0], Address 0x40 Bits[1:0], 00 (default) 3 crystal periods ( approximately 0.105 µs)
Interrupt/VDP Sub Map 01 15 crystal periods (approximately 0.525 µs)
10 63 crystal periods (approximately 2.205 µs)
The INTRQ_OP_SEL[1:0] bits program the INTRQ hardware
11 Active until cleared
interrupt to drive out in a variety of ways when active.
In open-drain mode, the INTRQ pin is at the DVDDIO voltage when
not active and drives low when active. The INTRQ pin requires
a pull-up resistor to DVDDIO for the INTRQ interrupt to work.
ANALOG FRONT END

INPUT CONFIGURATION MAN_MUX_EN
The following two steps are key for configuring the ADV7280A,
ADV7281A, and ADV7282A devices to correctly decode the
AIN1
input video: AIN2 MUX_0P[3:0]
AIN3
1. Use the INSEL[4:0] bits to configure the routing and format AIN4
decoding (CVBS, Y/C, or YPrPb).
2. If the input requirements are not met using the INSEL[4:0] AIN2
AIN4
options, the analog input muxing section must be configured MUX_0N[3:0]
manually to correctly route the video from the analog input

pins to the ADC. Configure the SDP block, which decodes the
digital data, to process the CVBS, Y/C, or YPrPb format. This AIN2 ADC
is performed by the INSEL[4:0] setting. AIN4

MUX_1[3:0]
For a full description of the INSEL[4:0] input formats, see the

ADV7280A, ADV7281A, and ADV7282A data sheets.
AIN2
MAN_MUX_EN
MUX_2[3:0]
16169-003
AIN1 Figure 3. Manual Muxing Scheme for ADV7282A
AIN2 MUX_0P[3:0]
AIN3
AIN4 MAN_MUX_EN
AIN1
AIN2
AIN4 AIN2
AIN3
MUX_1[3:0] AIN4 MUX_0P[3:0]
AIN5
AIN6
AIN2 ADC AIN2

AIN3 AIN4
MUX_2[3:0] AIN6 MUX_0N[3:0]
16169-001
Figure 1. Manual Muxing Scheme for ADV7280A ADC

AIN2
AIN4
MAN_MUX_EN AIN6 MUX_1[3:0]
AIN1
AIN2
AIN3
AIN4
AIN5 AIN2
AIN6 MUX_0P[3:0] AIN3 MUX_2[3:0]
AIN7
16169-004
AIN8
AIN2
AIN4 Figure 4. Manual Muxing Scheme for ADV7281A-M and ADV7282A-M
AIN5 MUX_1[3:0]
AIN6
AIN8
AIN2 ADC
AIN3
AIN6 MUX_2[3:0]
16169-002
Figure 2. Manual Muxing Scheme for ADV7280A-M
MANUAL MUXING MODE MUX_0N[3:0] cannot be powered down independently. MUX_0N
In manual muxing mode, the user selects any analog input pin that can only be powered down when MUX_0P[3:0], MUX_1[3:0], and
is to be processed by the ADC of the ADV7280A, ADV7281A, and MUX_2[3:0] are all powered down.
ADV7282A devices. MAN_MUX_EN (User Map, Register 0xC4, Manual Muxing of the ADV7280A and ADV7280A-M
Bit 7) must be set to 1 to enable the following muxing blocks: Table 11 shows the settings for manual muxing of the ADV7280A.
• MUX_0P[3:0], ADC mux configuration, Address 0xC3, To setup manual muxing for the ADV7280A, complete the
Bits[3:0] following steps:
• MUX_0N[3:0], ADC mux configuration, Address 0x60, • MAN_MUX_EN must be set to 1 (user sub map, Register
Bits[3:0] (applies only to the ADV7281A-M, ADV7282A, and 0xC4, Bit 7).
ADV7282A-M models) • CVBS can only be processed by MUX_0P[3:0].
• MUX_1[3:0], ADC mux configuration, Address 0xC3, • Y/C can only be processed by MUX_0P[3:0] and
Bits[7:4] MUX_1[3:0]. MUX_0P[3:0] processes the luma (Y) and
• MUX_2[3:0], ADC mux configuration, Address 0xC4, MUX_1[3:0] processes the chroma (C).
Bits[3:0] • Component (YPbPr) signals can only be processed by
The four mux sections are controlled by the signal buses, MUX_0P[3:0] (Y), MUX_1[3:0] (Pb), and MUX_2[3:0] (Pr).
MUX_0P[3:0], MUX_0N[3:0], MUX_2[3:0], and MUX_3[2:0]. Table 12 shows the settings for manual muxing of the
Table 11 and Table 12 explain the control words used. ADV7280A-M. To set up manual muxing for ADV7280A-M,
complete the following steps:
The input signal that contains the timing information (HS and VS)
must be processed by MUX_0P[3:0]. For example, in a Y/C input • MAN_MUX_EN must be set to 1 (User Map, Register 0xC4,
configuration, connect MUX_0P[3:0] to the Y channel and Bit 7).
MUX_1[3:0] to the C channel. • CVBS can only be processed by MUX_0P[3:0].
MUX_0N[3:0] only processes the negative input for fully • Y/C can only be processed by MUX_0P[3:0] and
differential or pseudo differential CVBS inputs. MUX_1[3:0]. MUX_0P[3:0] processes the luma (Y) and
MUX_1[3:0] processes the chroma (C).
When one or more muxes do not process video, such as the CVBS
• Component (YPbPr) signals can only be processed by
input, the idle mux and associated channel clamps and buffers must
MUX_0P[3:0] (Y), MUX_1[3:0] (Pb), and MUX_2[3:0] (Pr).
be powered down (see the description of Register 0x3A in the user
sub map in Table 92).
Table 11. Manual Mux Settings for ADC of ADV7280A

MUX_0P[3:0] ADC Connection MUX_1[3:0] ADC Connected To MUX_2[3:0] ADC Connection
0000 No connect 0000 No connect 0000 No connect
0001 AIN1 0001 No connect 0001 No connect
0010 AIN2 0010 AIN2 0010 AIN2
0011 AIN3 0011 No connect 0011 AIN3
0100 AIN4 0100 AIN4 0100 No connect
0101 to 1111 No connect 0101 to 1111 No connect 0101 to 1111 No connect
Table 12. Manual Mux Settings for ADC of ADV7280A-M

MUX_0P[3:0] ADC Connection MUX_1[3:0] ADC Connected To MUX_2[3:0] ADC Connection
0000 No connect 0000 No connect 0000 No connect
0010 AIN2 0010 AIN2 0010 AIN2
0011 AIN3 0011 No connect 0011 AIN3
0110 AIN6 0110 AIN6 0110 AIN6
1001 to 1111 No connect 1001 to 1111 No connect 1001 to 1111 No connect
Manual Muxing of the ADV7282A • Y/C can only be processed by MUX_0P[3:0] and
Table 14 shows the settings for manual muxing of the ADV7282A. MUX_1[3:0]. MUX_0P[3:0] processes the luma (Y) and
To setup manual muxing for ADV7282A, complete the following MUX_1[3:0] processes the chroma (C).
steps: • Component (YPbPr) signals can only be processed by
• MAN_MUX_EN must be set to 1 (user sub map, Register
For example, Y can be fed in on AIN1 or AIN3 for
0xC4, Bit 7)
MUX_0P[3:0]. Pb can be fed in on AIN4 for MUX_1[3:0]. Pr
• CVBS can only be processed by MUX_0P[3:0].
can be fed in on AIN2 for MUX_2[3:0]. Table 13 gives an
• Differential CVBS can only be processed by MUX_0P[3:0] example of how to program the ADV7282A to accept YPrPb
(positive channel) and MUX_0N[3:0] (negative channel). inputs.
Table 13. Register Writes to Program the ADV7282A to Accept YPbPr Input
Register Register Register
Map Address Write Description
User Sub Map 0x00 0x0C Program INSEL[4:0] for YPbPr input.
0xC3 0x87 Program manual muxing. Y is fed in on AIN3 for MUX_0P[3:0]. Pb is fed in on AIN4 for
MUX_1[3:0].
0xC4 0x82 Enable manual muxing. Pr is fed in on AIN2 for MUX_2[3:0].
Table 14. Manual Mux Settings for ADC of ADV7282A

MUX_0P[3:0] ADC Connection MUX_0N[3:0] ADC Connection MUX_1[3:0] ADC Connection MUX_2[3:0] ADC Connection
0000 No connect 0000 No connect 0000 No connect 0000 No connect
0001 AIN1 0001 No connect 0001 No connect 0001 No connect
0010 AIN2 0010 AIN2 0010 AIN2 0010 AIN2
1000 AIN4 1000 AIN4 1000 AIN4 1000 No connect
1001 to 1111 No connect 1001 to 1111 No connect 1001 to 1111 No connect 1001 to 1111 No connect
Manual Muxing of the ADV7281A-M and ADV7282A-M • Differential CVBS can only be processed by MUX_0P[3:0]
Table 15 shows the settings for manual muxing of the (positive channel) and MUX_0N[3:0] (negative channel).
ADV7281A-M and ADV7282A-M. To set up manual muxing for • Y/C can only be processed by MUX_0P[3:0] and
ADV7281A-M or ADV7282A-M, complete the following steps: MUX_1[3:0]. MUX_0P[3:0] processes the luma (Y) and
MUX_1 processes the chroma (C).
• MAN_MUX_EN must be set to 1 (user sub map,
• Component (YPbPr) signals can only be processed by
Register 0xC4, Bit 7)
• CVBS can only be processed by MUX_0P[3:0].
Table 15. Manual Mux Settings for ADC of ADV7281A-M and ADV7282A-M
MUX_0P[3:0] ADC Connection MUX_0N[3:0] ADC Connection MUX_1[3:0] ADC Connection MUX_2[3:0] ADC Connection
0010 AIN2 0010 AIN2 0010 AIN2 0010 AIN2
0011 AIN3 0011 No connect 0011 No connect 0011 AIN3
1001 to 1111 No connect 1001 to 1111 No connect 1001 to 1111 No connect 1001 to 1111 No connect
ANTIALIASING FILTERS
The ADV7280A, ADV7281A, and ADV7282A devices have The antialiasing filters are enabled by default and the selection of
optional on-chip antialiasing (AA) filters on each of the four INSEL[4:0] determines which filters are powered up at any given
channels that are multiplexed to the ADC (see Figure 5). time. For example, if CVBS mode is selected, the filter circuits for
the remaining input channels are powered down to conserve
10-BIT, 86MHz
ADC power. However, the antialiasing filters can be disabled or bypassed
AA
AIN1
AIN2
FILTER 1 using the AA_FILT_MAN_OVR control.
MUX BLOCK
AIN3 AA
AIN4 FILTER 2 +
SHA ADC
ANTIALIASING FILTER CONFIGURATION
AIN5 AA
AIN6 FILTER 3
– AA_FILT_MAN_OVR, Address 0xF3, Bit 4, User Sub Map
AIN7
AIN8
AA
FILTER 4 This feature allows the user to override the on/off settings of the
antialiasing filters, which are automatically selected by INSEL[4:0].
NOTES
1. EIGHT ANALOG INPUTS ARE ONLY AVAILABLE
ON THE ADV7280A-M. AA_FILT_EN3 to AA_FILT_EN0, Address 0xF3, Bits[3:0],
SIX ANALOG INPUTS ARE AVAILABLE ON THE
ADV7281A-M AND ADV7282A-M
User Sub Map
16169-005
FOUR ANALOG INPUTS ARE AVAILABLE ON

THE ADV7280A, ADV7281A, AND ADV7282A. These bits allow the user to enable or disable the antialiasing filters
Figure 5. Antialias Filter Configuration
on each of the three input channels multiplexed to the ADC. When
disabled, the analog signal bypasses the AA filters and is routed
The filters are designed for SD video up to 10 MHz bandwidth. directly to the ADC.
Figure 6 and Figure 7 show the filter magnitude and phase
AA_FILT_EN[0], Address 0xF3, Bit 0
characteristics.
0 When AA_FILT_EN[0] is set to 0, AA Filter 1 is disabled.
–4 When AA_FILT_EN[0] is set to 1, AA Filter 1 is enabled.
–8 AA_FILT_EN[1], Address 0xF3, Bit 1
–12 When AA_FILT_EN[1] is set to 0, AA Filter 2 is disabled.
MAGNITUDE (dB)
–16 When AA_FILT_EN[1] is set to 1, AA Filter 2 is enabled.

–20 AA_FILT_EN[2], Address 0xF3, Bit 2
–24
When AA_FILT_EN[2] is set to 0, AA Filter 3 is disabled.
–28
When AA_FILT_EN[2] is set to 1, AA Filter 3 is enabled.
–32
AA_FILT_EN[3], Address 0xF3, Bit 3
–36
When AA_FILT_EN[3] is set to 0, AA Filter 4 is disabled.
16169-006
1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)
When AA_FILT_EN[3] is set to 1, AA Filter 4 is enabled.
Figure 6. Antialiasing Filter Magnitude Response
0
–10
–20
–30
–40
–50
PHASE (Degrees)
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
16169-007
1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)
Figure 7. Antialiasing Filter Phase Response
GLOBAL CONTROL REGISTERS

The register control bits listed in this section affect the entire chip. GLOBAL PIN CONTROL
POWER SAVING MODE AND RESET CONTROL Drive Strength Selection (I2C)
Power Down DR_STR_S[1:0], Address 0xF4, Bits[1:0], User Sub Map
PWRDWN, Address 0x0F, Bit 5, User Sub Map The DR_STR_S[1:0] bits allow the user to select the strength of
The ADV7280A, ADV7281A, and ADV7282A devices can be the I2C signal output drivers. These bits affect the drive strength
placed into a chip wide, power-down mode by setting the for the SDATA and SCLK pins.
PWRDWN bit or by using the PWRDWN pin. The power-down Table 16. DR_STR_S Function
mode stops the clock from entering the digital section of the chip, Setting Description
thereby freezing its operation. No I2C bits are lost during power- 00 Low drive strength (1×)1
down mode. The PWRDWN bit also affects the analog blocks and 01 (default) Medium low drive strength (2×)
switches them into low current modes. The I2C interface is 10 Medium high drive strength (3×)
unaffected and remains operational in power-down mode. 11 High drive strength (4×)
When PWRDWN is set to 0, the chip is operational. When 1
The low drive strength setting is not recommended for the optimal performance
PWRDWN is set to 1 (default), the ADV7280A, ADV7281A, and of the ADV7280A, ADV7281A, and ADV7282A devices.
ADV7282A devices are in a chip wide, power-down mode.
GPO CONTROLS
Chip Reset
The ADV7280A-M, ADV7281A-M, and ADV7282A-M have three
Reset, Address 0x0F, Bit 7, User Sub Map GPOs.
Setting this bit, which is equivalent to controlling the RESET pin on These outputs allow the user to control other devices in a system
the ADV7280A, ADV7281A, and ADV7282A devices, issues a full via the I2C port of the device. See Table 17 for the GPO truth table.
chip reset. All I2C registers are reset to their default/power-up
GPO_ENABLE, Address 0x59, Bit 4, User Sub Map
values. Some register bits do not have a reset value specified; they
keep their last written value. Those bits are marked as having a reset When GPO_ENABLE is set to 0 (default), all GPO pins are
value of X in the register tables (see Table 92 and Table 94). After tristated.
the reset sequence, the devices immediately start to acquire the When GPO_ENABLE is set to 1, all GPO pins are in a driven state.
incoming video signal. The polarity output from each GPO is controlled by GPO[3:0].
After setting the reset bit (or initiating a reset via the RESET pin), GPO[2] to GPO[0], Address 0x59, Bits[2:0], User Sub Map
the part returns to the default for its primary mode of operation. Individual control of the four GPO ports is achieved using
All I2C bits are loaded with their default values, making this bit self GPO[2:0].
clearing. Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any further I2C GPO_ENABLE must be set to 1 for the GPO pins to become active.
writes are performed. GPO[0]
The I C master controller receives a no acknowledge condition on
2
When GPO[0] is set to 0 (default), Logic 0 is output from the
the ninth clock cycle when a chip reset is implemented. GPO0 pin.
When the reset bit is set to 0 (default), operation is normal. When GPO[0] is set to 1, Logic 1 is output from the GPO0 pin.
When the reset bit is set to 1, the reset sequence starts. GPO[1]
GPO1 pin.
When GPO[1] is set to 1, Logic 1 is output from the GPO1 pin.
GPO[2]
GPO2 pin.
When GPO[2] is set to 1, Logic 1 is output from the GPO2 pin.
Table 17. GPO Registers Truth Table
GPO_ENABLE GPO[2:0] GPO2 GPO1 GPO0
0 XXX1 Z2 Z2 Z2
1 000 0 0 0
1 001 0 0 1
1 010 0 1 0
1 011 0 1 1
1 100 1 0 0
1 101 1 0 1
1 110 1 1 0
1 111 1 1 1
1
X means don’t care.
2
Z means high-Z.
GLOBAL STATUS REGISTER

Four registers provide summary information about the video STATUS 3
decoder. The IDENT register allows the user to identify the
Status 3, Address 0x13, Bits[7:0], User Sub Map
revision code of the ADV7280A, ADV7281A, and ADV7282A
devices. The other three registers (Address 0x10, Address 0x12, and Table 21. Status 3 Function
Address 0x13) contain status bits from the ADV7280A, Bit Bit Name Description
ADV7281A, and ADV7282A devices. 7 PAL_SW_LOCK Reliable sequence of swinging bursts
Depending on the setting of the FSCLE bit, the status registers are detected
based solely on horizontal timing information or on the horizontal 6 Interlaced Interlaced video detected (field sequence
found)
timing and lock status of the color subcarrier. See the FSCLE,
5 STD_FLD_LEN Field length is correct for currently selected
Address 0x51 section. video standard
IDENTIFICATION 4 FREE_RUN_ACT Flags if ADV7280A, ADV7281A, and
ADV7282A devices enter free run mode
IDENT[7:0], Address 0x11[7:0], User Sub Map
(see the Free Run Operation section)
This is the register identification of the ADV7280A, ADV7281A, 3 Reserved Reserved
and ADV7282A devices revision (see Table 18). 2 SD_OP_50Hz Flags whether 50 Hz or 60 Hz is present at
output
Table 18. IDENT[7:0] Code 1 Reserved Reserved
Address Description 0 INST_HLOCK Horizontal lock achieved
0x43 Production silicon
AUTODETECTION RESULT
STATUS 1 AD_RESULT[2:0], Address 0x10, Bits [6:4], User Sub Map
The AD_RESULT[2:0] bits report back on the findings from the
This read only register provides information about the internal autodetection block of the ADV7280A, ADV7281A, and
status of the ADV7280A, ADV7281A, and ADV7282A devices. ADV7282A devices. See the General Setup section for more
See the CIL[2:0], Address 0x51, Bits[2:0], User Sub Map section information on enabling the autodetection block and the
and the COL[2:0], Address 0x51, Bits[5:3], User Sub Map Autodetection of SD Modes section for more information on how
section for details on timing. to configure it.
Table 19. Status 1 Function Table 22. AD_RESULT[2:0] Function

Bit Bit Name Description Setting Description
7 COL_KILL Color kill active 000 NTSC M/NTSC J
6:4 AD_RESULT[2:0] Result of autodetection 001 NTSC 4.43
3 FOLLOW_PW AGC follows peak white algorithm 010 PAL M
2 FSC_LOCK fSC locked (now) 011 PAL 60
1 LOST_LOCK Lost lock (since last read) 100 PAL B/PAL G/PAL H/PAL I/PAL D
0 IN_LOCK In lock (now) 101 SECAM
110 PAL Combination N
STATUS 2 111 SECAM 525
Table 20. Status 2 Function
Bit Bit Name Description
7 Reserved Reserved
6 Reserved Reserved
5 FSC_NSTD Subcarrier frequency (fSC) is nonstandard
4 LL_NSTD Line length is nonstandard
3 MV_AGC_DET Detected Rovi AGC pulses
2 MV_PS_DET Detected Rovi pseudo sync pulses
1 MVCS_T3 Rovi color striping protection; conforms to
Type 3 if high, Type 2 if low
0 MVCS_DET Detected Rovi (previously Macrovision) color
striping
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
MACROVISION VBI DATA STANDARD SLLC

DETECTION RECOVERY AUTODETECTION CONTROL
DIGITIZED CVBS
DIGITIZED Y (Y/C) LUMA LUMA
DIGITAL LUMA LUMA LUMA
FILTER GAIN RESAMPLE 2D COMB
FINE CONTROL
CLAMP
LINE AV
SYNC LENGTH
RESAMPLE ACE DITHER I2P SD PROCESSOR
EXTRACT CONTROL CODE
PREDICTOR INSERTION OUTPUT
MEASUREMENT
DIGITIZED CVBS
DIGITIZED C (Y/C) CHROMA BLOCK (≥ I2C)
DIGITAL CHROMA CHROMA CHROMA CHROMA CHROMA
FINE DEMOD FILTER GAIN RESAMPLE 2D COMB VIDEO DATA
CLAMP CONTROL PROCESSING
BLOCK
INTERLACED TO
PROGRESSIVE
fSC CONVERTER BLOCK,
16169-008
RECOVERY
ADV7280A, ADV7280A-M
ADV7282A, AND
ADV7282A-M ONLY
Figure 8. Block Diagram of Video Processor
Figure 8 shows a block diagram of the video processor within the SD CHROMA PATH
ADV7280A, ADV7281A, and ADV7282A devices. The devices The input signal is processed by the following blocks:
can handle SD video in CVBS, Y/C, and YPrPb formats. It can
be divided into a luminance and chrominance path. If the input • Chroma digital fine clamp. This block uses a high precision
video is of a composite type (CVBS), both processing paths are fed algorithm to clamp the video signal.
with the CVBS input. The output from the video processor is fed • Chroma demodulation. This block employs a color subcarrier
into a MIPI Tx block in the ADV7280A-M, ADV7281A-M, and signal (fSC) recovery unit to regenerate the color subcarrier for
ADV7282A-M models. In the ADV7280A and ADV7282A any modulated chroma scheme. The demodulation block then
models, the output of the video processor is output from the performs an AM demodulation for PAL and NTSC, and an
devices in an ITU-R BT.656 video stream. FM demodulation for SECAM.
• Chroma filter. This block contains a chroma decimation filter
SD LUMA PATH
(CAA) with a fixed response and some shaping filters (CSH)
The analog video signal received is processed by the following that have selectable responses.
blocks: • Chroma gain control. AGC can operate on several different
• Luma digital fine clamp. This block uses a high precision modes, including gain based on the color subcarrier
algorithm to clamp the video signal. amplitude, gain based on the depth of the horizontal sync
• Luma filter. This block contains a luma decimation filter pulse on the luma channel, and fixed manual gain.
(YAA) with a fixed response and some shaping filters (YSH) • Chroma resample. The chroma data is digitally resampled to
that have selectable responses. keep it perfectly aligned with the luma data. The resampling
• Luma gain control. The AGC can operate on a variety of corrects static and dynamic line length errors of the incoming
different modes, including gain based on the depth of the video signal.
horizontal sync pulse, peak white mode, and fixed • Chroma 2D comb. The 2D, five-line, super adaptive comb
manual gain. filter provides high quality Y/C separation if the input signal is
• Luma resample. To correct for line length errors as well as CVBS.
dynamic line length changes, the data is digitally resampled. • AV code insertion. At this point, the demodulated chroma (Cr
• Luma 2D comb. The 2D comb filter provides Y/C separation. and Cb) signal is merged with the retrieved luma values. AV
• Active video (AV) code insertion. At this point, the decoded codes can be inserted (as per ITU-R BT.656).
luma (Y) signal is merged with the retrieved chroma values.
AV codes can be inserted (as per ITU-R BT.656).
ACE, I2P, AND DITHER PROCESSING BLOCKS The ADV7280A, ADV7281A, and ADV7282A devices are also
capable of automatically detecting the incoming video standard
• ACE. This block offers improved visual detail by using an
with respect to the following:
algorithm to automatically vary the contrast levels to enhance
picture detail. See the ACE section. • Color subcarrier frequency
• Dither. When enabled, this block converts the digital output • Field rate
of the ADV7280A, ADV7281A, and ADV7282A devices from • Line rate
8-bit pixel data down to 6-bit pixel data. This function makes
The ADV7280A, ADV7281A, and ADV7282A devices can
it easier for the devices to communicate with some liquid
configure to support PAL B/PAL D/ PAL I/PAL G/PAL H, PAL M,
crystal display (LCD) panels. See the Dither Function section.
PAL N, PAL Combination N, NTSC M/NTSC J, SECAM 50 Hz/
• Interlaced to progressive converter (I2P). This block is only
60 Hz, NTSC 4.43, and PAL 60 formats.
available in the ADV7280A, ADV7280A-M, ADV7282A, and
ADV7282A-M models. This block converts interlaced video GENERAL SETUP
formats (480i and 576i) into progressive video formats (480p Video Standard Selection
and 576p). The VID_SEL[3:0] bits (Address 0x02, Bits[7:4]) allow the user to
SYNC PROCESSING force the digital core into a specific video standard, which is not
necessary under normal circumstances. The VID_SEL[3:0] bits
TheADV7280A, ADV7281A, and ADV7282A devices extract
default to an autodetection mode that supports PAL, NTSC,
syncs embedded in the analog input video signal. The sync
SECAM, and other variants.
extraction is optimized to support imperfect video sources, such as
VCRs with head switches. The coded algorithm used employs a Autodetection of SD Modes
coarse detection based on a threshold crossing, followed by a more To guide the autodetect system of the ADV7280A, ADV7281A,
detailed detection using an adaptive interpolation algorithm. The and ADV7282A devices, individual enable bits are provided for
raw sync information is sent to a line length measurement and each of the supported video standards. Setting the relevant bit to 0
prediction block. The output of this then drives the digital inhibits the standard from being detected automatically. Instead,
resampling section to ensure the ADV7280A, ADV7281A, and the system chooses the closest of the remaining enabled standards.
ADV7282A devices output 720 active pixels per line. The results of the autodetection block can be read back via the
The sync processing on the ADV7280A, ADV7281A, and status registers (see the Global Status Register section for more
ADV7282A devices also include the following specialized information).
postprocessing blocks that filter and condition the raw sync VID_SEL[3:0], Address 0x02, Bits[7:4], User Sub Map
information retrieved from the digitized analog video:
Table 23. VID_SEL Function
• VS single processor. This block provides extra filtering of the
Setting Description
detected VSYNCs to improve vertical lock.
0000 Autodetect PAL B/PAL G/PAL H/PAL I/PAL D, NTSC J (no
• HS single processor. The HSYNC processor is designed to (default) pedestal), SECAM
filter incoming HSYNCs that were corrupted by noise, 0001 Autodetect PAL B/PAL G/PAL H/PAL I/PAL D, NTSC M
providing much improved performance for video signals with (pedestal), SECAM
a stable time base, but poor SNR. 0010 Autodetect PAL N (pedestal), NTSC J
(no pedestal), SECAM
VBI DATA RECOVERY 0011 Autodetect PAL N (pedestal), NTSC M (pedestal),
The ADV7280A, ADV7281A, and ADV7282A devices can SECAM
retrieve the following information from the input video vertical 0100 NTSC J
blanking interval: 0101 NTSC M
0110 PAL 60
• WSS
0111 NTSC 4.43
• CGMS
1000 PAL B/PAL G/PAL H/PAL I/PAL D
• CCAP
1001 PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with pedestal)
• Rovi protection presence 1010 PAL M (without pedestal)
• Teletext 1011 PAL M
1100 PAL Combination N
1101 PAL Combination N (with pedestal)
1110 SECAM
1111 SECAM
AD_SEC525_EN, Address 0x07, Bit 7, User Sub Map Setting AD_NTSC_EN to 1 (default) enables the detection of
Setting AD_SEC525_EN to 0 (default) disables the autodetection of standard NTSC.
a 525 line system with a SECAM style, FM-modulated color AD_PAL_EN, Address 0x07, Bit 0, User Sub Map
component. Setting AD_PAL_EN to 0 disables the detection of standard PAL.
Setting AD_SEC525_EN to 1 enables the detection of a SECAM Setting AD_PAL_EN to 1 (default) enables the detection of
style, FM modulated color component. standard PAL.
AD_SECAM_EN, Address 0x07, Bit 6, User Sub Map SFL_INV, Address 0x41, Bit 6 (ADV7280A Only), User Sub
Setting AD_SECAM_EN to 0 disables the autodetection of Map
SECAM. The subcarrier frequency lock (SFL) inversion bit controls the
Setting AD_SECAM_EN to 1 (default) enables the detection of behavior of the PAL switch bit in the SFL (genlock telegram) data
SECAM. stream. Implemented to solve compatibility issues with video
encoders, it solves two problems.
AD_N443_EN, Address 0x07, Bit 5, User Sub Map
First, the PAL switch bit is meaningful only in PAL. Some encoders
Setting AD_N443_EN to 0 disables the autodetection of NTSC
(including Analog Devices encoders) also look at the state of this
style systems with a 4.43 MHz color subcarrier.
bit in NTSC.
Setting AD_N443_EN to 1 (default) enables the detection of NTSC
Second, it overcomes interfacing issues between different
style systems with a 4.43 MHz color subcarrier.
generations of Analog Devices video encoders. Older generations
AD_P60_EN, Address 0x07, Bit 4, User Sub Map (for example, the ADV7194) used the SFL (genlock telegram) bit
Setting AD_P60_EN to 0 disables the autodetection of PAL systems directly. Newer encoders (for example, the ADV7174/ADV7179,
with a 60 Hz field rate. ADV7340/ADV7341, ADV7342/ADV7343, and ADV7344,
ADV7390/ADV7391/ADV7392/ADV7393) invert the bit prior to
Setting AD_P60_EN to 1 (default) enables the detection of PAL
using it, meaning the inversion compensated for the one-line delay
systems with a 60 Hz field rate.
of an SFL (genlock telegram) transmission.
AD_PALN_EN, Address 0x07, Bit 3, User Sub Map As a result, for newer encoders, the PAL switch bit in the SFL
Setting AD_PALN_EN to 0 disables the detection of the PAL N (genlock telegram) must be set to 0 for NTSC to work. For older
standard. video encoders, the PAL switch bit in the SFL must be set to 1 to
Setting AD_PALN_EN to 1 (default) enables the detection of the work in NTSC. If the state of the PAL switch bit is wrong, a 180°
PAL N standard. phase shift occurs.
AD_PALM_EN, Address 0x07, Bit 2, User Sub Map In a decoder/encoder back to back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
Setting AD_PALM_EN to 0 disables the autodetection of PAL M.
Setting SFL_INV to 0 (default) makes the device SFL compatible
Setting AD_PALM_EN to 1 (default) enables the detection of with the ADV7174/ADV7179, ADV7340/ADV7341, ADV7342/
PAL M. ADV7343, ADV7344, and ADV7390/ADV7391/ADV7392/
AD_NTSC_EN, Address 0x07, Bit 1, User Sub Map ADV7393 video encoders.
Setting AD_NTSC_EN to 0 disables the detection of standard Setting SFL_INV to 1 makes the devices SFL compatible with the
NTSC. older video encoders.
SELECT THE RAW LOCK SIGNAL

SRLS FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TIME_WIN 1
0
FREE_RUN 0 COUNTER INTO LOCK STATUS 1[0]
COUNTER OUT OF LOCK
1
fSC LOCK MEMORY STATUS 1[1]
16169-009
TAKE fSC LOCK INTO ACCOUNT

FSCLE
Figure 9. Lock Related Signal Path
Lock Related Controls CIL[2:0], Address 0x51, Bits[2:0], User Sub Map
Lock information is presented to the user through Bits[2:0] of the CIL[2:0] (count into lock) determines the number of consecutive
Status 1 register (see the Status 1, Address 0x10, Bits[7:0] section). lines for which the lock condition must be true before the system
Figure 9 outlines the signal flow and the controls that are available switches into the locked state and reports this via Register Status 1,
to influence the way the lock status information is generated. Bits[1:0]. The bit counts the value in lines of video.
SRLS, Address 0x51, Bit 6, User Sub Map Table 25. CIL[2:0] Function
Using the select raw lock signal (SRLS) bit, the user can choose Setting Number of Video Lines
between two sources for determining the lock status (per Bits[1:0] 000 1
in the Status 1 register). See Figure 9. 001 2
• The FREE_RUN signal evaluates the properties of the 010 5
incoming video over several fields, taking vertical 011 10
synchronization information into account. 100 (default) 100
• The TIME_WIN signal is based on a line to line evaluation of 101 500
the horizontal synchronization pulse of the incoming video. 110 1000
111 100,000
Setting SRLS to 0 (default) selects the FREE_RUN signal to
evaluate over several fields. COLOR CONTROLS
Setting SRLS to 1 selects the TIME_WIN signal to evaluate on a These registers allow the user to control picture appearance,
line to line basis. including control of active data in the event of video being lost.
FSCLE, Address 0x51, Bit 7, User Sub Map These controls are independent of any other controls. For instance,
brightness control is independent of picture clamping, although
The fSC lock enable (FSCLE) bit allows the user to choose whether
both controls affect the dc level of the signal.
the status of the color subcarrier loop is taken into account when
the overall lock status is determined and presented via Bits[1:0] in CON[7:0], Address 0x08, Bits[7:0], User Sub Map
the Status 1 register. This bit must be set to 0 when operating the This register allows the user to control contrast adjustment of the
ADV7280A, ADV7281A, and ADV7282A devices in YPrPb picture.
component mode to generate a reliable INST_HLOCK status bit.
Table 26. CON[7:0] Function
When FSCLE is set to 0 (default), the overall lock status is
dependent only on horizontal sync lock. Setting Description
0x80 (default) Gain on luma channel = 1
When FSCLE is set to 1, the overall lock status is dependent on 0x00 Gain on luma channel = 0
horizontal sync lock and fSC lock. 0xFF Gain on luma channel = 2
COL[2:0], Address 0x51, Bits[5:3], User Sub Map
COL[2:0] determines the number of consecutive lines for which SD_SAT_Cb[7:0], Address 0xE3, Bits[7:0], User Sub Map
the out of lock condition must be true before the system switches This register allows the user to control the gain of the Cb channel
into the unlocked state and reports this via Register Status 1, only, which in turn adjusts the saturation of the picture.
Bits[1:0]. It counts the value in lines of video.
Table 27. SD_SAT_Cb[7:0] Function
Table 24. COL[2:0] Function Setting Description
Setting Number of Video Lines 0x80 (default) Gain on Cb channel = 0 dB
000 1 0x00 Gain on Cb channel = −42 dB
001 2 0xFF Gain on Cb channel = +6 dB
010 5
011 10 SD_SAT_Cr[7:0], Address 0xE4, Bits[7:0], User Sub Map
100 100
This register allows the user to control the gain of the Cr channel
(default)
only, which in turn adjusts the saturation of the picture.
101 500
110 1000 Table 28. SD_SAT_Cr[7:0] Function
111 100,000 Setting Description
0x00 Gain on Cr channel = −42 dB
0x80 (default) Gain on Cr channel = 0 dB
0xFF Gain on Cr channel = +6 dB
SD_OFF_Cb[7:0], Address 0xE1, Bits[7:0], User Sub Map DEF_Y[5:0], Address 0x0C, Bits[7:2], User Sub Map
This register allows the user to select an offset for the Cb channel When the ADV7280A, ADV7281A, and ADV7282A devices lose
only and to adjust the hue of the picture. There is a functional lock on the incoming video signal or when there is no input signal,
overlap with the HUE[7:0] register (Address 0x0B, User Sub Map). the DEF_Y[5:0] register allows the user to specify a default luma
value to be output. This value is used under the following
Table 29. SD_OFF_Cb[7:0] Function conditions:
Setting Description
0x00 −312 mV offset applied to the Cb channel
• If the DEF_VAL_AUTO_EN bit is set to 1 and the
0x80 (default) 0 mV offset applied to the Cb channel ADV7280A, ADV7281A, and ADV7282A devices have lost
0xFF +312 mV offset applied to the Cb channel
lock to the input video signal, this is the intended mode of
operation (automatic mode).
SD_OFF_Cr[7:0], Address 0xE2, Bits[7:0], User Sub Map • If the DEF_VAL_EN bit is set to 1, regardless of the lock status
of the video decoder, this is a forced mode that may be useful
This register allows the user to select an offset for the Cr channel during configuration.
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register. The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
Table 30. SD_OFF_Cr[7:0] Function mode, the output is Y[7:0] = (DEF_Y[5:0], 0, 0).
Setting Description
The default value of Register 0x0C is 0x36, which equates to a value
0x00 −312 mV offset applied to the Cr channel
of 0x0D for DEF_Y[5:0]. The default output color is blue.
0x80 (default) 0 mV offset applied to the Cr channel
0xFF +312 mV offset applied to the Cr channel DEF_C[7:0], Address 0x0D, Bits[7:0], User Sub Map
The Default Value C (DEF_C[7:0]) register complements the
BRI[7:0], Address 0x0A, Bits[7:0], User Sub Map DEF_Y[5:0] value. It defines the four MSBs of Cr and Cb values to
This register controls the brightness of the video signal. It allows be output if
the user to adjust the brightness of the picture. • The DEF_VAL_AUTO_EN bit is set to high and the
ADV7280A, ADV7281A, and ADV7282A devices cannot
Table 31. BRI[7:0] Function
lock to the input video (automatic mode).
Setting Description
• The DEF_VAL_EN bit is set to high (forced output).
0x00 (default) Offset of the luma channel = 0 IRE
0x7F Offset of the luma channel = +30 IRE The DEF_C[7:0] control is composed of a red chroma control
0x80 Offset of the luma channel = −30 IRE (Cr[3:0] is contained in DEF_C[7:4]) and a blue chroma control
(Cb[3:0] is contained in DEF_C[3:0]).
HUE[7:0], Address 0x0B, Bits[7:0], User Sub Map The default value of DEF_C[7:0] is 0x7C. The default output color
This register contains the value for the color hue adjustment. It is blue.
allows the user to adjust the hue of the picture. FREE RUN OPERATION
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an Free run mode provides the user with a stable clock and predictable
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°. data if the input signal cannot be decoded, for example, if input
The hue adjustment value is fed into the AM color demodulation video is not present.
block. Therefore, it applies only to video signals that contain The ADV7280A, ADV7281A, and ADV7282A devices
chroma information in the form of an AM modulated carrier automatically enter free run mode if the input signal cannot
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM be decoded. The user can prevent this operation by setting
and does not work on component video inputs (YPrPb). DEF_VAL_AUTO_EN to 0. When the DEF_VAL_AUTO_EN bit
is set to 0, the ADV7280A, ADV7281A, and ADV7282A devices
Table 32. HUE[7:0] Function
output noise if it cannot decode the input video. It is recommended
Setting Description
that the user keep DEF_VAL_AUTO_EN set to 1.
0x00 (default) Phase of the chroma signal = 0°
0x7F Phase of the chroma signal = −90° The user can force free run mode by setting the DEF_VAL_EN bit
0x80 Phase of the chroma signal = +90° to 1. The free run feature can be a useful tool in debugging system
level issues.
The VID_SEL[3:0] bits can force the video standard output in free
run mode (see the Video Standard Selection section).
The user can also specify which data is output in free run mode DEF_VAL_EN, Address 0x0C, Bit 0, User Sub Map
with the FREE_RUN_PAT_SEL[2:0] bits. The following test The default value enable bit forces free run mode.
patterns can be set using this function:
• Single color Table 34. DEF_VAL_EN Function
• Color bars Setting Description
0 Do not force free run mode (that is, free run mode
• Luma ramp
(default) dependent on DEF_VAL_AUTO_EN)
• Boundary box 1 Force free run mode
Single Color Test Pattern
In this mode, the ADV7280A, ADV7281A, and ADV7282A FREE_RUN_PAT_SEL[2:0] Address 0x14, Bits[2:0],
devices can be set to output the default luma and chroma data User Sub Map
stored in the DEF_Y[5:0] and DEF_C[7:0] controls (see the Color The free run pattern select bit selects what data is output in free run
Controls section). mode.
Color Bars Test Pattern Table 35. FREE_RUN_PAT_SEL[2:0] Function
In this mode, the ADV7280A, ADV7281A, and ADV7282A Setting Description
devices output the 100% color bars pattern. 000 Single color set by DEF_C[7:0] and DEF_Y[5:0] controls;
Luma Ramp Test Pattern (default) see the Color Controls section
001 100% color bars
In this mode, the ADV7280A, ADV7281A, and ADV7282A
010 Luma ramp. To display properly, set the DEF_C[7:0]
devices output a series of vertical bars. Each vertical bar is register to 0x88; see the Color Controls section
progressively brighter than the vertical bar to its left. 101 Boundary box
Boundary Box Test Pattern
In this mode, the ADV7280A, ADV7281A, and ADV7282A CLAMP OPERATION
devices output a black screen with a one-pixel depth white border The input video is ac-coupled into the ADV7280A, ADV7281A,
(see Figure 10). and ADV7282A devices, which has the advantage of protecting
the devices from STB events. However, the dc value of the input
video must be restored. This process is referred to as clamping the
video. This section explains the general process of clamping on the
ADV7280A, ADV7281A, and ADV7282A devices in both single-
ended and differential modes. This section also shows the different
ways in which a user can configure clamp operation behavior.
Single-Ended CVBS Clamp Operation
16169-010
The ADV7280A, ADV7281A, and ADV7282A devices use a

Figure 10. Boundary Box Free Run Test Pattern combination of current sources and a digital processing block for
DEF_VAL_AUTO_EN, Address 0x0C, Bit 1, User Sub Map clamping, as shown in Figure 11.
The default value automatic enable bit enables the ADV7280A, The analog processing channel shown is replicated three times
ADV7281A, and ADV7282A devices to enter free run mode if the inside the integrated circuit (IC). Whereas only a single channel is
devices cannot decode the video signal that is input. needed for a single-ended CVBS signal, two independent channels
are needed for Y/C (S-VHS format) type signals, and three
Table 33. DEF_VAL_AUTO_EN Function independent channels are needed to allow component signals
Setting Description (YPrPb) to be processed.
0 The ADV7280A, ADV7281A, and ADV7282A devices The clamping can be divided into two sections.
output noise if the devices lose lock with the inputted
video signal. • Clamping before the ADC (analog domain): current sources
1 The ADV7280A, ADV7281A, and ADV7282A devices and voltage sources
(default) enter free run mode if the devices lose lock with the • Clamping after the ADC (digital domain): digital processing
inputted video signal. block
The analog clamping circuit ensures the video signal stays within Differential CVBS Clamping Operation
the valid 1.0 V ADC input window so the analog-to-digital This section applies to the ADV7281A-M, ADV7282A, and
conversion can take place. The current sources in the AFE correct ADV7282A-M models only.
the dc level of the ac-coupled input video signal before it is fed into
The differential clamping operation works in a similar manner to
the ADC. The digitized data from the ADC is then fed into the
the single-ended clamping operation (see the Single-Ended CVBS
video processor. The digital fine clamp block within the video
Clamp Operation section). In differential mode, a coarse clamp
processor corrects for any remaining variation in the dc level.
pulls the positive and negative video input to a common-mode
The video processor also sends clamp control signals to the current voltage level (VCML) (see Figure 12). The feedback loop between the
sources. This feedback loop fine-tunes the current clamp operation current clamps and the video processor fine-tunes this coarse dc
and compensates for any noise on the input video signal. This offset and makes the clamping robust to noise on the video input.
feedback loop maintains the dc level of the video signal during The current clamps are controlled within a feedback loop between
normal operation. the AFE and the video processor; the coarse clamps are not.
ADV7280A/ADV7281A/ADV7282A
ANALOG FRONT END (AFE) DIGITAL CORE
EXTERNAL AC CLAMP CONTROL
COUPLING
CAPACITOR
DATA PRE- VIDEO PROCESSOR
ADC WITH DIGITAL
PROCESSOR
CURRENT FINE CLAMP
SINGLE-ENDED SOURCE
ANALOG CLAMPS
16169-011
VIDEO INPUT
Figure 11. Single-Ended Clamping Overview

ADV7281A-M/ADV7282A/ADV7282A-M
ANALOG FRONT END (AFE) DIGITAL CORE
EXTERNAL AC
COARSE CLAMP CONTROL
COUPLING
CAPACITOR CLAMP
VIDEO PROCESSOR
ADC DATA PRE-
PROCESSOR WITH DIGITAL
CURRENT FINE CLAMP
POSITIVE
DIFFERENTIAL ANALOG SOURCE
VIDEO INPUT VCML CLAMPS
NEGATIVE
DIFFERENTIAL ANALOG CURRENT
VIDEO INPUT SOURCE
CLAMPS
EXTERNAL AC COARSE
COUPLING CLAMP CONTROL
16169-012
CLAMP
CAPACITOR
Figure 12. Differential Clamping Overview
Clamp Operation Controls • The ITU-R BT.601 standard recommends a sampling
The following sections describe the I2C signals that can influence frequency of 13.5 MHz. The luma antialias filter decimates
the behavior of the clamping block. the oversampled video using a high quality linear phase,
low-pass filter that preserves the luma signal while, at the
CCLEN, Address 0x14, Bit 4, User Sub Map
same time, attenuating out of band components. The luma
The current clamp enable bit allows the user to switch off all the antialias filter (YAA) has a fixed response.
current sources in the AFE simultaneously. Disabling the current • Luma shaping filters (YSH). The shaping filter block is a
source can be useful if the incoming analog video signal is clamped programmable low-pass filter with a wide variety of responses.
externally. It can reduce selectively the luma video signal bandwidth
When CCLEN is set to 0, the current sources are switched off. (needed prior to scaling, for example). For some video sources
that contain high frequency noise, reducing the bandwidth of
When CCLEN is set to 1 (default), the current sources are enabled.
the luma signal improves visual picture quality. If the video is
DCT[1:0], Address 0x15, Bits[6:5], User Sub Map compressed subsequent to the ADV7280A, ADV7281A, and
The clamp timing bits determines the time constant of the digital ADV7282A, low-pass filtering can improve the effectiveness
fine clamp circuitry. Note that the digital fine clamp reacts quickly of the compression.
because it immediately corrects any residual dc level error for the The ADV7280A, ADV7281A, and ADV7282A devices have
active line. The time constant from the digital fine clamp must be two responses for the shaping filter: one that is used for good
much quicker than the one from the analog blocks. quality composite, component, and SVHS type sources, and a
second for nonstandard CVBS signals.
By default, the time constant of the digital fine clamp is adjusted
The YSH filter responses also include a set of notches for PAL
dynamically to suit the currently connected input signal.
and NTSC. However, using the comb filters for Y/C separation
Table 36. DCT[1:0] Function is recommended.
Setting Description • Digital resampling filter. This block allows dynamic
00 (default) Slow (time constant (TC) = 1 sec) resampling of the video signal to alter parameters such as the
01 Medium (TC = 0.5 sec) time base of a line of video. Fundamentally, the resampler is a
10 Fast (TC = 0.1 sec) set of low-pass filters. The actual response is chosen by the
11 Determined by ADV7280A, ADV7281A, and system with no requirement for user intervention.
ADV7282A devices, depending on the input
Figure 14 through Figure 17 show the overall response of all filters
video parameters
together. Unless otherwise noted, the filters are set into a typical
wideband mode.
DCFE, Address 0x15, Bit 4, User Sub Map
Y Shaping Filter
This bit allows users to freeze the digital clamp loop at any time
(self clamping). Users can disable the current sources for analog For input signals in CVBS format, the luma shaping filters are
clamping via the appropriate register bits, wait until the digital essential in removing the chroma component from a composite
clamp loop settles, and then freeze it via the DCFE bit. signal. Y/C separation must aim for the best possible crosstalk
reduction while retaining as much bandwidth (especially on the
When DCFE is set to 0 (default), the digital clamp is operational.
luma component) as possible. High quality Y/C separation can be
When DCFE is set to 1, the digital clamp loop is frozen. achieved by using the internal comb filters of the ADV7280A,
LUMA FILTER ADV7281A, and ADV7282A devices. Comb filtering, however,
relies on the frequency relationship of the luma component
Data from the digital fine clamp block is processed by the three sets
(multiples of the video line rate) and the color subcarrier frequency.
of filters that follow. The data format at this point is CVBS for a
For good quality CVBS signals, this relationship is known; the
CVBS input or luma only for Y/C and YPrPb input formats. The
comb filter algorithms can separate luma and chroma with high
following describes the filters:
accuracy.
• Luma antialias filter (YAA). The ADV7280A, ADV7281A, In the case of nonstandard video signals, the frequency relationship
and ADV7282A devices receive video based on an crystal can be disturbed, and the comb filters may not be able to remove all
(XTAL) frequency of 28.6363 MHz. In the case of 4× crosstalk artifacts without the assistance of the shaping filter block.
oversampled video, the ADC samples at 57.27 MHz, and
the first decimation is performed inside the data An automatic mode is provided that allows the ADV7280A,
preprocessor (DPP) filters. This decimation provides video ADV7281A, and ADV7282A devices to evaluate the quality of the
data at the correct rate to the digital core. incoming video signal and select the filter responses in accordance
with the signal quality and video standard. The YSFM[4:0],
WYSFMOVR, and WYSFM[4:0] bits allow the user to manually
override the automatic decisions in part or in full.
The luma shaping filter has the following control bits: Table 37. YSFM[4:0] Function
• YSFM[4:0] allows the user to manually select a shaping filter Setting Description
mode (applied to all video signals) or to enable an automatic 00000 Automatic selection including a wide notch response
(PAL/NTSC/SECAM)
selection (depending on video quality and video standard).
00001 Automatic selection including a narrow notch
• WYSFMOVR allows the user to manually override the (default) response (PAL/NTSC/SECAM)
WYSFM[4:0] decision. 00010 SVHS 1
• WYSFM[4:0] allows the user to select a different shaping filter 00011 SVHS 2
mode for good quality composite (CVBS), component 00100 SVHS 3
(YPrPb), and SVHS (Y/C) input signals. 00101 SVHS 4
In automatic mode, the system preserves the maximum possible 00110 SVHS 5
bandwidth for stable CVBS sources (because they can be combed) 00111 SVHS 6
as well as for luma components of YPrPb and Y/C sources (because 01000 SVHS 7
they do not need to be combed). For less stable CVBS sources (for 01001 SVHS 8
example, VCRs), the system selects from a set of proprietary 01010 SVHS 9
shaping filter responses that complements comb filter operation to 01011 SVHS 10
reduce visual artifacts. 01100 SVHS 11
01101 SVHS 12
The decisions of the control logic are shown in Figure 13.
01110 SVHS 13
YSFM[4:0], Address 0x17, Bits[4:0], User Sub Map 01111 SVHS 14
The Y shaping filter mode bits allow the user to select from a wide 10000 SVHS 15
range of low-pass and notch filters. When switched in automatic 10001 SVHS 16
mode, the filter selection is based on other register selections, such 10010 SVHS 17
as detected video standard, as well as properties extracted from the 10011 SVHS 18 (CCIR 601) (default)
incoming video itself, such as quality and time base stability. The 10100 PAL NN1
automatic selection always selects the widest possible bandwidth 10101 PAL NN2
for the video input encountered (see Table 37). 10110 PAL NN3
10111 PAL WN1
The Y shaping filter mode operates as follows:
11000 PAL WN2
• If the YSFM[4:0] settings specify a filter (that is, YSFM[4:0] is 11001 NTSC NN1
set to values other than 00000, 00001, or 11111 (reserved)), 11010 NTSC NN2
the chosen filter is applied to all video, regardless of its quality. 11011 NTSC NN3
• In automatic selection mode, use the notch filters for less 11100 NTSC WN1
stable video sources. For all other video signals, use 11101 NTSC WN2
wideband filters. 11110 NTSC WN3
11111 Reserved
SET YSFM
YES YSFM IN AUTO MODE? NO

00000 OR 00001
VIDEO
QUALITY
BAD GOOD
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
AUTO SELECT LUMA
SHAPING FILTER TO WYSFMOVR
COMPLEMENT COMB
1 0
SELECT WIDEBAND
16169-013
SELECT AUTOMATIC
FILTER AS PER WIDEBAND FILTER
WYSFM[4:0]
Figure 13. YSFM[4:0] and WYSFM[4:0] Control Flowchart
WYSFMOVR, Address 0x18, Bit 7, User Sub Map 01111 SVHS 14

Setting the Wideband Y Shaping Filter Override (WYSFMOVR) 10000 SVHS 15
bit enables the use of the WYSFM[4:0] settings for good quality 10001 SVHS 16
video signals. For more information on luma shaping filters, see the 10010 SVHS 17
Y Shaping Filter section and the flowchart shown in Figure 13. 10011 (default) SVHS 18 (CCIR 601) (default)
10100 to 11111 Reserved, do not use
When WYSFMOVR is set to 0, the shaping filter for good quality
video signals is selected automatically.
Figure 14 shows the S-VHS 1 (narrowest) to S-VHS 18 (widest)
When WYSFMOVR is set to 1 (default), it enables manual override shaping filter settings. Figure 15 shows the CCIR mode shaping
via WYSFM[4:0]. filter response. Figure 16 shows the PAL notch filter responses. The
WYSFM[4:0], Wideband Y Shaping Filter Mode, NTSC notch filter responses are shown in Figure 17.
Address 0x18[4:0]
0
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, such as CVBS with stable time –10
base, luma component of YPrPb, and luma component of Y/C. The –20
AMPLITUDE (dB)
WYSFM[4:0] bits are active only if the WYSFMOVR bit is set to 1.

See the general discussion of the shaping filter settings in the Y –30
Shaping Filter section.

–40
Table 38. WYSFM[4:0] Function

–50
WYSFM[4:0] Description
00000 Reserved, do not use –60
00001 Reserved, do not use

–70
16169-014
00010 SVHS 1 0 2 4 6 8 10 12
00011 SVHS 2 FREQUENCY (MHz)
00100 SVHS 3 Figure 14. Combined Y Antialias, S-VHS Low-Pass Filter,

and Y Resample Responses
00101 SVHS 4
00110 SVHS 5
00111 SVHS 6
01000 SVHS 7
01001 SVHS 8
01010 SVHS 9
01011 SVHS 10
01100 SVHS 11
01101 SVHS 12
01110 SVHS 13
0 and the chroma/YPrPb by a factor of 2. A decimating filter
(CAA) preserves the active video band and removes any out of
–20 band components. The CAA filter has a fixed response.
• Chroma shaping (CSH) filters. The CSH filter block can be
programmed to perform a variety of low-pass filter responses.
AMPLITUDE (dB)
–40
The CSH filter block can selectively reduce the bandwidth of

–60 the chroma signal for scaling or compression.
• Digital resampling filter. This block allows dynamic
–80
resampling of the video signal to alter parameters such as the
time base of a line of video. Fundamentally, the resampler is a
–100
set of low-pass filters. The actual response is chosen by the
system without user intervention.
–120
16169-015
0 2 4 6 8 10 12
FREQUENCY (MHz)
Figure 18 shows the overall response of all filters together.
Figure 15. Combined Y Antialias, CCIR Mode Shaping Filter, Y Resample 0
Responses
–10
0
ATTENUATION (dB)
–20
–10
–20 –30
AMPLITUDE (dB)
–30
–40
–40
–50
–50
–60
16169-018
–60 0 1 2 3 4 5 6
FREQUENCY (MHz)
–70
Figure 18. Chroma Shaping Filter Responses; Combined C Antialias, C Shaping
16169-016
0 2 4 6 8 10 12
FREQUENCY (MHz)
Filter, and C Resampler
Figure 16. Combined Y Antialias, PAL Notch Filters, and Y Resample CSFM[2:0], Address 0x17, Bits[7:5], User Sub Map
Responses
The C shaping filter mode bits allow the user to select from a range
0 of low-pass filters for the chrominance signal. When switched in
–10
automatic mode, the widest filter is selected based on the video
standard/format and user choice (see the 000 and 001 settings in
–20 Table 39).
AMPLITUDE (dB)
–30 Table 39. CSFM[2:0] Function

Setting Description
–40
000 (default) Autoselection 1.5 MHz bandwidth
–50 001 Autoselection 2.17 MHz bandwidth
010 SH1
–60
011 SH2
–70 100 SH3
16169-017
0 2 4 6 8 10 12
FREQUENCY (MHz)
101 SH4
Figure 17. Combined Y Antialias Filter, NTSC Notch Filter, and Y Resample 110 SH5
111 Wideband mode
CHROMA FILTER
Data from the digital fine clamp block is processed by the three sets Figure 18 shows the responses of SH1 (narrowest) to SH5 (widest)
of filters that follow. The data format at this point is CVBS for in addition to the wideband mode.
CVBS (or differential CVBS) inputs, chroma only for Y/C, or U/V
interleaved for YPrPb input formats.
• Chroma antialias (CAA) filter. The ADV7280A, ADV7281A,
and ADV7282A devices oversample the CVBS by a factor of 4
GAIN OPERATION The minimum supported amplitude of the input video is
The gain control within the ADV7280A, ADV7281A, and determined by the ability of the ADV7280A, ADV7281A, and
ADV7282A devices is implemented on a purely digital basis. The ADV7282A devices to retrieve horizontal and vertical timing and
input ADC supports a 10-bit range mapped into a 1.0 V analog to lock to the color burst, if present.
voltage range. Gain correction takes place after the digitization in There are separate gain control units for luma and chroma data.
the form of a digital multiplier. Both can operate independently of each other. The chroma unit,
Advantages of this architecture over the commonly used however, can also take its gain value from the luma path.
programmable gain amplifier (PGA) before the ADC include the The possible AGC modes are shown in Table 40.
fact that the gain is completely independent of supply, temperature,
and process variations. Table 40. AGC Modes
Input
As shown in Figure 21, the ADV7280A, ADV7281A, and Video
ADV7282A devices can decode a video signal as long as it fits into Type Luma Gain Chroma Gain
the ADC window. The primary components that determine Any Manual gain luma Manual gain chroma
whether the video signal fits inside the ADC window are the CVBS Dependent on Dependent on color burst
amplitude of the input signal and the dc level it resides on. The dc horizontal sync amplitude taken from luma
level is set by the clamping circuitry (see the Clamp Operation depth path
section). Peak white Dependent on color burst
amplitude taken from luma
If the amplitude of the analog video signal is too high, clipping may path
occur, resulting in visual artifacts. The analog input range of the Y/C Dependent on Dependent on color burst
ADC, together with the clamp level, determines the maximum horizontal sync amplitude taken from luma
supported amplitude of the video signal. depth path
Peak white Dependent on color burst
Figure 19 and Figure 20 show the typical voltage divider networks
amplitude
required to keep the input video signal within the allowed range of
YPrPb Dependent on Taken from luma path
the ADC, 0 V to 1 V. Place the circuit in Figure 19 before all the horizontal sync
single-ended analog inputs to the ADV7280A, ADV7281A, and depth
ADV7282A devices, and place the circuit in Figure 20 before all the
differential inputs to the devices. It is possible to freeze the automatic gain control loops, causing the
Differential inputs can only be applied directly to the loops to stop updating and the AGC determined gain at the time of
ADV7281A-M, ADV7282A and ADV7282A-M models. the freeze to stay active until the loop is either unfrozen or the gain
ANALOG VIDEO mode of operation is changed.
INPUT 100nF
AINx The currently active gain from any of the modes can be read back.
24Ω
Refer to the description of the dual-function manual gain bits,
16169-019
51Ω
LG[11:8] luma gain and CG[11:0] chroma gain, in the Luma Gain
Figure 19. Single-Ended Input Voltage Divider Network section and the Chroma Gain section, respectively.
ANALOG_INPUT
CVBS_1P 0.1µF
1.3kΩ
AINx
430Ω
75Ω
ANALOG_INPUT 430Ω
CVBS_1N 0.1µF
1.3kΩ
16169-020
AINx
Figure 20. Differential Input Voltage Divider Network
ANALOG VOLTAGE RANGE SUPPORTED BY ADC
(1V RANGE)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
DATA PRE-
ADC PROCESSOR
(DPP)
GAIN
CONTROL
16169-021
MINIMUM CLAMP
VOLTAGE LEVEL
Figure 21. Gain Control Overview
Luma Gain PW_UPD, Address 0x2B, Bit 0, User Sub Map

LAGC[2:0], Address 0x2C, Bits[6:4], User Sub Map
The peak white and average video algorithms determine the gain
The luma automatic gain control mode bits select the operating based on measurements taken from the active video. The
mode for the gain control in the luma path. PW_UPD bit determines the rate of gain change. LAGC[2:0] must
The peak white algorithm detects if the input video amplitude be set to the appropriate mode to enable the peak white or average
exceeds the ADC input range of the ADV7280A, ADV7281A, and video mode in the first place. For more information, see the
ADV7282A devices. If the amplitude exceeds the input range, then LAGC[2:0], Address 0x2C, Bits[6:4] section.
the devices reduce the internal luma gain to prevent the signal from Setting PW_UPD to 0 updates the gain once per video line.
becoming saturated. Setting PW_UPD to 1 (default) updates the gain once per field.
Table 41. LAGC[2:0] Function LMG[11:8]/LG[11:8], Address 0x2F, Bits[3:0], and
Setting Description LMG[7:0]/LG[7:0], Address 0x30, Bits[7:0], User Sub Map
000 Manual fixed gain (use LMG[11:8])
Luma gain (Bits[11:0]) is a dual-function register. If all of these
001 AGC, peak white algorithm off (blank level to sync
tip) bits are written to, a desired manual luma gain can be programmed.
010 AGC, peak white algorithm on (blank level to sync This gain becomes active if the LAGC[2:0] mode is switched to
(default) tip) manual fixed gain. Equation 1 shows how to calculate a
011 Reserved desired gain.
100 Reserved If read back, this register returns the current gain value. Depending
101 Reserved on the setting in the LAGC[2:0] bits, the value is one of the
110 Reserved following:
111 Freeze gain
• Luma manual gain value (LAGC[2:0] set to luma manual gain
mode)
LAGT[1:0], Address 0x2F, Bits[7:6], User Sub Map
• Luma automatic gain value (LAGC[2:0] set to either of the
The luma automatic gain timing bits allows the user to influence automatic modes)
the tracking speed of the luminance automatic gain control. This
register has an effect only if the LAGC[2:0] register is set to 001 or Table 43. LG/LMG Function
010 (automatic gain control modes). Setting1 Read/Write Description
If peak white AGC is enabled and active (see the Status 1, LMG[11:0] = X Write Manual gain for luma path
Address 0x10, Bits[7:0] section), the actual gain update speed is LG[11:0] = X Read Actual used gain
dictated by the peak white AGC loop and, as a result, the 1
LAGT[1:0] settings have no effect. As soon as the device leaves
peak white AGC, LAGT[1:0] becomes relevant again. LMG[11:8 ]Decimal
Luma Gain ≅ (1)
The update speed for the peak white algorithm can be customized Luma Calibration Factor
by the use of internal parameters. where:
LMG[11:8] is a decimal value between 1024 and 4095.
Table 42. LAGT[1:0] Function
Decimal informs the user to use the decimal values instead of the
Setting Description
hexadecimal or binary values.
00 Slow (time constant = 2 sec)
01 Medium (time constant = 1 sec)
10 Fast (time constant = 0.2 sec)
11 (default) Adaptive
Calculation of the Luma Calibration Factor • The chroma automatic gain value (CAGC[1:0] set to either of
1. Using a video source, set the content to a gray field and apply a the automatic modes).
standard CVBS signal to the CVBS input of the ADV7280A, Table 46. CMG/CG Function
ADV7281A, and ADV7282A devices.
Setting Read/Write Description
2. Using an oscilloscope, measure the signal at the CVBS input to
CMG[11:0] Write Manual gain for chroma path
ensure that its sync depth, color burst, and luma are at the
CG[11:0] Read Currently active gain
standard levels.
3. Connect the output of the ADV7280A, ADV7281A, and CMG[11:0 ]Decimal
ADV7282A devices to a backend system that has unity gain Chroma Gain ≅ (2)
Chroma Calibration Factor
and monitor the output voltage.
4. Measure the luma level correctly from the black level. Turn off where Chroma Calibration Factor is a decimal value between 0
the luma AGC and manually change the value of the luma and 4095.
manual gain control register, LMG[11:8], until the output Take the following steps to calculate the chroma calibration factor:
luma level matches the input measured in Step 2.
1. Apply a CVBS signal with the color bars/Society of Motion
This value, in decimal, is the luma calibration factor. Picture and Television Engineers (SMPTE) bars test pattern
Chroma Gain content directly to measurement equipment, for example, an
oscilloscope.
CAGC[1:0], Address 0x2C, Bits[1:0], User Sub Map
2. Ensure correct termination of 75 Ω on the measurement
The two bits of the color automatic gain control mode select the equipment. Measure chroma output levels.
basic mode of operation for the automatic gain control in the 3. Reconnect the source to the CVBS input of the ADV7280A,
chroma path. ADV7281A, and ADV7282A devices that has a back-end gain
of 1. Repeat the measurement of chroma levels.
Table 44. CAGC[1:0] Function
4. Turn off the chroma AGC, and manually change the chroma
Setting Description
gain control register, CMG[11:0], until the chroma level
00 Manual fixed gain (use CMG[11:0])
matches that measured directly from the source.
01 Use luma gain for chroma
10 (default) Automatic gain (based on color burst) This value, in decimal, is the chroma calibration factor.
11 Freeze chroma gain CKE, Address 0x2B, Bit 6, User Sub Map
The color kill enable bit allows the optional color kill function to be
CAGT[1:0], Address 0x2D, Bits[7:6], User Sub Map
switched on or off.
The chroma automatic gain timing bits allows the user to influence
For quadrature amplitude modulation (QAM)-based video
the tracking speed of the chroma automatic gain control. These bits
standards (PAL and NTSC), as well as frequency modulation (FM)-
have an effect only if the CAGC[1:0] bits are set to 10 (automatic
based systems (SECAM), the threshold for the color kill decision is
gain).
selectable via the CKILLTHR[2:0] bits.
Table 45. CAGT[1:0] Function If color kill is enabled and the color carrier of the incoming video
CAGT[1:0] Description signal is less than the threshold for 128 consecutive video lines,
00 Slow (time constant = 2 sec) color processing is switched off (black and white output). To switch
01 Medium (time constant = 1 sec) the color processing back on, another 128 consecutive lines with a
10 Reserved color burst greater than the threshold are required.
11 (default) Adaptive
The color kill option works only for input signals with a modulated
chroma part. For component input (YPrPb), there is no color kill.
CMG[11:8]/CG[11:8], Address 0x2D, Bits[3:0], and
CMG[7:0]/CG[7:0] Address 0x2E, Bits[7:0], User Sub Map Set CKE to 0 to disable color kill.
Chroma gain (Bits[11:0]) is a dual-function register. If written to, a Set CKE to 1 (default) to enable color kill.
desired manual chroma gain can be programmed. This gain CKILLTHR[2:0], Address 0x3D, Bits[6:4], User Sub Map
becomes active if the CAGC[1:0] function is switched to manual
The CKILLTHR[2:0] bits allow the user to select a threshold for the
fixed gain. See Equation 2 for calculating a desired gain.
color kill function. The threshold applies only to QAM-based
If read back, this register returns the current gain value. Depending (NTSC and PAL) or FM-based (SECAM) video standards.
on the setting in the CAGC[1:0] bits, this is either
To enable the color kill function, the CKE bit must be set. For the
• The chroma manual gain value (CAGC[1:0] set to chroma 000, 001, 010, and 011 settings, chroma demodulation inside the
manual gain mode). ADV7280A, ADV7281A, and ADV7282A devices may not work
satisfactorily for unstable CVBS sources.
Table 47. CKILLTHR[2:0] Function For the alpha blender to be active, enable the CTI block via the
Description CTI_EN bit.
Setting NTSC, PAL SECAM Set CTI_AB_EN to 0 to disable the CTI alpha blender.
000 Kill at <0.5% No color kill
Set CTI_AB_EN to 1 (default) to enable the CTI alpha blend
001 Kill at <1.5% Kill at <5%
mixing function.
010 (default) Kill at <2.5% Kill at <7%
011 Kill at <4% Kill at <8% CTI_AB[1:0], Address 0x4D, Bits[3:2], User Sub Map
100 Kill at <8.5% Kill at <9.5% The CTI_AB[1:0] controls the behavior of alpha blend circuitry
101 Kill at <16% Kill at <15% that mixes the sharpened chroma signal with the original one and
110 Kill at <32% Kill at <32% controls the visual impact of CTI on the output data.
111 Reserved Reserved
For CTI_AB[1:0] to become active, the CTI block must be enabled
via the CTI_EN bit, and the alpha blender must be switched on via
CTI CTI_AB_EN.
The signal bandwidth allocated for chroma is typically much
Sharp blending maximizes the effect of CTI on the picture;
smaller than for luminance.
however, it may also increase the visual impact of small amplitude,
The uneven bandwidth, however, can lead to visual artifacts in high frequency chroma noise.
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see Table 48. CTI_AB[1:0] Function
Figure 22). Due to the higher bandwidth, the signal transition of Setting Description
the luma component is usually much sharper than the chroma 00 Sharpest mixing between sharpened and original
component signal transition. The color edge is not sharp, and in the chroma signal
worst case, it can be blurred over several pixels. 01 Sharp mixing between sharpened and original
chroma signal
10 Smooth mixing between sharpened and original
chroma signal
LUMA SIGNAL WITH A
LUMA SIGNAL
TRANSITION, ACCOMPANIED
BY A CHROMA TRANSITION
11 Smoothest mixing between sharpened and original
(default) chroma signal
CTI_C_TH[7:0], Address 0x4E[7:0], User Sub Map

DEMODULATED
ORIGINAL, SLOW CHROMA
TRANSITION PRIOR TO CTI The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying
CHROMA SIGNAL
the amplitude step size in a chroma transition, steepened by the
16169-022
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI CTI block. Programming a small value into this register causes
Figure 22. CTI Luma and Chroma Transition even smaller edges to be steepened by the CTI block. Making
The chroma transient improvement block examines the input video CTI_C_TH[7:0] a large value causes the block to improve large
data. It detects transitions of chroma and can be programmed to transitions only.
create steeper chroma edges in an attempt to artificially restore lost The default value for CTI_C_TH[7:0] is 00001000.
color bandwidth. The CTI block, however, operates only on edges
DIGITAL NOISE REDUCTION (DNR) AND LUMA
above a certain threshold to ensure noise is not emphasized. Ensure
PEAKING FILTER
that edge ringing and undesirable saturation or hue distortion are
avoided. Digital noise reduction (DNR) is based on the assumption that
high frequency signals with low amplitude are noise and their
Chroma transient improvements are needed primarily for signals
removal improves picture quality. The two DNR blocks in the
that have severe chroma bandwidth limitations. For those types of
ADV7280A, ADV7281A, and ADV7282A devices are the DNR1
signals, it is strongly recommended to enable the CTI block via
block before the luma peaking filter and the DNR2 block after the
CTI_EN.
luma peaking filter, as shown in Figure 23.
CTI_EN, Address 0x4D, Bit 0, User Sub Map
Set CTI_EN to 0 to disable the CTI block.
Set CTI_EN to 1 (default) to enable the CTI block.
CTI_AB_EN, Address 0x4D, Bit 1, User Sub Map
The CTI_AB_EN bit enables an alpha blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
15
10
FILTER RESPONSE (dB)

LUMA
LUMA
LUMA
5
SIGNAL DNR1 PEAKING DNR2 OUTPUT
FILTER
0
16169-023
–5
Figure 23. DNR and Peaking Block Diagram –10
DNR and Peaking –15
DNR_EN, Address 0x4D, Bit 5, User Sub Map

–20
16169-024
The DNR_EN bit enables or bypasses the DNRx blocks. 0 1 2 3 4 5 6 7
FREQUENCY (MHz)
Table 49. DNR_EN Function Figure 24. Peaking Filter Responses

Setting Description DNR_TH2[7:0], Address 0xFC, Bits[7:0], User Sub Map
0 Bypasses the DNRx blocks (disable)
The DNR2 block is positioned after the luma peaking block and
1 (default) Enables the DNRx blocks
affects the gained luma signal. It operates similarly to the DNR1
block; however, there is an independent threshold control,
DNR_TH[7:0], Address 0x50, Bits[7:0], User Sub Map
DNR_TH2[7:0], for this block. This unsigned, 8-bit value
The DNR1 block is positioned before the luma peaking block. The determines the maximum edge that is interpreted as noise and
DNR_TH[7:0] value is an unsigned, 8-bit number that determines blanked from the luma data. Programming a large value into
the maximum edge that is interpreted as noise and, therefore, DNR_TH2[7:0] causes the DNR2 block to interpret even large
blanked from the luma data. Programming a large value into transients as noise and remove them. As a result, the effect on the
DNR_TH[7:0] causes the DNRx blocks to interpret even large video data is more visible. Programming a small value causes only
transients as noise and remove them. As a result, the effect on the small transients to be seen as noise and removed.
video data is more visible. Programming a small value causes only
small transients to be seen as noise and to be removed. Table 52. DNR_TH2[7:0] Function
Setting Description
Table 50. DNR_TH[7:0] Function 0x04 Specifies the maximum luma edge that is interpreted
Setting Description (default) as noise and therefore blanked
0x08 Threshold for maximum luma edges to be
(default) interpreted as noise COMB FILTERS
The comb filters of the ADV7280A, ADV7281A, and ADV7282A
PEAKING_GAIN[7:0], Address 0xFB, Bits[7:0], User
devices can automatically handle video of all types, standards, and
Sub Map
levels of quality. The NTSC and PAL comb filter configuration
This filter can be manually enabled. The user can select to boost or registers allow the user to customize the comb filter operation
to attenuate the midregion of the Y spectrum around 3 MHz. The depending on which video standard is detected (by autodetection)
peaking filter can visually improve the picture by showing more or selected (by manual programming).
definition on the picture details that contain frequency components
NTSC Comb Filter Settings
around 3 MHz. The default value on this register passes through
the luma data unaltered. A lower value attenuates the signal, and a These settings are used for NTSC M/NTSC J CVBS inputs.
higher value gains the luma signal. Figure 24 shows the responses NSFSEL[1:0], Address 0x19, Bits[3:2], User Sub Map
of the peaking filter.
The NSFSEL[1:0] control selects how much of the overall signal
Table 51. PEAKING_GAIN[7:0] Function bandwidth is fed to the combs. A narrow split filter selection results
Setting Description in improved performance on diagonal lines but more dot crawl in
0x40 Increases/decreases the gain for high frequency the final output image. The opposite is true for selecting a wide
(default) portions of the video signal bandwidth split filter.
Table 53. NSFSEL[1:0] Function YCMN[2:0], Address 0x38, Bits[2:0], User Sub Map
Setting Description NTSC luma comb mode bits.
00 (default) Narrow
01 Medium Table 56. YCMN Function
10 Medium YCMN[2:0] Description Configuration
11 Wide 000 Adaptive comb mode Three-line adaptive, (three
(default) taps) luma comb
CTAPSN[1:0], Address 0x38, Bits[7:6], User Sub Map 100 Disable luma comb Use low-pass/notch filter;
see the Y Shaping Filter
CTAPSN[1:0] are the NTSC chroma comb taps bits that select how section
many lines the NTSC chroma comb uses in its operation. 101 Fixed luma comb (top Fixed luma comb two-line
lines of line memory) (two taps)
Table 54. CTAPSN[1:0] Function
110 Fixed luma comb (all Fixed luma comb three-line
CTAPSN[1:0] Description lines of line memory) (three taps)
00 Do not use 111 Fixed luma comb Fixed luma comb two-line
01 NTSC chroma comb adapts three lines to (bottom lines of line (two taps)
two lines memory)
10 (default) NTSC chroma comb adapts five lines to
three lines PAL Comb Filter Settings
11 NTSC chroma comb adapts five lines to four lines
These settings are used for PAL B/PAL G/PAL H/PAL I/PAL D,
PAL M, PAL Combinational N, PAL 60, and NTSC 4.43
CCMN[2:0], Address 0x38, Bits[5:3], User Sub Map CVBS inputs.
CCMN[2:0] are the NTSC chroma comb mode bits that select how PSFSEL[1:0], Address 0x19, Bits[1:0], User Sub Map
the NTSC chroma comb is configured. The PSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
Table 55. CCMN[2:0] Function
eliminates dot crawl but shows imperfections on diagonal lines.
Setting Description Configuration
The opposite is true for selecting a narrow bandwidth split filter.
000 Adaptive comb Three-line adaptive chroma comb
(default) mode for CTAPSN = 01, four-line adaptive Table 57. PSFSEL[1:0] Function
chroma comb for CTAPSN = 10, or
five-line adaptive chroma comb for Setting Description
CTAPSN = 11 00 Narrow
01 (default) Medium
100 Disable chroma 10 Wide
comb 11 Widest
101 Fixed chroma Fixed two-line chroma comb for
comb (top lines CTAPSN = 01, fixed three-line CTAPSP[1:0], Address 0x39, Bits[7:6], User Sub Map
of line memory) chroma comb for CTAPSN = 10, or
fixed four-line chroma comb for CTAPSP[1:0] are the PAL chroma comb taps bits that select how
CTAPSN = 11 many lines the PAL chroma comb uses in its operation.
Table 58. CTAPSP[1:0] Function

110 Fixed chroma Fixed three-line chroma comb for
comb (all lines of CTAPSN = 01, fixed four-line Setting Description
line memory) chroma comb for CTAPSN = 10, or 00 Do not use
fixed five-line chroma comb for 01 PAL chroma comb adapts five lines (three taps) to three
CTAPSN = 11 lines (two taps); cancels cross luma only
10 PAL chroma comb adapts five lines (five taps) to three
111 Fixed chroma Fixed two-line chroma comb for lines (three taps); cancels cross luma and hue error less
comb (bottom CTAPSN = 01, fixed three-line well
lines of line chroma comb for CTAPSN = 10, or 11 PAL chroma comb adapts five lines (five taps) to four
memory) fixed four-line chroma comb for (default) lines (four taps); cancels cross luma and hue error well
CTAPSN = 11
CCMP[2:0], Address 0x39, Bits[5:3], User Sub Map intermediate frequency (IF) filter compensation for NTSC and
CCMP[2:0] are the PAL chroma comb mode bits that select how PAL, respectively.
the PAL chroma comb is configured The options for this feature are as follows:
Table 59. CCMP[2:0] Function  Bypass mode

Setting Description Configuration  NTSC, consisting of three filter characteristics
000 Adaptive comb mode Adaptive three-line  PAL, consisting of three filter characteristics
(default) chroma comb for CTAPSN See Table 92 for programming details.
= 01
6
Adaptive four-line chroma
comb for CTAPSN = 10 4
Adaptive five-line chroma
2
comb for CTAPSN = 11
100 Disable chroma comb 0
AMPLITUDE (dB)
101 Fixed chroma comb (top Fixed two-line chroma –2
lines of line memory) comb for CTAPSN = 01
–4
Fixed three-line chroma
comb for CTAPSN = 10 –6
Fixed four-line chroma
–8
110 Fixed chroma comb (all Fixed three-line chroma –10
lines of line memory) comb for CTAPSN = 01
–12
16169-025
Fixed four-line chroma 2.0 2.5 3.0 3.5 4.0 4.5 5.0
comb for CTAPSN = 10 FREQUENCY (MHz)
Fixed five-line chroma Figure 25. NTSC IF Filter Compensation (Zoomed Around fSC)
comb for CTAPSN = 11 6
111 Fixed chroma comb Fixed two-line chroma
(bottom lines of line comb for CTAPSN = 01 4
memory)
Fixed three-line chroma 2
AMPLITUDE (dB)

Fixed four-line chroma 0

–2
YCMP[2:0], Address 0x39, Bits[2:0], User Sub Map –4
PAL luma comb mode bits.

–6
Table 60. YCMP Function
–8
16169-026
Setting Description Configuration 3.0 3.5 4.0 4.5 5.0 5.5 6.0
000 Adaptive comb mode Adaptive five-line (three FREQUENCY (MHz)
(default) taps) luma comb

100 Disable luma comb Use low-pass/notch filter; see Figure 26. PAL IF Filter Compensation (Zoomed Around fSC)
the Y Shaping Filter section
ACE
101 Fixed luma comb (top Fixed three-line (two taps) The ADV7280A, ADV7281A, and ADV7282A devices can
lines of line memory) luma comb
increase the contrast of an image depending on the content of the
110 Fixed luma comb (all Fixed five-line (three taps)
lines of line memory) luma comb picture, brightening bright areas and darkening dark areas. ACE is
111 Fixed luma comb Fixed three-line (two taps) an algorithm that automatically varies the contrast level applied
(bottom lines of line luma comb across an image to enhance the picture detail visible. This
memory) automatic variation enables the contrast in the dark areas of an
image to be increased without saturating the bright areas, which is
IF FILTER COMPENSATION useful in automotive applications where it can be important to
IFFILTSEL[2:0], Address 0xF8, Bits[2:0], User Sub Map clearly discern objects in shaded areas.
The IFFILTSEL[2:0] bits allow the user to compensate for surface The ACE function is disabled by default. To enable the ACE
acoustic wave (SAW) filter characteristics on a composite input, as function, execute the register writes shown in Table 61. To disable
observed on tuner outputs. Figure 25 and Figure 26 show the ACE function, execute the register writes shown in Table 62.
The ACE feature works by sampling the chroma and luma levels in ACE_LUMA_GAIN[4:0], Address 0x83, Bits[4:0], User
the input image. This information is then histogrammed, and the Sub Map 2
resulting correction is applied to the entire image. This correction is
This is a control to set the autocontrast level for the luma channel
done in a nonlinear fashion so more correction can be applied to
when ACE_ENABLE is set to 1.
dark areas, if required.
For normal use, use the luma and chroma gain controls; however, Table 64. ACE_LUMA_GAIN[4:0] Function
in automotive applications, when dark areas may need further Setting Description
enhancement, use the gamma gain controls. 00000 Sets ACE luma autocontrast level to minimum
value
The reaction time of the ACE function can be set using the 01101 Sets ACE luma autocontrast level to default value
ACE_RESPONSE_SPEED[3:0] bits (see Table 93). The corrected (default)
image is faded over the original image using alpha blending, giving 11111 Sets ACE luma autocontrast level to maximum
a gradual change in contrast with scene changes. The ACE_ value
RESPONSE_SPEED[3:0] bits determine the duration of the
transition from the original to the corrected image. A larger value ACE_RESPONSE_SPEED[3:0], Address 0x85, Bits[7:4],
for these bits results in a faster transition time; however, a smaller User Sub Map 2
value gives more stability to rapid scene changes.
This control sets the reaction time of the ACE function.
The ACE_CHROMA_MAX[3:0] bits set a maximum value that
clips the chroma gain regardless of the ACE_CHROMA_ Table 65. ACE_RESPONSE_SPEED[3:0] Function
GAIN[3:0] settings. Setting Description
0000 Sets speed of ACE response to slowest value
The ACE_GAMMA_GAIN[3:0] bits are useful in automotive
1111 (default) Sets speed of ACE response
applications because they allow dramatic image enhancement in
1111 Sets speed of ACE response to fastest value
dark regions by stretching the contrast of pixels at the low (dark)
values of the image histogram. The luma and chroma gain controls
are normally used; however, use the ACE_GAMMA_GAIN[3:0] ACE_CHROMA_GAIN[3:0], Address 0x84, Bits[3:0],
bits when further stretching of the contrast in the dark areas of an User Sub Map 2
image is needed. This control sets the color saturation level for the color channels
when ACE_ENABLE is set to 1.
Table 61. Register Writes to Enable the ACE Function
Register Register Register Table 66. ACE_CHROMA_GAIN[3:0] Function
Map Address Write Description Setting Description
User Sub 0x0E 0x40 Enter User Sub 0000 Sets ACE color autosaturation level to minimum
Map Map 2 value
0x80 0x80 Enable ACE 1000 Sets ACE color autosaturation level to default value
0x0E 0x00 Reenter User Sub (default)
Map 1111 Sets ACE color autosaturation level to maximum
value
Table 62. Register Writes to Disable the ACE Function
Register Register Register ACE_CHROMA_MAX[3:0], Address 0x84, Bits[7:4], User
Sub Map 2
User Sub 0x0E 0x40 Enter User Sub
Map Map 2 This control sets a maximum threshold value that clips the
0x80 0x00 Disable ACE chroma gain regardless of the ACE_CHROMA_GAIN[3:0]
0x0E 0x00 Reenter User Sub settings.
Map
ACE_ENABLE, Address 0x80, Bit 7, User Sub Map 2 Table 67. ACE_CHROMA_MAX[3:0] Function
This control enables ACE. Setting Description
4b’0000 Sets maximum threshold for ACE color
Table 63. ACE_ENABLE Function autosaturation level to minimum value
Setting Description 1000 Sets maximum threshold for ACE color
0 (default) Disables ACE (default) autosaturation level to default value
1 Enables ACE 4b’1111 Sets maximum threshold for ACE color
autosaturation level to maximum value
ACE_GAMMA_GAIN[3:0], Address 0x85[3:0] User Sub Table 70. Register Writes to Enable the Dither Function
Map 2 Register Register Register
This control provides further contrast enhancement to the luma
User Sub 0x0E 0x40 Enter User Sub Map 2
and chroma gain controls and is particularly effective in the darker Map
areas of an image. 0x92 0x07 Enable 8-bit to 6-bit
downdither
Table 68. ACE_GAMMA_GAIN[3:0] Function
0x0E 0x00 Reenter user sub map
ACE_GAMMA_GAIN[3:0] Description
4b’0000 Sets further contrast enhancement to
minimum value
1000 (default) Sets further contrast enhancements to
default value Table 71. Register Writes to Disable the Dither Function
4b’1111 Sets further contrast enhancement to Register Register Register
maximum value Map Address Write Description
DITHER FUNCTION User Sub 0x0E 0x40 Enter User Sub Map 2
Map
The dither function converts the digital output of the ADV7280A, 0x92 0x06 Disable 8-bit to 6-bit
ADV7281A, and ADV7282A devices from 8-bit pixel data down to downdither
6-bit pixel data. This function makes it easier for the devices to 0x0E 0x00 Reenter user sub map
communicate with some LCD panels. The dither function is turned
off by default. The dither function is activated by the I2P FUNCTION
BR_DITHER_MODE bit.
This section applies only to the ADV7280A, ADV7280A-M,
BR_DITHER_MODE, Address 0x92, Bit 0, User Sub ADV7282A, and ADV7282A-M models.
Map 2 The I2P function converts an interlaced video input into a
BR_DITHER_MODE sets whether 8-bit to 6-bit downdithering is progressive video output. This function is performed without the
enabled or disabled. It is contained in the User Sub Map 2. need for external memory. Edge adaptive technology minimizes
video defects on low angle lines.
Table 69. BR_DITHER_MODE Function
The I2P function is disabled by default. To enable the I2P function,
BR_DITHER_MODE Description
see the recommended scripts for each device at www.analog.com.
0 (default) 8-bit to 6-bit downdither disabled
1 8-bit to 6-bit downdither enabled
The script described in Table 70 and Table 71 explains how to

enable and disable the 8-bit to 6-bit downdither function.
OUTPUT VIDEO FORMAT

All ADV7280A, ADV7281A, and ADV7282A devices (MIPI Tx or OUTPUT FORMAT CONTROL
ITU-R BT.656 output models) output video data in YCbCr 4:2:2 BT.656-4, Address 0x04, Bit 7, User Sub Map
format. The video timing is compliant with the ITU-R BT.656-3 or
ITU-R BT.656-4 standards. The BT.656-4 bit allows the user to select an output mode
compatible with the ITU-R BT.656-3 or ITU-R BT.656-4 standard.
The following bits modify the video output of all ADV7280A,
ADV7281A, and ADV7282A devices. For more output controls, When the BT.656-4 bit equals 0 (default), the ADV7280A,
see the ITU-R BT.656 Output section and MIPI CSI-2 Tx Output ADV7281A, and ADV7282A devices output video that is
section. compatible with the ITU-R BT.656-3 standard.
When the BT.656-4 bit equals 1, the ADV7280A, ADV7281A, and
SWAP COLOR OUTPUT
ADV7282A devices output video that is compatible with the ITU-R
SWPC, Address 0x27, Bit 7, User Sub Map BT.656-4 standard.
This bit allows Cr and Cb output samples to be swapped. This bit The BT.656-4 bit also affects the MIPI Tx active video output
affects the ADV7280A, ADV7280A-M, ADV7281A-M, resolution from ADV7280A-M, ADV7281A-M, and ADV7282A-
ADV7282A, and ADV7282A-M models. M devices. Table 72 shows all the possible active video output
When SWPC is 0 (default), no swapping is allowed. resolutions from the ADV7280A, ADV7280A-M, ADV7281A-M,
When SWPC is 1, the Cr and Cb output values are swapped. ADV7282A, and ADV7282A-M devices.
Events such as video source disconnection or reconnection can
cause the ADV7280A, ADV7281A, and ADV7282A devices to
output nonstandard line lengths during the event.
Table 72. Output Resolution from the ADV7280A, ADV7281A, and ADV7282A Devices
Digital Active Video Output Resolution in ITU-R BT.656-3 Active Video Output Resolution in ITU-R BT.656-4
Format Frames Mode (BT.656-4 Bit Equal to 0) Mode (BT.656-4 Bit Equal to 1)
480i Even 720 × 253 720 × 243
frames
Odd 720 × 254 720 × 244
frames
480p Even 720 × 507 720 × 487
frames
Odd 720 × 507 720 × 487
frames
576i Even 720 × 288 720 × 288
frames
Odd 720 × 288 720 × 288
frames
576p Even 720 × 576 720 × 576
frames
Odd 720 × 576 720 × 576
frames
ITU-R BT.656 OUTPUT

ITU-R BT.656 OUTPUT CONTROL REGISTERS VS/FIELD/SFL Sync Mux Selection
The following are controls for the ITU-R BT.656 output for the This section applies only to the ADV7280A model.
ADV7280A and ADV7282A devices. See the Global Control FLD_OUT_SEL[2:0], Address 0x6B, Bits[2:0], User Sub
Registers section for further control registers. Map
Tristate Output Drivers The FLD_OUT_SEL[2:0] bits select whether the VS/FIELD/
This section applies only to the ADV7280A model. SFL pin outputs vertical sync, horizontal sync, field sync, data
TOD, Address 0x03, Bit 6, User Sub Map enable (DE), or SFL signals.
This bit allows the user to tristate the output drivers of the Note that the VS/FIELD/SFL pin must be active for this selection to
ADV7280A. occur. See the ITU-R BT.656 Output Control Registers section for
more information.
Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/SFL
pins are tristated. Table 73. FLD_OUT_SEL[2:0] Function
The timing pins (HS and VS/FIELD/SFL pins) can be forced active Setting Description
via the TIM_OE bit. Note the HS and VS/FIELD/SFL pins are only 000 The VS/FIELD/SFL pin outputs horizontal sync
available on the ADV7280A model. information
001 The VS/FIELD/SFL pin outputs vertical sync
When TOD is set to 0, the output drivers are enabled. information
When TOD is set to 1 (default), the output drivers are tristated. 010 The VS/FIELD/SFL pin outputs field sync information
(default)
Tristate LLC Driver 011 The VS/FIELD/SFL pin outputs DE information
This section applies only to the ADV7280A and ADV7282A 100 The VS/FIELD/SFL pin outputs SFL information.
models.
TRI_LLC, Address 0x1D, Bit 7, User Sub Map HS Mux Selection
This section applies only to the ADV7280A model.
This bit allows the output drivers for the LLC pin of the
ADV7280A and ADV7282A models to be tristated. HS_OUT_SEL[2:0], Address 0x6A, Bits[2:0], User Sub
When TRI_LLC is set to 0, the LLC pin drivers work according to Map
the DR_STR_C[1:0] setting (pin enabled). The HS_OUT_SEL[2:0] bits allow the user to change the operation
When TRI_LLC is set to 1 (default), the LLC pin drivers are of the HS pin. The HS pin is set to output horizontal sync signals as
tristated. the default. The user can also set the HS pin to output vertical sync,
field sync, DE, or SFL information.
Timing Signals Output Enable
Note that the HS pin must be active for this selection to occur. See
This section applies only to the ADV7280A model.
the ITU-R BT.656 Output Control Registers section for more
TIM_OE, Address 0x04, Bit 3, User Sub Map information.
The TIM_OE bit must be regarded as an addition to the TOD Table 74. HS_OUT_SEL[2:0] Function
bit. Setting it high forces the output drivers for the HS and
HS_OUT_SEL[2:0] Description
VS/FIELD/SFL pins into the active state (that is, driving state)
000 (default) The HS pin output horizontal sync
even if the TOD bit is set. If TIM_OE is set to low, the HS and information.
VS/FIELD/SFL pins are tristated depending on the TOD bit. 001 The HS pin outputs vertical sync information.
This functionality is beneficial if the decoder is used only as a 010 The HS pin outputs field sync information.
timing generator, for example, if only the timing signals are 011 The HS pin outputs DE information.
extracted from an incoming signal or if the device is in free run 100 The HS pin outputs SFL information.
mode where a separate chip can output a company logo.
When TIM_OE is set to 0 (default), the HS and VS/FIELD/SFL
pins are tristated according to the TOD bit.
When TIM_OE is set to 1, the HS and VS/FIELD/SFL pins are
forced active all the time.
Drive Strength Selection (Data) Enable Subcarrier Frequency Lock Pin
This section applies only to the ADV7280A and ADV7282A This section applies only to the ADV7280A model.
models. EN_SFL_PIN, Address 0x04, Bit 1, User Sub Map
DR_STR[1:0], Address 0xF4, Bits[5:4], User Sub Map The EN_SFL_PIN bit enables the output of subcarrier lock
For EMC and crosstalk reasons, it can be desirable to strengthen or information (also known as genlock) from the ADV7280A core to
weaken the drive strength of the output drivers. The DR_STR[1:0] an encoder in a decoder/encoder back to back arrangement.
bits affect the drive strength for the pixel output pins (P7 to P0) and When the EN_SFL_PIN is set to 0 (default), the SFL output is
the timing pins (HS and VS/FIELD/SFL). Note the HS and disabled.
VS/FIELD/SFL pins are only available on the ADV7280A model.
When EN_SFL_PIN is set to 1, the subcarrier frequency lock
Table 75. DR_STR[1:0] Function information is output on the SFL pin.
Setting Description Polarity LLC Pin
00 Low drive strength (1×)1
This section applies only to the ADV7280A and ADV7282A
01 (default) Medium low drive strength (2×)
models.
10 Medium high drive strength (3×)
11 High drive strength (4×) PCLK, Address 0x37, Bit 0, User Sub Map
1
The polarity of the clock that exits the ADV7280A and ADV7282A
of the ADV7280A and ADV7282A models. models via the LLC pin can be inverted using the PCLK bit.
Drive Strength Selection (Clock) Changing the polarity of the LLC clock output can be necessary to
meet the setup and hold time expectations of subsequent devices
This section applies only to the ADV7280A and ADV7282A
that follow on.
models.
When PCLK is set to 0, the LLC output polarity is inverted.
DR_STR_C[1:0], Address 0xF4, Bits[3:2], User Sub Map
When PCLK is set to 1 (default), the LLC output polarity is normal.
The DR_STR_C[1:0] bits can select the strength of the LLC clock
signal output driver.
Table 76. DR_STR_C[1:0] Function

Setting Description
00 Low drive strength (1×)1
01 (default) Medium low drive strength (2×)
10 Medium high drive strength (3×)
11 High drive strength (4×)
1
of the ADV7280A and ADV7282A models.
MIPI CSI-2 TX OUTPUT

This section applies to the ADV7280A-M, ADV7281A-M, and To force the data lanes to exit the ULPS state, use the read and
ADV7282A-M models only. writes listed in Table 79.
The decoder in the ADV7280A-M, ADV7281A-M, and Table 79. Reads/Writes to Force MIPI Tx Data Lanes (D0P and
ADV7282A-M output is an ITU-R BT.656 data stream. The ITU-R D0N) to Exit Ultra Low ULPS
BT.656 data stream is connected into a MIPI Tx module. Data from Order of ESC_
the MIPI Tx module is fed into a D-PHY physical layer and output Reads/ ESC_MODE_ XSHUTDOWN_
serially from the device. Writes EN_D0 Setting D0 Setting Description
Read 1 0 Data lanes in ULPS
ULTRA LOW POWER STATE state.
The ADV7280A-M, ADV7281A-M and ADV7282A-M MIPI Tx First write 1 1 The ULPS exit
sequence is
can be programmed to enter the ultra low power state (ULPS) transmitted and
by the CSITX_PWRDN bit (see Table 77 and Table 96, the MIPI then D0P and D0N
CSI-2 Tx Map, Address 0x00, Bit 7). In this mode, the MIPI Tx exit ULPS state. D0P
and D0N go to the
clock and data lanes transition to the low level Thevenin output high level Thevenin
voltage (VOL) and do not oscillate. output voltage
(VOH).
Alternatively, the MIPI Tx clock and data lanes can be Second write 0 1 Data lanes enter
programmed to enter the ULPS state separately using the normal operation.
ESC_MODE_EN_CLK, ESC_XSHUTDOWN_CLK, Third write 0 0 No change. Data
ESC_MODE_EN_D0, and ESC_XSHUTDOWN_D0 bits. lanes remain in
normal operation.
Table 77. CSITX_PWRDN Function
Setting Description ESC_MODE_EN_CLK, Address 0x26, Bit 5 and ESC_
0 Power up CSI output block. The clock and data lanes XSHUTDOWN_CLK, Address 0x26, Bit 4, User Sub Map
output the ultra low power state exit sequence and exit The MIPI Tx clock lanes (CLKP and CLKN) can be programmed
the ultra low power state.
to enter and exit the ULPS using the ESC_MODE_EN_D0 and
1 Power down CSI output block. The clock and data lanes
ESC_XSHUTDOWN_D0 bits.
(default) output the ultra low power state entry sequence and
enter ultra low power state. To force the data lanes to enter the ULPS state, use the writes listed
in Table 80.
ESC_MODE_EN_D0, Address 0x26, Bit 7 and ESC_
XSHUTDOWN_D0, Address 0x26, Bit 6 (User Sub Map) Table 80. Writes to Force MIPI Tx Clock Lanes
(CLKP and CLKN) to Enter ULPS
The MIPI Tx data lanes (D0P and D0N) can be programmed to ESC_
enter and exit the ULPS using the ESC_MODE_EN_D0 and Order of ESC_MODE_ XSHUTDOWN_
ESC_XSHUTDOWN_D0 bits. Writes EN_CLK Setting CLK Setting Description
First write 0 0 Normal operation.
To force the data lanes to enter the ULPS state, use the writes listed Second write 1 0 The ULPS entry
in Table 78. sequence is
transmitted and then
Table 78. Writes to Force MIPI Tx Data Lanes (D0P and D0N) CLKP and CLKN enter
ULPS state. CLKP and
to Enter ULPS CLKN go to VOL.
ESC_
Order of ESC_MODE_EN_D0 XSHUTDOWN_
Writes Setting D0 Setting Description
First write 0 0 Normal
operation.
Second 1 0 The ULPS entry
write sequence is
transmitted and
then D0P and
D0N enter ULPS
state. D0P and
D0N go to VOL.
To force the data lanes to exit the ULPS state, use the read and VPP_SLAVE_ADDR, Bits[6:0], Address 0xFD, Bits[7:1]
writes listed in Table 81. User Sub Map
Table 81. Reads/Writes to Force MIPI Tx Clock Lanes These bits program the I2C address of the VPP map.
(CLKP and CLKN) to Exit ULPS Table 82. Program VPP Register Map Address
ESC_MODE_ ESC_
Order of EN_CLK XSHUTDOWN_ Setting Description
Reads/Writes Setting D0 Setting Description 0000000 (default) When set to this value, the VPP
Read 1 0 Clock lanes in ULPS state. register map cannot be written to
First write 1 1 The ULPS exit sequence or read from.
is transmitted and then 1000100 (recommended) This sets the VPP register map to a
CLKP and CLKN exit ULPS write address of 0x84 and a read
state. CLKP and CLKN go
to VOH.
address of 0x85. This is the
Second write 0 1 Clock lanes enter normal
recommended setting.
operation.
Third write 0 0 No change. Clock lanes CSI_TX_SLAVE_ADDR[6:0], Address 0xFE, Bits[7:1]
remain in normal
operation.
User Sub Map
Table 83. Program CSI_Tx Register Map Address

Setting Description
0000000 (default) When set to this value, the CSI_Tx
register map cannot be written to
or read from.
1000100 (recommended) This sets the CSI_Tx register map
to a write address of 0x88 and a
read address of 0x89. This is the
recommended setting.
POWER SUPPLY REQUIREMENTS

Table 84 and Table 85 show the current rating recommendations
for power supply design. Use these values when designing a power Table 85. Current Supply Design Recommendations
supply section to ensure that an adequate current can be supplied for the ADV7280A-M, ADV7281A-M, and ADV7282A-M
to the ADV7280A, ADV7281A, and ADV7282A devices. Models
Parameter Rating (mA)
Table 84. Current Supply Design Recommendations for the IDVDDIO 5
ADV7280A and ADV7282A Models IDVDD 110
Parameter Rating (mA) IAVDD 100
Digital I/O supply current (IDVDDIO) 20 IPVDD 20
Digital supply current (IDVDD) 110 MIPI Tx supply current (IMVDD) 20
Analog supply current (IAVDD) 100
Phase-locked loop supply current (IPVDD) 20
I2C REGISTER MAPS

To access all the registers listed in Table 87, SUB_USR_EN[1:0] in Register Address 0x0E must be programmed to 00. All reserved bits are left
blank.
To understand the read/write modes, see Table 86.
Table 86. Register Access Conventions

Mode Description
R/W Memory location has read and write access.
R Memory location is read access only. A read always returns 0 unless otherwise specified.
W Memory location is write access only.
Table 87. User Sub Map Register Map Details

Addr Register Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex
0x00 Input control R/W INSEL[4] INSEL[3] INSEL[2] INSEL[1] INSEL[0] 0x0E
0x01 Video R/W ENHSPLL Betacam ENVSPROC 0xC8
Selection 1
0x02 Video R/W VID_SEL[3] VID_SEL[2] VID_SEL[1] VID_SEL[0] 0x04
Selection 2
0x03 Output control R/W VBI_EN TOD 0x4C
0x04 Extended R/W BT.656-4 TIM_OE BL_C_VBI EN_SFL_PIN Range 0x35
output control
0x05 Reserved
0x06 Reserved
0x07 Autodetect R/W AD_SEC525_ AD_SECAM_ AD_N443_EN AD_P60_EN AD_PALN_EN AD_PALM_EN AD_NTSC_EN AD_PAL_EN 0x7F
enable EN EN
0x08 Contrast R/W CON[7] CON[6] CON[5] CON[4] CON[3] CON[2] CON[1] CON[0] 0x80
0x09 Reserved
0x0A Brightness R/W BRI[7] BRI[6] BRI[5] BRI[4] BRI[3] BRI[2] BRI[1] BRI[0] 0x00
adjust
0x0B Hue adjust R/W HUE[7] HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0] 0x00
0x0C Default Value Y R/W DEF_Y[5] DEF_Y[4] DEF_Y[3] DEF_Y[2] DEF_Y[1] DEF_Y[0] DEF_VAL_AUTO_ DEF_VAL_ 0x36
EN EN
0x0D Default Value C R/W DEF_C[7] DEF_C[6] DEF_C[5] DEF_C[4] DEF_C[3] DEF_C[2] DEF_C[1] DEF_C[0] 0x7C
0x0E Analog Devices R/W SUB_USR_ SUB_USR_ 0x00
Control 1 EN[1] EN[0]
0x0F Power R/W Reset PWRDWN 0x20
management
0x10 Status 1 R COL_KILL AD_ AD_ AD_ FOLLOW_ FSC_LOCK LOST_LOCK IN_LOCK
RESULT[2] RESULT[1] RESULT[0] PW
0x11 IDENT R IDENT[7] IDENT[6] IDENT[5] IDENT[4] IDENT[3] IDENT[2] IDENT[1] IDENT[0] 0x43
0x12 Status 2 R FSC_NSTD LL_NSTD MV_AGC_DET MV_PS_DET MVCS_T3 MVCS_DET
0x13 Status 3 R PAL_SW_LOCK Interlaced STD_FLD_ FREE_RUN_ Reserved SD_OP_50Hz Reserved INST_
LEN ACT HLOCK
0x14 Analog clamp R/W CCLEN FREE_RUN_ FREE_RUN_ FREE_RUN_ 0x10
control PAT_SEL[2] PAT_SEL[1] PAT_SEL[0]
0x15 Digital Clamp R/W DCT[1] DCT[0] DCFE 0x00
Control 1
0x16 Reserved
0x17 Shaping Filter R/W CSFM[2] CSFM[1] CSFM[0] YSFM[4] YSFM[3] YSFM[2] YSFM[1] YSFM[0] 0x01
Control 1
0x18 Shaping Filter R/W WYSFMOVR WYSFM[4] WYSFM[3] WYSFM[2] WYSFM[1] WYSFM[0] 0x93
Control 2
0x19 Comb filter R/W NSFSEL[1] NSFSEL[0] PSFSEL[1] PSFSEL[0] 0xF1
control
0x1D Analog Devices R/W TRI_LLC 0xC0
Control 2
0x27 Pixel delay R/W SWPC AUTO_ CTA[2] CTA[1] CTA[0] LTA[1] LTA[0] 0x58
control PDC_EN
0x2B Misc gain R/W CKE PW_UPD 0xE1
control
0x2C AGC mode R/W LAGC[2] LAGC[1] LAGC[0] CAGC[1] CAGC[0] 0xAE
control
0x2D Chroma Gain W CAGT[1] CAGT[0] CMG[11] CMG[10] CMG[9] CMG[8] 0xF4
Control 1
0x2D Chroma Gain 1 R CG[11] CG[10] CG[9] CG[8]
0x2E Chroma Gain W CMG[7] CMG[6] CMG[5] CMG[4] CMG[3] CMG[2] CMG[1] CMG[0] 0x00
Control 2
0x2E Chroma Gain 2 R CG[7] CG[6] CG[5] CG[4] CG[3] CG[2] CG[1] CG[0]
0x2F Luma Gain W LAGT[1] LAGT[0] LMG[11] LMG[10] LMG[9] LMG[8] 0xF0
Control 1
0x2F Luma Gain 1 R LG[11] LG[10] LG[9] LG[8]
0x30 Luma Gain W LMG[7] LMG[6] LMG[5] LMG[4] LMG[3] LMG[2] LMG[1] LMG[0] 0x00
Control 2
0x30 Luma Gain 2 R LG[7] LG[6] LG[5] LG[4] LG[3] LG[2] LG[1] LG[0]
0x31 VS/FIELD R/W NEWAVMODE HVSTIM 0x02
Control 1
0x32 VS/FIELD R/W VSBHO VSBHE 0x41
Control 2
0x33 VS/FIELD R/W VSEHO VSEHE 0x84
Control 3
0x34 HS Position R/W HSB[10] HSB[9] HSB[8] HSE[10] HSE[9] HSE[8] 0x00
Control 1
0x35 HS Position R/W HSB[7] HSB[6] HSB[5] HSB[4] HSB[3] HSB[2] HSB[1] HSB[0] 0x02
Control 2
0x36 HS Position R/W HSE[7] HSE[6] HSE[5] HSE[4] HSE[3] HSE[2] HSE[1] HSE[0] 0x00
Control 3
0x37 Polarity R/W PHS PVS PF PCLK 0x09
0x38 NTSC comb R/W CTAPSN[1] CTAPSN[0] CCMN[2] CCMN[1] CCMN[0] YCMN[2] YCMN[1] YCMN[0] 0x80
control
0x39 PAL comb R/W CTAPSP[1] CTAPSP[0] CCMP[2] CCMP[1] CCMP[0] YCMP[2] YCMP[1] YCMP[0] 0xC0
control
0x3A ADC control R/W PWRDWN_ PWRDWN_MUX_1 PWRDWN_MUX_2 MUX_PDN_ 0x00
MUX_0P OVERRIDE
0x3D Manual R/W CKILLTHR[2] CKILLTHR[1] CKILLTHR[0] 0x22
window control
0x41 Resample R/W SFL_INV 0x01
control
0x4D CTI DNR R/W DNR_EN CTI_AB[1] CTI_AB[0] CTI_AB_EN CTI_EN 0xEF
Control 1
0x4E CTI DNR R/W CTI_C_TH[7] CTI_C_TH[6] CTI_C_TH[5] CTI_C_TH[4] CTI_C_TH[3] CTI_C_TH[2] CTI_C_TH[1] CTI_C_TH[0] 0x08
Control 2
0x50 DNR Noise R/W DNR_TH[7] DNR_TH[6] DNR_TH[5] DNR_TH[4] DNR_TH[3] DNR_TH[2] DNR_TH[1] DNR_TH[0] 0x08
Threshold 1
0x51 Lock count R/W FSCLE SRLS COL[2] COL[1] COL[0] CIL[2] CIL[1] CIL[0] 0x24
0x5D DIAG1 control R/W DIAG1_ DIAG1_SLICE_ DIAG1_SLICE_ DIAG1_SLICE_ 0x6D
SLICER_ LEVEL[2] LEVEL[1] LEVEL[0]
PWRDN
0x5E DIAG2 control R/W DIAG2_ DIAG2_SLICE_ DIAG2_SLICE_ DIAG2_SLICE_ 0x6D
SLICER_ LEVEL[2] LEVEL[1] LEVEL[0]
PWRDN
0x59 GPO R/W GPO_ENABLE GPO[2] GPO[1] GPO[0] 0x00
0x60 ADC Switch 3 R/W MUX_0N[3] MUX_0N[2] MUX_0N[1] MUX_0N[0] 0x10
0x6A Output Sync R/W HS_OUT_SEL[2] HS_OUT_SEL[1] HS_OUT_ 0x00
Select 1 SEL[0]
0x6B Output Sync R/W FLD_OUT_SEL[2] FLD_OUT_SEL[1] FLD_OUT_ 0x12
Select 2 SEL[0]
0x8F Free Run Line W LLC_PAD_ LLC_PAD_ LLC_PAD_ 0x00
Length 1 SEL[2] SEL[1] SEL[0]
0x99 CCAP1 R CCAP1[7] CCAP1[6] CCAP1[5] CCAP1[4] CCAP1[3] CCAP1[2] CCAP1[1] CCAP1[0]
0x9A CCAP2 R CCAP2[7] CCAP2[6] CCAP2[5] CCAP2[4] CCAP2[3] CCAP2[2] CCAP2[1] CCAP2[0]
0x9B Letterbox 1 R LB_LCT[7] LB_LCT[6] LB_LCT[5] LB_LCT[4] LB_LCT[3] LB_LCT[2] LB_LCT[1] LB_LCT[0]
0x9C Letterbox 2 R LB_LCM[7] LB_LCM[6] LB_LCM[5] LB_LCM[4] LB_LCM[3] LB_LCM[2] LB_LCM[1] LB_LCM[0]
0x9D Letterbox 3 R LB_LCB[7] LB_LCB[6] LB_LCB[5] LB_LCB[4] LB_LCB[3] LB_LCB[2] LB_LCB[1] LB_LCB[0]
0xB2 CRC enable W CRC_ENABLE 0x1C
0xC3 ADC Switch 1 R/W MUX_1[3] MUX_1[2] MUX_1[1] MUX_1[0] MUX_0P[3] MUX_0P[2] MUX_0P[1] MUX_0P[0] 0x00
0xC4 ADC Switch 2 R/W MAN_MUX_EN MUX_2[3] MUX_2[2] MUX_2[1] MUX_2[0] 0x00
0xDC Letterbox R/W LB_TH[4] LB_TH[3] LB_TH[2] LB_TH[1] LB_TH[0] 0xAC
Control 1
0xDD Letterbox R/W LB_SL[3] LB_SL[2] LB_SL[1] LB_SL[0] LB_EL[3] LB_EL[2] LB_EL[1] LB_EL[0] 0x4C
Control 2
0xDE ST Noise R ST_NOISE_VLD ST_NOISE[10] ST_NOISE[9] ST_NOISE[8]
Readback 1
0xDF ST Noise R ST_NOISE[7] ST_NOISE[6] ST_NOISE[5] ST_NOISE[4] ST_NOISE[3] ST_NOISE[2] ST_NOISE[1] ST_NOISE[0]
Readback 2
0xE1 SD offset Cb R/W SD_OFF_Cb[7] SD_OFF_Cb[6] SD_OFF_Cb[5 SD_OFF_Cb[4] SD_OFF_Cb[3] SD_OFF_Cb[2] SD_OFF_Cb[1] SD_OFF_ 0x80
channel ] Cb[0]
0xE2 SD offset Cr R/W SD_OFF_Cr[7] SD_OFF_Cr[6] SD_OFF_Cr[5] SD_OFF_Cr[4] SD_OFF_Cr[3] SD_OFF_Cr[2] SD_OFF_Cr[1] SD_OFF_ 0x80
channel Cr[0]
0xE3 SD saturation R/W SD_SAT_Cb[7] SD_SAT_Cb[6] SD_SAT_ SD_SAT_Cb[4] SD_SAT_Cb[3] SD_SAT_Cb[2] SD_SAT_Cb[1] SD_SAT_ 0x80
Cb channel Cb[5] Cb[0]
0xE4 SD saturation R/W SD_SAT_Cr[7] SD_SAT_Cr[6] SD_SAT_Cr[5] SD_SAT_Cr[4] SD_SAT_Cr[3] SD_SAT_Cr[2] SD_SAT_Cr[1] SD_SAT_ 0x80
Cr channel Cr[0]
0xE5 NTSC V bit R/W NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG[4] NVBEG[3] NVBEG[2] NVBEG[1] NVBEG[0] 0x25
begin
0xE6 NTSC V bit end R/W NVENDDELO NVENDDELE NVENDSIGN NVEND[4] NVEND[3] NVEND[2] NVEND[1] NVEND[0] 0x04
0xE7 NTSC F bit R/W NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG[4] NFTOG[3] NFTOG[2] NFTOG[1] NFTOG[0] 0x63
toggle
0xE8 PAL V bit begin R/W PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG[4] PVBEG[3] PVBEG[2] PVBEG[1] PVBEG[0] 0x65
0xE9 PAL V bit end R/W PVENDDELO PVENDDELE PVENDSIGN PVEND[4] PVEND[3] PVEND[2] PVEND[1] PVEND[0] 0x14
0xEA PAL F bit toggle R/W PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG[4] PFTOG[3] PFTOG[2] PFTOG[1] PFTOG[0] 0x63
0xEB Vblank R/W NVBIOLCM[1] NVBIOLCM[0] NVBIELCM[1] NVBIELCM[0] PVBIOLCM[1] PVBIOLCM[0] PVBIELCM[1] PVBIELCM[0] 0x55
Control 1
0xEC Vblank R/W NVBIOCCM[1] NVBIOCCM NVBIECCM[1] NVBIECCM[0] PVBIOCCM[1] PVBIOCCM[0] PVBIECCM[1] PVBIECCM[0 0x55
Control 2 [0] ]
0xF3 AFE Control 1 R/W AA_FILT_ AA_FILT_EN[3] AA_FILT_EN[2] AA_FILT_EN[1] AA_FILT_EN 0x00
MAN_OVR [0]
0xF4 Drive strength R/W GLITCH_FILT_ DR_STR[1] DR_STR[0] DR_STR_C[1] DR_STR_C[0] DR_STR_S[1] DR_STR_ 0x15
BYP S[0]
0xF8 IF_COMP_ R/W IFFILTSEL[2] IFFILTSEL[1] IFFILTSEL[0] 0x00
CONTROL
0xF9 VS mode R/W VS_COAST_ VS_COAST_MODE[0] EXTEND_VS_MIN_ EXTEND_ 0x03
control MODE[1] FREQ VS_MAX_
FREQ
0xFB Peaking gain R/W PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_ PEAKING_GAIN[2] PEAKING_GAIN[1] PEAKING_ 0x40
GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[0]
0xFC DNR Noise R/W DNR_TH2[7] DNR_TH2[6] DNR_TH2[5] DNR_TH2[4] DNR_TH2[3] DNR_TH2[2] DNR_TH2[1] DNR_TH2[0] 0x04
Threshold 2
0xFD VPP slave R/W VPP_SLAVE_ VPP_SLAVE_ VPP_SLAVE_ VPP_SLAVE_ VPP_SLAVE_ VPP_SLAVE_ VPP_SLAVE_
address ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
0xFE CSI Tx slave R/W CSI_TX_ CSI_TX_ CSI_TX_ CSI_TX_ CSI_TX_SLAVE_ CSI_TX_SLAVE_ CSI_TX_SLAVE_ 0x00
address SLAVE_ SLAVE_ SLAVE_ SLAVE_ ADDR[2] ADDR[1] ADDR[0]
ADDR[6] ADDR[5] ADDR[4] ADDR[3]
To access the registers listed in Table 88, SUB_USR_EN[1:0] in Register Address 0x0E, user sub map, must be programmed to 10. All read only
bits are left blank.
Table 88. User Sub Map 2 Register Map Details

Register
Addr Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex
0x80 ACE Control 1 R/W ACE_ENABLE 0x00
0x83 ACE Control 4 R/W ACE_LUMA_ ACE_LUMA_ ACE_LUMA_ ACE_LUMA_ ACE_LUMA_ 0x0D
GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0]
0x84 ACE Control 5 R/W ACE_ ACE_ ACE_ ACE_ ACE_CHROMA_ ACE_CHROMA_ ACE_CHROMA_ ACE_ 0x88
CHROMA_ CHROMA_ CHROMA_ CHROMA_ GAIN[3] GAIN[2] GAIN[1] CHROMA_
MAX[3] MAX[2] MAX[1] MAX[0] GAIN[0]
0x85 ACE Control 6 R/W ACE_ ACE_ ACE_ ACE_ ACE_GAMMA_ ACE_GAMMA_ ACE_GAMMA_ ACE_ 0xF8
RESPONSE_ RESPONSE_ RESPONSE_ RESPONSE_ GAIN[3] GAIN[2] GAIN[1] GAMMA_
SPEED[3] SPEED[2] SPEED[2] SPEED[1] GAIN[0]
0x92 Dither control R/W BR_DITHER_ 0x00
MODE
0xD9 MIN_MAX_0 R/W MIN_ MIN_THRESH_ MIN_THRESH_ MIN_THRESH_ MIN_THRESH_Y[3] MIN_THRESH_Y[2] MIN_THRESH_ MIN_THRESH_ 0x00
THRESH_Y[7] Y[6] Y[5] Y[4] Y[1] Y[0]
Register
Addr Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex
0xDA MIN_MAX_1 R/W MAX_ MAX_THRESH_ MAX_THRESH_ MAX_THRESH_ MAX_THRESH_Y[3] MAX_THRESH_ MAX_THRESH_ MAX_ 0xFF
THRESH_Y[7] Y[6] Y[5] Y[4] Y[2] Y[1] THRESH_Y[0]
0xDB MIN_MAX_2 R/W MIN_ MIN_THRESH_ MIN_THRESH_C MIN_THRESH_ MIN_THRESH_C[3] MIN_THRESH_C[2] MIN_THRESH_ MIN_THRESH_ 0x00
THRESH_C[7] C[6] [5] C[4] C[1] C[0]
0xDC MIN_MAX_3 R/W MAX_ MAX_THRESH_ MAX_THRESH_ MAX_THRESH_ MAX_THRESH_C[3] MAX_THRESH_ MAX_THRESH_ MAX_ 0xFF
THRESH_C[7] C[6] C[5] C[4] C[2] C[1] THRESH_C[0]
0xDD MIN_MAX_4 R/W MIN_ MIN_ MIN_ MIN_ MAX_SAMPLES_ MAX_SAMPLES_ MAX_SAMPLES_ MAX_ 0xCC
SAMPLES_ SAMPLES_ SAMPLES_ SAMPLES_ ALLOWED_Y[3] ALLOWED_ ALLOWED_Y[1] SAMPLES_
ALLOWED_ ALLOWED_ ALLOWED_Y[1] ALLOWED_Y[0] Y[2] ALLOWED_
Y[3] Y[2] Y[0]
0xDE MIN_MAX_5 R/W MIN_ MIN_ MIN_ MIN_SAMPLES_ MAX_SAMPLES_ MAX_SAMPLES_ MAX_SAMPLES_ MAX_ 0xCC
SAMPLES_ SAMPLES_ SAMPLES_ ALLOWED_C[0] ALLOWED_C[3] ALLOWED_C[2] ALLOWED_C[1] SAMPLES_
ALLOWED_ ALLOWED_ ALLOWED_C[1] ALLOWED_
C[3] C[2] C[0]
0xE0 FL control R/W FL_ENABLE 0x00
0xE1 Y Average 0 R/W LINE_ LINE_START[7] LINE_START[6] LINE_START[5] LINE_START[4] LINE_START[3] LINE_START[2] LINE_START[1] 0x11
START[8]
0xE2 Y Average 1 R/W LINE_END[8] LINE_END[7] LINE_END[6] LINE_END[5] LINE_END[4] LINE_END[3] LINE_END[2] LINE_END[1] 0x88
0xE3 Y Average 2 R/W SAMPLE_ SAMPLE_ SAMPLE_ SAMPLE_ SAMPLE_START[5] SAMPLE_START[4] SAMPLE_ SAMPLE_ 0x1B
START[9] START[8] START[7] START[6] START[3] START[2]
0xE4 Y Average 3 R/W SAMPLE_ SAMPLE_ SAMPLE_ SAMPLE_END[6] SAMPLE_END[5] SAMPLE_END[4] SAMPLE_END[3] SAMPLE_ 0xD7
END[9] END[8] END[7] END[2]
0xE5 Y Average 4 R/W SAMPLE_ SAMPLE_ SAMPLE_ SAMPLE_ LINE_END[0] LINE_START[0] 0x23
END[1] END[0] START[1] START[0]
0xE6 Y Average 5 R/W Y_AVG_TIME_ Y_AVG_TIME_ Y_AVG_TIME_ Y_AVG_FILT_EN CAPTURE_ 0x10
CONST[2] CONST[1] ONST[0] VALUE
0xE7 Y average R Y_ Y_AVERAGE[8] Y_AVERAGE[7] Y_AVERAGE[6] Y_AVERAGE[5] Y_AVERAGE[4] Y_AVERAGE[3] Y_AVERAGE[2]
data MSB AVERAGE[9]
0xE8 Y average R Y_AVERAGE[1] Y_AVERAGE[0]
data LSB
To access the registers listed in Table 89, SUB_USR_EN[1:0] in Register Address 0x0E, user sub map, must be programmed to 01. All read
only registers are left blank.
Table 89. Interrupt/VDP Sub Map Details

0x40 Interrupt R/W INTRQ_DUR_ INTRQ_DUR_SEL[0] MV_INTRQ_SEL[1] MV_INTRQ_ MPU_STIM_ INTRQ_OP_ INTRQ_OP_ 0x10
Configuration 1 SEL[1] SEL[0] INTRQ SEL[1] SEL[0]
0x42 Interrupt R MV_PS_CS_Q SD_FR_CHNG_Q SD_UNLOCK_Q SD_LOCK_Q
Status 1
0x43 Interrupt W MV_PS_CS_CLR SD_FR_CHNG_CLR SD_UNLOCK_ SD_LOCK_CLR 0x00
Clear 1 CLR
0x44 Interrupt R/W MV_PS_CS_MSKB1 SD_FR_CHNG_ SD_UNLOCK_ SD_LOCK_ 0x00
Mask 1 MSKB1 MSKB1 MSKB1
0x45 Raw Status 2 R MPU_STIM_ CHX_MIN_MAX_ EVEN_FIELD CCAPD
INTRQ INTRQ
0x46 Interrupt R MPU_STIM_ SD_FIELD_ CCAPD_Q
Status 2 INTRQ_Q CHNGD_Q
0x47 Interrupt W MPU_STIM_ CHX_MIN_MAX_ SD_FIELD_ CCAPD_CLR 0x00
Clear 2 INTRQ_CLR INTRQ_CLR CHNGD_CLR
0x48 Interrupt R/W MPU_STIM_ CHX_MIN_MAX_ SD_FIELD_ CCAPD_MSKB1 0x00
Mask 2 INTRQ_MSKB1 INTRQ_MSKB1 CHNGD_MSKB1
0x49 Raw Status 3 R SCM_LOCK SD_H_LOCK SD_V_LOCK SD_OP_50Hz
0x4A Interrupt R PAL_SW_ SCM_LOCK_ SD_AD_ SD_H_LOCK_ SD_V_LOCK_ SD_OP_
Status 3 LK_CHNG_Q CHNG_Q CHNG_Q CHNG_Q CHNG_Q CHNG_Q
0x4B Interrupt W PAL_SW_ SCM_LOCK_ SD_AD_ SD_H_LOCK_ SD_V_LOCK_ SD_OP_CHNG_ 0x00
Clear 3 LK_CHNG_CLR CHNG_CLR CHNG_CLR CHNG_CLR CHNG_CLR CLR
0x4C Interrupt R/W PAL_SW_LK_ SCM_LOCK_ SD_AD_ SD_H_LOCK_ SD_V_LOCK_ SD_OP_CHNG_ 0x00
Mask 3 CHNG_MSKB1 CHNG_MSKB1 CHNG_MSKB1 CHNG_MSKB1 CHNG_MSKB1 MSKB1
0x4E Interrupt R VDP_CGMS_ VDP_CCAPD_Q
Status 4 WSS_CHNGD_Q
0x4F Interrupt Clear W VDP_CGMS_ VDP_CCAPD_ 0x00
4 WSS_CHNGD_ CLR
CLR
0x50 Interrupt R/W VDP_CGMS_ VDP_CCAPD_ 0x00
Mask 4 WSS_CHNGD_ MSKB1
MSKB1
0x51 Interrupt R Y_CHANNEL_ Y_CHANNEL_ CB_ CB_CHANNEL_ CR_CHANNEL_ CR_CHANNEL_
Latch 0 MIN_VIOLATION MAX_ CHANNEL_ MAX_ MIN_VIOLATION MAX_
VIOLATION MIN_ VIOLATION VIOLATION
VIOLATION
0x53 Interrupt R DIAG_TRI2_L1 DIAG_TRI1_L1
Status 5
0x54 Interrupt W DIAG_TRI2_ DIAG_TRI1_L1_ 0x00
Clear 5 L1_CLR CLR
0x55 Interrupt R/W DIAG_TRI2_L1 DIAG_TRI1_L1 0x00
Mask 5 MSK MSK
0x60 VDP_ R/W WST_PKT_ VDP_TTXT_ VDP_TTXT_ VDP_TTXT_ 0x88
CONFIG_1 DECODE_ TYPE_MAN_ TYPE_MAN[1] TYPE_MAN[0]
DISABLE ENABLE
0x62 VDP_ADF_ R/W ADF_ENABLE ADF_MODE[1] ADF_MODE[0] ADF_DID[4] ADF_DID[3] ADF_DID[2] ADF_DID[1] ADF_DID[0] 0x15
CONFIG_1
0x63 VDP_ADF_ R/W DUPLICATE_ ADF_SDID[5] ADF_SDID[4] ADF_SDID[3] ADF_SDID[2] ADF_SDID[1] ADF_SDID[0] 0x2A
CONFIG_2 ADF
0x64 VDP_LINE_00E R/W MAN_LINE_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
PGM P318[3] P318[2] P318[1] P318[0]
0x65 VDP_LINE_00F R/W VBI_DATA_P6_ VBI_DATA_P6_ VBI_DATA_P6_ VBI_DATA_P6_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
N23[3] N23[2] N23[1] N23[0] P319_N286[3] P319_N286[2] P319_N286[1] P319_N286[0]
0x66 VDP_LINE_010 R/W VBI_DATA_P7_ VBI_DATA_P7_ VBI_DATA_P7_ VBI_DATA_P7_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
N24[3] N24[2] N24[1] N24[0] P320_N287[3] P320_N287[2] P320_N287[1] P320_N287[0]
0x67 VDP_LINE_011 R/W VBI_DATA_P8_ VBI_DATA_P8_ VBI_DATA_P8_ VBI_DATA_P8_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
N25[3] N25[2] N25[1] N25[0] P321_N288[3] P321_N288[2] P321_N288[1] P321_N288[0]
0x68 VDP_LINE_012 R/W VBI_DATA_ VBI_DATA_P9[2] VBI_DATA_P9[1] VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P9[3] P9[0] P322[3] P322[2] P322[1] P322[0]
0x69 VDP_LINE_013 R/W VBI_DATA_ VBI_DATA_P10[2] VBI_DATA_P10[1] VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P10[3] P10[0] P323[3] P323[2] P323[1] P323[0]
0x6A VDP_LINE_014 R/W VBI_DATA_ VBI_DATA_P11[2] VBI_DATA_P11[1] VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P11[3] P11[0] P324_N272[3] P324_N272[2] P324_N272[1] P324_N272[0]
0x6B VDP_LINE_015 R/W VBI_DATA_P12_ VBI_DATA_P12_ VBI_DATA_P12_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
N10[3] N10[2] N10[1] P12_N10[0] P325_N273[3] P325_N273[2] P325_N273[1] P325_N273[0]
0x6C VDP_LINE_016 R/W VBI_DATA_ VBI_DATA_P13_ VBI_DATA_P13_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P13_N11[3] N11[2] N11[1] P13_N11[0] P326_N274[3] P326_N274[2] P326_N274[1] P326_N274[0]
0x6D VDP_LINE_017 R/W VBI_DATA_ VBI_DATA_P14_ VBI_DATA_P14_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P14_N12[3] N12[2] N12[1] P14_N12[0] P327_N275[3] P327_N275[2] P327_N275[1] P327_N275[0]
0x6E VDP_LINE_018 R/W VBI_DATA_ VBI_DATA_P15_ VBI_DATA_P15_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P15_N13[3] N13[2] N13[1] P15_N13[0] P328_N276[3] P328_N276[2] P328_N276[1] P328_N276[0]
0x6F VDP_LINE_019 R/W VBI_DATA_ VBI_DATA_P16_ VBI_DATA_P16_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P16_N14[3] N14[2] N14[1] P16_N14[0] P329_N277[3] P329_N277[2] P329_N277[1] P329_N277[0]
0x70 VDP_LINE_01A R/W VBI_DATA_ VBI_DATA_P17_ VBI_DATA_P17_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P17_N15[3] N15[2] N15[1] P17_N15[0] P330_N278[3] P330_N278[2] P330_N278[1] P330_N278[0]
0x71 VDP_LINE_01B R/W VBI_DATA_ VBI_DATA_P18_ VBI_DATA_P18_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P18_N16[3] N16[2] N16[1] P18_N16[0] P331_N279[3] P331_N279[2] P331_N279[1] P331_N279[0]
0x72 VDP_LINE_01C R/W VBI_DATA_ VBI_DATA_P19_ VBI_DATA_P19_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P19_N17[3] N17[2] N17[1] P19_N17[0] P332_N280[3] P332_N280[2] P332_N280[1] P332_N280[0]
0x73 VDP_LINE_01D R/W VBI_DATA_ VBI_DATA_P20_ VBI_DATA_P20_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P20_N18[3] N18[2] N18[1] P20_N18[0] P333_N281[3] P333_N281[2] P333_N281[1] P333_N281[0]
0x74 VDP_LINE_01E R/W VBI_DATA_ VBI_DATA_P21_ VBI_DATA_P21_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P21_N19[3] N19[2] N19[1] P21_N19[0] P334_N282[3] P334_N282[2] P334_N282[1] P334_N282[0]
0x75 VDP_LINE_01F R/W VBI_DATA_ VBI_DATA_P22_ VBI_DATA_P22_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P22_N20[3] N20[2] N20[1] P22_N20[0] P335_N283[3] P335_N283[2] P335_N283[1] P335_N283[0]
0x76 VDP_LINE_020 R/W VBI_DATA_ VBI_DATA_P23_ VBI_DATA_P23_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P23_N21[3] N21[2] N21[1] P23_N21[0] P336_N284[3] P336_N284[2] P336_N284[1] P336_N284[0]
0x77 VDP_LINE_021 R/W VBI_DATA_ VBI_DATA_P24_ VBI_DATA_P24_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ VBI_DATA_ 0x00
P24_N22[3] N22[2] N22[1] P24_N22[0] P337_N285[3] P337_N285[2] P337_N285[1] P337_N285[0]
0x78 VDP_STATUS R TTXT_AVL CGMS_WSS_ CC_EVEN_FIELD CC_AVL
AVL
0x78 VDP_STATUS_ W CGMS_WSS_ CC_CLEAR 0x00
CLEAR CLEAR
0x79 VDP_CCAP_ R CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_
DATA_0 BYTE_1[7] BYTE_1[6] BYTE_1[5] BYTE_1[4] BYTE_1[3] BYTE_1[2] BYTE_1[1] BYTE_1[0]
0x7A VDP_CCAP_ R CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_ CCAP_
DATA_1 BYTE_2[7] BYTE_2[6] BYTE_2[5] BYTE_2[4] BYTE_2[3] BYTE_2[2] BYTE_2[1] BYTE_2[0]
0x7D VDP_CGMS_ R CGMS_CRC[5] CGMS_CRC[4] CGMS_CRC[3] CGMS_CRC[2]
WSS_DATA_0
0x7E VDP_CGMS_ R CGMS_CRC[1] CGMS_CRC[0] CGMS_WSS[13] CGMS_WSS[12] CGMS_ CGMS_WSS[10] CGMS_WSS[9] CGMS_WSS[8]
WSS_DATA_1 WSS[11]
0x7F VDP_CGMS_ R CGMS_WSS[7] CGMS_WSS[6] CGMS_WSS[5] CGMS_WSS[4] CGMS_WSS[3] CGMS_WSS[2] CGMS_WSS[1] CGMS_WSS[0]
WSS_DATA_2
0x9C VDP_OUTPUT_ R/W WSS_CGMS_ 0x30
SEL CB_CHANGE
1
B at the end of the bit name means an overbar for the whole bit name.
To access the registers listed in Table 90, set the VPP I2C slave address by writing to Register 0xFD in the user sub map. All read only bits are left
blank.
Table 90. VPP Map Details

Address Register Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Hex
0x41 DEINT_RESET R/W DEINT_RESET 0x00
0x55 I2C_DEINT_ENABLE R/W I2C_DEINT_ENABLE 0x00
0x5B ADV_TIMING_MODE_EN R/W ADV_TIMING_MODE_EN 0x00
To access the registers listed in Table 91, set the MIPI CSI-2 Tx I2C slave address by writing to Register 0xFE in the user sub map. All read only
registers are left blank.
Table 91. MIPI CSI-2 Tx Map Details

0x00 CSITX_PWRDN R/W CSITX_PWRDN 0x80
0x01 TLPX R/W TLPX[4] TLPX[3] TLPX[2] TLPX[1] TLPX[0] 0x18
0x02 THSPREP R/W THSPREP[4] THSPREP[3] THSPREP[2] THSPREP[1] THSPREP[0] 0x18
0x03 THSZEROS R/W THSZEROS[4] THSZEROS[3] THSZEROS[2] THSZEROS[1] THSZEROS[0] 0x30
0x04 THSTRAIL R/W THSTRAIL[4] THSTRAIL[3] THSTRAIL[2] THSTRAIL[1] THSTRAIL[0] 0x20
0x05 THSEXIT R/W THSEXIT[4] THSEXIT[3] THSEXIT[2] THSEXIT[1] THSEXIT[0] 0x28
0x06 TCLK_PREP R/W TCLK_PREP[2] TCLK_PREP[1] TCLK_PREP[0] 0x40
0x07 TCLK_ZEROS R/W TCLK_ZEROS[4] TCLK_ZEROS[3] TCLK_ZEROS[2] TCLK_ZEROS[1] TCLK_ZEROS[0] 0x58
0x08 TCLK_TRAIL R/W TCLK_TRAIL[3] TCLK_TRAIL[2] TCLK_TRAIL[1] TCLK_TRAIL[0] 0x30
0x09 ANCILLARY_DI R/W ANCILLARY_DI[5] ANCILLARY_ ANCILLARY_DI[3] ANCILLARY_DI[2] ANCILLARY_ ANCILLARY_ 0xC0
DI[4] DI[1] DI[0]
0x0A VBIVIDEO_DI R/W VBIVIDEO_DI[5] VBIVIDEO_DI[4] VBIVIDEO_DI[3] VBIVIDEO_DI[2] VBIVIDEO_DI[1] VBIVIDEO_DI[0] 0xC4
0x0B LSPKT_DI R/W LSPKT_DI[5] LSPKT_DI[4] LSPKT_DI[3] LSPKT_DI[2] LSPKT_DI[1] LSPKT_DI[0] 0x08
0x0C LEPKT_DI R/W LEPKT_DI[5] LEPKT_DI[4] LEPKT_DI[3] LEPKT_DI[2] LEPKT_DI[1] LEPKT_DI[0] 0x0C
0x0D VC_REF R/W VC_REF[1] VC_REF[0] 0x00
0x0E CKSUM_EN R/W CKSUM_EN 0x80
0x1F CSI_FRAME_ R/W FRAMENUMBER_ FBIT_VAL_AT_ 0x40
NUM_CTL INTERLACED FIELD1START_
INTERLACED
0x20 CSI_ R/W LINENUMBER_ 0x00
LINENUMBER_ INCR_
INCR_ INTERLACED
INTERLACED
0x26 ESC_MODE_ R/W ESC_MODE_ ESC_ ESC_MODE_ ESC_ 0x50
CTL EN_D0 XSHUTDOWN_ EN_CLK XSHUTDOWN_
D0 CLK
0xDE DPHY_PWDN_ R/W DPHY_PWDN_ DPHY_PWDN 0x01
CTL OVERRIDE
USER SUB MAP DESCRIPTION
To access all the registers listed in Table 92, SUB_USR_EN[1:0] in Register Address 0x0E must be programmed to 00. The gray shading is the
default.
Table 92. User Sub Map Register Descriptions

User Sub Map Bits1
Addr Register Name Bit Description 7 6 5 4 3 2 1 0 Functionality Comments
0x00 Input control INSEL[4:0]; the INSEL 0 0 0 0 0 CVBS input on AIN1
bits allow the user to 0 0 0 0 1 CVBS input on AIN2
select an input
0 0 0 1 0 CVBS input on AIN3
channel and the input
format 0 0 0 1 1 CVBS input on AIN4
0 1 0 0 0 Y input on AIN1, C input on AIN2
0 1 0 0 1 Y input on AIN3, C input on AIN4
0 1 1 0 0 Y input on AIIN1, Pb input on AIN2,
Pr input on AIN3
0 1 1 1 0 Differential positive on AIN1,
differential negative on AIN2
0 1 1 1 1 Differential positive on AIN3,
differential negative on AIN4
0x01 Video Selection Reserved 0 0 0 Sets to default
1 ENVSPROC 0 Disables VSYNC processor
1 Enables VSYNC processor
Reserved 0 Sets to default
Betacam; enables 0 Standard video input
betacam levels 1 Betacam input enable
ENHSPLL 0 Disables HSYNC processor
1 Enables HSYNC processor
0x02 Video Selection Reserved 0 1 0 0 Sets to default
2 VID_SEL[3:0]; the 0 0 0 0 Autodetects PAL B/PAL G/PAL H/
VID_SEL bits allow the PAL I/PAL D, NTSC J (no pedestal),
user to select the SECAM
input video standard 0 0 0 1 Autodetects PAL B/PAL G/PAL H/
PAL I/PAL D, NTSC M (pedestal),
SECAM
0 0 1 0 Autodetects PAL N (pedestal),
NTSC J (no pedestal), SECAM
0 0 1 1 Autodetects PAL N (pedestal),
NTSC M (pedestal) SECAM
0 1 0 0 NTSC J
0 1 0 1 NTSC M
0 1 1 0 PAL 60
0 1 1 1 NTSC 4.43
1 0 0 0 PAL B/PAL G/PAL H/PAL I/PAL D
1 0 0 1 PAL N = PAL B/PAL G/PAL H/
PAL I/PAL D (with pedestal)
1 0 1 0 PAL M (without pedestal)
1 0 1 1 PAL M
1 1 0 0 PAL Combination N
1 1 0 1 PAL Combination N (with
pedestal)
1 1 1 0 SECAM
1 1 1 1 SECAM
User Sub Map Bits1
0x03 Output control Reserved 0 0 1 1 0 0 Reserved
TOD; tristate output 0 Output drivers enabled See also TIM_OE and TRI_LLC
drivers; this bit allows 1 Output drivers tristated
the user to tristate the
output drivers; pixel
outputs, HS and
VS/FIELD/SFL
VBI_EN; vertical 0 All lines filtered and scaled
blanking interval data 1 Only active video region filtered
enable; allows VBI
data (Line 1 to Line
21) to be passed
through with only a
minimum amount of
filtering performed
0x04 Extended Range; allows the 0 16 ≤ Y ≤ 235, 16 ≤ C/P ≤ 240 ITU-R BT.656
output control user to select the 1 1 ≤ Y ≤ 254, 1 ≤ C/P ≤ 254 Extended range
range of output
values; can be ITU-R
BT.656 compliant or
can fill the whole
accessible number
range
EN_SFL_PIN 0 Disables SFL output SFL output enables encoder
1 Outputs SFL information on the and decoder to be connected
SFL pin directly
BL_C_VBI; blank 0 Decode and output color during
chroma during VBI; if VBI
set, it enables data in 1 Blank Cr and Cb values during VBI
the VBI region to be
passed through the
decoder undistorted
TIM_OE; enables 0 HS and VS/FIELD/SFL tristated Controlled by TOD
timing signals output 1 HS and VS/FIELD/SFL forced active
Reserved 0 1 1
BT.656-4; allows the 0 ITU-R BT.656-3 compatible
user to select an 1 ITU-R BT.656-4 compatible
output mode
compatible with ITU-
R BT.656-3/-4
0x07 Autodetect AD_PAL_EN; PAL B/ 0 Disables
enable PAL D/PAL I/PAL G/ 1 Enables
PAL H autodetect
enable
AD_NTSC_EN; NTSC 0 Disables
autodetect enable 1 Enables
AD_PALM_EN; PAL M 0 Disables
AD_PALN_EN; PAL N 0 Disables
AD_P60_EN; PAL 60 0 Disables
AD_N443_EN; NTSC 0 Disables
4.43 autodetect 1 Enables
enable
User Sub Map Bits1
AD_SECAM_EN; 0 Disables
SECAM autodetect 1 Enables
enable
AD_SEC525_EN; 0 Disables
SECAM 525 1 Enables
autodetect enable
0x08 Contrast CON[7:0]; contrast 1 0 0 0 0 0 0 0 0x00 = 0 gain on luma channel
adjust; this is the user 0x80 = unity gain on luma
control for contrast channel
adjustment
0xFF = 2× gain on luma channel
0x0A Brightness BRI[7:0]; this register 0 0 0 0 0 0 0 0 0x00 = 0 IRE luma channel offset
adjust controls the 0x7F = +30 IRE luma channel
brightness of the offset
video signal
0x80 = −30 IRE luma channel
offset
0x0B Hue adjust HUE[7:0]; this register 0 0 0 0 0 0 0 0 0x00 = 0° chroma phase adjust
contains the value for 0x7F = −90° chroma phase adjust
the color hue
0x80 = +90° chroma phase adjust
adjustment
0x0C Default Value Y DEF_VAL_EN; default 0 Free run mode dependent
value enable on DEF_VAL_AUTO_EN
1 Forces free run mode on
DEF_VAL_AUTO_EN; 0 Disables free run mode When lock is lost, free run mode
default value 1 Enables automatic free run mode can be enabled to output stable
automatic enable timing, clock, and a set color
DEF_Y[5:0]; default 0 0 1 1 0 1 Y[7:0] = (DEF_Y[5:0], 0, 0) Default Y value output in free
value is Y; this register run mode
holds the Y default
value
0x0D Default Value C DEF_C[7:0]; default 0 1 1 1 1 1 0 0 Cr[3:0] = (DEF_C[7:4]), Default Cb/Cr value output in
value is C; the Cr and Cb[3:0] = (DEF_C[3:0]) free run mode; default values
Cb default values are output a blue
defined in this
register
0x0E Analog Devices Reserved 0 0 0 0 0 Sets as default
Control 1 SUB_USR_EN[1:0]; 0 0 Accesses user sub map register
enables user to access space
the Interrupt/VDP 0 1 Accesses the interrupt/VDP sub
Sub map and User map register space
Sub Map 2
1 0 Accesses User Sub Map 2
Reserved 0 Sets as default
0x0F Power Reserved 0 0 0 0 0 Sets to default
management PWRDWN; power- 0 System functional
down places the 1 Powered down
decoder into a full
power-down mode
Reset; chip reset, 0 Normal operation
loads all I2C bits with 1 Starts reset sequence Executing reset takes
default values approximately 2 ms; this bit is
self clearing
User Sub Map Bits1
0x10 Status 1 IN_LOCK X 1 = in lock (now) Provides information about the
(read only) internal status of the decoder
LOST_LOCK X 1 = lost lock (since last read)
FSC_LOCK X 1 = fSC lock (now)
FOLLOW_PW X 1 = peak white AGC mode active
AD_RESULT[2:0]; 0 0 0 NTSC M/NTSC J Detected standard
autodetection result 0 0 1 NTSC 4.43
reports the standard
0 1 0 PAL M
of the input video
0 1 1 PAL 60
1 0 0 PAL B/PAL G/PAL H/PAL I/PAL D
1 0 1 SECAM
1 1 0 PAL Combination N
1 1 1 SECAM 525
COL_KILL X 1 = color kill is active Color kill
0x11 IDENT IDENT[7:0]; provides 0 1 0 0 0 0 1 0 Power-up value = 0x43
(read only) ID on the revision of
the device
0x12 Status 2 MVCS_DET X Rovi color striping detected 1 = detected
(read only) MVCS_T3 X MV color striping type 0 = Type 2, 1 = Type 3
MV_PS_DET X MV pseudosync detected 1 = detected
MV_AGC_DET X MV AGC pulses detected 1 = detected
LL_NSTD X Nonstandard line length 1 = detected
FSC_NSTD X Nonstandard fSC 1 = detected
Reserved X X
0x13 Status 3 INST_HLOCK X 1 = horizontal lock achieved Unfiltered
(read only) Reserved X Reserved
SD_OP_50Hz 0 SD 60 Hz detected SD field rate detect
1 SD 50 Hz detected
Reserved X
FREE_RUN_ACT X 1 = free run mode active
STD_FLD_LEN X 1 = field length standard Correct field length found
Interlaced X 1 = interlaced video detected Field sequence found
PAL_SW_LOCK X 1 = swinging burst detected Reliable swinging burst
sequence
0x14 Analog clamp FREE_RUN_PAT_ 0 0 0 Single color set by DEF_C and
control SEL[2:0] DEF_Y; see the Color Controls
section
0 0 1 100% color bars
0 1 0 Luma ramp
1 0 1 Boundary box
CCLEN; current clamp 0 Current sources switched off
enable allows the 1 Current sources enabled
user to switch off the
current sources in the
analog front
Reserved 0 0 0 Sets to default
User Sub Map Bits1
0x15 Digital Clamp Reserved X X X X Sets to default
Control 1 DCFE; digital clamp 0 Digital clamp on
freeze enable 1 Digital clamp off
DCT[1:0]; digital 0 0 Slow (TC = 1 sec)
clamp timing 0 1 Medium (TC = 0.5 sec)
determines the time
1 0 Fast (TC = 0.1 sec)
constant of the digital
fine clamp circuitry 1 1 TC dependent on video
0x17 Shaping Filter YSFM[4:0]; selects Y 0 0 0 0 0 Autowide notch for poor quality Decoder selects optimum Y
Control 1 shaping filter mode in sources or wideband filter with shaping filter depending on
CVBS-only mode; comb for good quality input CVBS quality
allows the user to 0 0 0 0 1 Autonarrow notch for poor quality
select a wide range of sources or wideband filter with
low-pass/notch filters; comb for good quality input
if either auto mode is
0 0 0 1 0 SVHS 1 If one of these modes is
selected, the decoder
0 0 0 1 1 SVHS 2 selected, the decoder does not
selects the optimum
change filter modes; depending
Y filter depending on 0 0 1 0 0 SVHS 3
on video quality, a fixed filter
the CVBS video 0 0 1 0 1 SVHS 4 response (the one selected) is
source quality (good
0 0 1 1 0 SVHS 5 used for stable and less stable
vs. poor)
0 0 1 1 1 SVHS 6 video sources
0 1 0 0 0 SVHS 7
0 1 0 0 1 SVHS 8
0 1 0 1 0 SVHS 9
0 1 0 1 1 SVHS 10
0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR 601)
1 0 1 0 0 PAL NN1
1 0 1 0 1 PAL NN2
1 0 1 1 0 PAL NN3
1 0 1 1 1 PAL WN1
1 1 0 0 0 PAL WN2
1 1 0 0 1 NTSC NN1
1 1 0 1 0 NTSC NN2
1 1 0 1 1 NTSC NN3
1 1 1 0 0 NTSC WN1
1 1 1 0 1 NTSC WN2
1 1 1 1 0 NTSC WN3
1 1 1 1 1 Reserved
User Sub Map Bits1
CSFM[2:0]: C shaping 0 0 0 Autoselection 1.5 MHz Automatically selects a C filter
filter mode allows 0 0 1 Autoselection 2.17 MHz based on video standard and
selection from a quality
range of low-pass 0 1 0 SH1 Selects a C filter for all video
chrominance filters; if standards and for good and bad
0 1 1 SH2
either auto mode is video
selected, the decoder 1 0 0 SH3
selects the optimum 1 0 1 SH4
C filter depending on 1 1 0 SH5
the CVBS video
1 1 1 Wideband mode
source quality (good
vs. bad); nonauto
settings force a C filter
for all standards and
quality of CVBS video
0x18 Shaping Filter WYSFM[4:0]; 0 0 0 0 0 Reserved, do not use
Control 2 wideband Y shaping 0 0 0 0 1 Reserved, do not use
filter mode allows the
0 0 0 1 0 SVHS 1
user to select which Y
shaping filter is used 0 0 0 1 1 SVHS 2
for the Y component 0 0 1 0 0 SVHS 3
of Y/C, YPrPb, 0 0 1 0 1 SVHS 4
bandwidth input
0 0 1 1 0 SVHS 5
signals; it is also used
when a good quality 0 0 1 1 1 SVHS 6
input CVBS signal is 0 1 0 0 0 SVHS 7
detected; for all other 0 1 0 0 1 SVHS 8
inputs, the Y shaping
filter chosen is 0 1 0 1 0 SVHS 9
controlled by 0 1 0 1 1 SVHS 10
YSFM[4:0] 0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR 601)
1 0 1 0 0 Reserved, do not use
1 1 1 1 1 Reserved, do not use
Reserved 0 0 Sets to default
WYSFMOVR; enables 0 Autoselection of best filter
use of the automatic 1 Manual select filter using
WYSFM filter WYSFM[4:0]
0x19 Comb filter PSFSEL[1:0]; controls 0 0 Narrow
control the signal bandwidth 0 1 Medium
that is fed to the
1 0 Wide
comb filters (PAL)
1 1 Widest
NSFSEL[1:0]; controls 0 0 Narrow
the signal bandwidth 0 1 Medium
that is fed to the
1 0 Medium
comb filters (NTSC)
1 1 Wide
Reserved 1 1 1 1
0x1D Analog Devices Reserved 0 0 0 X X X
Control 2 Reserved 1
TRI_LLC; tristate LLC 0 LLC pin active

driver 1 LLC pin tristated
User Sub Map Bits1
0x27 Pixel delay LTA[1:0]; luma timing 0 0 No delay CVBS mode, LTA[1:0] = 00b;
control adjust allows the user 0 1 Luma one clock (37 ns) late Y/C mode, LTA[1:0] = 01b;
to specify a timing YPrPb mode, LTA[1:0] = 01b
difference between 1 0 Luma two clocks (74 ns) early
chroma and luma 1 1 Luma one clock (37 ns) early
samples
Reserved 0 Sets to 0
CTA[2:0]; chroma 0 0 0 Reserved CVBS mode, CTA[2:0] = 011b;
timing adjust allows a 0 0 1 Chroma + two pixels (early) Y/C mode, CTA[2:0] = 101b;
specified timing YPrPb mode, CTA[2:0] = 110b
0 1 0 Chroma + one pixel (early)
difference between
the luma and chroma 0 1 1 No delay
samples 1 0 0 Chroma − one pixel (late)
1 0 1 Chroma − two pixels (late)
1 1 0 Chroma − three pixels (late)
1 1 1 Reserved
AUTO_PDC_EN; 0 Use values in LTA[1:0] and
automatic CTA[2:0] for delaying
programmed delay luma/chroma
control. automatically
programs the
LTA/CTA values so 1 LTA and CTA values determined
that luma and automatically
chroma are aligned at
the output for all
modes of operation
SWPC; allows the Cr 0 No swapping
and Cb samples to be 1 Swaps the Cr and Cb output
swapped samples
0x2B Misc gain PW_UPD; peak white 0 Updates once per video line Peak white must be enabled;
control update determines 1 Updates once per field see LAGC[2:0]
the rate of gain
Reserved 1 0 0 0 0 Sets to default
CKE; color kill enable 0 Color kill disabled For SECAM color kill, the
allows the color kill 1 Color kill enabled threshold is set at 8%; see
function to be CKILLTHR[2:0]
switched on and off
0x2C AGC mode CAGC[1:0]; chroma 0 0 Manual fixed gain Use CMG[11:0]
control automatic gain 0 1 Uses luma gain for chroma
control selects the
1 0 Automatic gain Based on color burst
basic mode of
operation for the AGC 1 1 Freeze chroma gain
in the chroma path
Reserved 1 1 Sets to 1
LAGC[2:0]; luma 0 0 0 Manual fixed gain Uses LMG[11:8]
automatic gain 0 0 1 AGC peak white algorithm off Blank level to sync tip
control selects the
0 1 0 AGC peak white algorithm on Blank level to sync tip
mode of operation for
the gain control in the 0 1 1 Reserved
luma path 1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Freeze gain
User Sub Map Bits1
0x2D Chroma Gain CMG[11:8]/CG[11:8]; 0 1 0 0 CAGC[1:0] settings decide in
Control 1, in manual mode, the which mode CMG[11:0]
Chroma Gain 1 chroma gain control operates
(CG) can program a
desired manual
chroma gain; in auto
mode, it can read
back the current gain
value
Reserved 1 1 Sets to 1 Has an effect only if CAGC[1:0] is
CAGT[1:0]; chroma 0 0 Slow (TC = 2 sec) set to autogain (10)
automatic gain 0 1 Medium (TC = 1 sec)
timing allows
1 0 Reserved
adjustment of the
chroma AGC tracking 1 1 Adaptive
speed
0x2E Chroma Gain CMG[7:0]/CG[7:0]; 0 0 0 0 0 0 0 0 CMG[11:0] = see the Chroma Gain Minimum value = 0 decimal,
Control 2, chroma manual gain section maximum value =
Chroma Gain 2 lower eight bits; see 4095 decimal
(CG) CMG[11:8]/CG[11:8]
for description
0x2F Luma Gain LMG[11:8]/LG[11:8]; in X X X X LAGC[1:0] settings decide in
Control 1, Luma manual mode, luma which mode LMG[11:8] operates
Gain 1 (LG) gain control can
program a desired
manual luma gain; in
auto mode, it can
read back the actual
gain value used
LAGT[1:0]; luma 0 0 Slow (TC = 2 sec) Has an effect only if LAGC[1:0] is
automatic gain 0 1 Medium (TC = 1 sec) set to autogain (001, 010)
timing allows
1 0 Fast (TC = 0.2 sec)
adjustment of the
luma AGC tracking 1 1 Adaptive
speed
0x30 Luma Gain LMG[7:0]/LG[7:0]; X X X X X X X X LMG[7:0]/LG[7:0]; luma manual Minimum value = 1024 decimal,
Control 2, Luma luma manual gain/ gain/luma gain lower eight bits; Maximum value = 4095 decimal
Gain 2 (LG) luma gain lower eight see LMG[11:8]/LG[11:8] for
bits; see description
LMG[11:8]/LG[11:8]
for description
0x31 VS/FIELD Reserved 0 1 0 Sets to default
Control 1 HVSTIM; horizontal 0 Start of line relative to HSE HSE = HSC end
VSYNC timing; selects 1 Start of line relative to HSB HSB = HS begin
where within a line of
video the VSYNC
signal is asserted
NEWAVMODE; sets 0 EAV/SAV codes generated to suit
the EAV/SAV mode Analog Devices encoders
1 Manual VS/FIELD position
controlled by the Register 0x32,
Register 0x33, and Register 0xE5
to Register 0xEA
Reserved 0 0 0 Sets to default
User Sub Map Bits1
0x32 VS/FIELD Reserved 0 0 0 0 0 1 Sets to default NEWAVMODE bit must be set
Control 2 VSBHE 0 VSYNC signal goes high in the high
middle of the line (even field)
1 VSYNC signal changes state at the
start of the line (even field)
VSBHO 0 VSYNC signal goes high in the
middle of the line (odd field)
start of the line (odd field)
0x33 VS/FIELD Reserved 0 0 0 1 0 0 Sets to default
Control 3 VSEHE 0 VSYNC signal goes low in the NEWAVMODE bit must be set
middle of the line (even field) high
start of the line (even field)
VSEHO 0 VSYNC signal goes low in the
middle of the line (odd field)
start of the line odd field
0x34 HS Position HSE[10:8]; HSYNC end 0 0 0 HSYNC output ends HSE[10:0] Using HSB and HSE, the
Control 1 allows positioning of pixels after the falling edge of position/length of the output
the HSYNC output HSYNC HSYNC can be programmed
within the video line
HSB[10:8]; HSYNC 0 0 0 HS output starts HSB[10:0] pixels
begin allows after the falling edge of HSYNC
positioning of the
HSYNC output within
the video line
0x35 HS Position HSB[7:0]; see Address 0 0 0 0 0 0 1 0
Control 2 0x34, using HSB[10:0]
and HSE[10:0], users
can program the
position and length of
the HSYNC output
signal
0x36 HS Position HSE[7:0]; see 0 0 0 0 0 0 0 0
Control 3 Address 0x35
description
0x37 Polarity PCLK; sets polarity of 0 Inverts polarity
LLC 1 Normal polarity as per the timing
diagrams in the ADV7280A and
ADV7282A data sheets
PF; sets the FIELD 0
polarity
1
Reserved 0
PVS; sets the VSYNC 0 Active high
polarity 1 Active low
PHS; sets HSYNC 0 0 Active high
polarity 1 1 Active low
User Sub Map Bits1
0x38 NTSC comb YCMN[2:0]; luma 0 0 0 Adaptive three-line, three-tap
control comb mode, NTSC luma comb
1 0 0 Disables luma comb; low-
pass/notch filter enabled
1 0 1 Fixed luma comb two-line Top lines of memory
(two taps)
1 1 0 Fixed luma comb three-line (three All lines of memory
taps)
1 1 1 Fixed luma comb two-line Bottom lines of memory
(two taps)
CCMN[2:0]; chroma 0 0 0 Adaptive three-line for CTAPSN =
comb mode, NTSC 01, adaptive four-line for
CTAPSN = 10, adaptive five-line
for CTAPSN = 11
1 0 0 Disables chroma comb
1 0 1 Fixed two-line for CTAPSN = 01, Top lines of memory
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
1 1 0 Fixed three-line for CTAPSN = 01, All lines of memory
fixed four-line for CTAPSN = 10,
fixed five-line for CTAPSN = 11
1 1 1 Fixed two-line for CTAPSN = 01, Bottom lines of memory
fixed three-line for CTAPSN = 10,
fixed four-line for CTAPSN = 11
CTAPSN[1:0]; chroma 0 0 Not used
comb taps, NTSC 0 1 Adapts three lines to two lines
1 0 Adapts five lines to three lines
1 1 Adapts five lines to four lines
0x39 PAL comb YCMP[2:0]; luma 0 0 0 Adaptive five-line, three-tap luma
control comb mode, PAL comb
1 0 0 Disables luma comb; low-
pass/notch filter enabled
1 0 1 Fixed three lines (two taps) luma Top lines of memory
comb (three-line)
1 1 0 Fixed five lines (three taps) luma All lines of memory
comb (five-line)
1 1 1 Fixed three lines (two taps) luma Bottom lines of memory
comb (three-line)
CCMP[2:0]; chroma 0 0 0 Adaptive three-line chroma for
comb mode, PAL CTAPSN = 01, adaptive four-line
chroma for CTAPSN = 10, adaptive
five-line chroma for CTAPSN = 11
1 0 0 Disable chroma comb
1 0 1 Fixed two-line chroma for CTAPSN Top lines of memory
= 01, fixed three-line chroma for
CTAPSN = 10, fixed four-line
chroma for CTAPSN = 11
1 1 0 Fixed three-line chroma for All lines of memory
chroma for CTAPSN = 10, fixed
five-line chroma for CTAPSN = 11
1 1 1 Fixed two-line chroma for CTAPSN Bottom lines of memory
= 01, fixed three-line chroma for
chroma for CTAPSN = 11
User Sub Map Bits1
CTAPSP[1:0]; chroma 0 0 Do not use
comb taps, PAL 0 1 Adapts five lines (three taps) to
three lines (two taps)
1 0 Adapts five lines (five taps) to
three lines (three taps)
1 1 Adapts five lines (five taps) to four
lines (four taps)
0x3A ADC control MUX_PDN_ 0 No control over power-down
OVERRIDE; mux for muxes and associated
power-down override channel circuit
1 Allows power-down of MUX_0P
/MUX_1/MUX_2 and associated
channel circuit; when INSEL[4:0]
is used, unused channels are
automatically powered down
PWRDWN_MUX_2; 0 MUX_2 and associated channel in
enables power-down normal operation
of MUX_2 and 1 Power down MUX_2 and MUX PDN override = 1
associated channel associated channel operation
clamp and buffer
PWRDWN_MUX_1; 0 MUX_1 and associated channel in
enables power-down normal operation
of MUX_1 and 1 Power down MUX_1 and MUX PDN override = 1
clamp and buffer
PWRDWN_MUX_0P; 0 MUX_0P and associated channel
enables power-down in normal operation
of MUX_0P and 1 Power down MUX_0P and MUX PDN override = 1
clamp and buffer
Reserved 0 0 0 0 Sets as default
0x3D Manual Reserved 0 0 1 0 Sets to default
window CKILLTHR[2:0]; color 0 0 0 NTSC, PAL color kill at <0.5%, CKE = 1 enables the color kill
control kill threshold SECAM no color kill function and must be enabled
0 0 1 NTSC, PAL color kill at <1.5%, for CKILLTHR[2:0] to take effect
SECAM color kill at <5%
0 1 0 NTSC, PAL color kill at <2.5%,
0 1 1 NTSC, PAL color kill at <4%,
1 0 0 NTSC, PAL color kill at <8.5%,
SECAM color kill at <9.5%
1 1 1 Reserved
0x41 Resample Reserved 0 0 0 0 0 1 Sets to default
control
SFL_INV; controls the 0 SFL compatible with the Analog
behavior of the PAL Devices video encoders (see the
switch bit SFL_INV, Address 0x41, Bit 6
(ADV7280A Only), User Sub Map
section)
1 SFL compatible with older Analog
Devices video encoders (see the
SFL_INV, Address 0x41, Bit 6
(ADV7280A Only), User Sub Map
section)
User Sub Map Bits1
0x4D CTI DNR CTI_EN; CTI enable 0 Disables CTI
Control 1 1 Enables CTI
CTI_AB_EN; enables 0 Disables CTI alpha blender
the mixing of the 1 Enables CTI alpha blender
transient improved
chroma with the
original signal
CTI_AB[1:0]; controls 0 0 Sharpest mixing between
the behavior of the sharpened/original chroma signal
alpha-blend circuitry 0 1 Sharp mixing between sharpened
and original chroma signal
1 0 Smooth mixing between
sharpened/original chroma signal
1 1 Smoothest mixing between
sharpened and original chroma
signal
DNR_EN; enables or 0 Bypasses the DNRx blocks
bypasses the DNRx 1 Enables the DNRx blocks
blocks
Reserved 1 1 Sets to default
0x4E CTI DNR CTI_C_TH[7:0]; 0 0 0 0 1 0 0 0
Control 2 specifies how big the
amplitude step must
be to be steepened
by the CTI block
0x50 DNR Noise DNR_TH[7:0]; 0 0 0 0 1 0 0 0
Threshold 1 specifies the
maximum luma edge
that is interpreted as
noise and is therefore
blanked
0x51 Lock count CIL[2:0]; count into 0 0 0 One line of video
lock determines the 0 0 1 Two lines of video
number of lines the
0 1 0 Five lines of video
system must remain
in lock before 0 1 1 10 lines of video
showing a locked 1 0 0 100 lines of video
status 1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100,000 lines of video
COL[2:0]; count out of 0 0 0 One line of video
lock determines the 0 0 1 Two lines of video
number of lines the
0 1 0 Five lines of video
system must remain
out-of-lock before 0 1 1 10 lines of video
showing a lost-locked 1 0 0 100 lines of video
status 1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100,000 lines of video
SRLS; select raw lock 0 Over field with vertical info
signal and selects the 1 Line-to-line evaluation
determination of the
lock status
FSCLE; fSC lock enable 0 Lock status set only by horizontal

lock
1 Lock status set by horizontal lock
and subcarrier lock
User Sub Map Bits1
0x5D DIAG1 Control Reserved 0 1 Note that it is recommended
DIAG1_SLICE_ 0 0 0 Set the DIAG1 slice level to 75 mV that the DIAG1 slice level not be
LEVEL[2:0] set to 75 mV, 225 mV, or 375 mV
0 0 1 Set the DIAG1 slice level to
to achieve optimal performance
225 mV
of the ADV7281A and
0 1 0 Set the DIAG1 slice level to ADV7282A devices.
375 mV
525 mV
675 mV
825 mV
975 mV
1 1 1 Set the DIAG1 slice level to 1.125 V
Reserved 1 Reserved
DIAG1_SLICER_ 0 Power up the DIAG1 slicer
PWRDN 1 Power down the DIAG1 slicer
Reserved 0 Reserved
0x5E DIAG2 Control Reserved 0 1 Note that it is recommended
DIAG2_SLICE_ 0 0 0 Set the DIAG2 slice level to 75 mV that the DIAG2 slice level not be
LEVEL[2:0] set to 75 mV, 225 mV, or 375 mV
to achieve optimal performance
225 mV
of the ADV7281A and
0 1 0 Set the DIAG2 slice level to ADV7282A devices.
375 mV
525 mV
675 mV
825 mV
975 mV
1.125 V
Reserved 1 Reserved
DIAG1_SLICER_ 0 Power up the DIAG1 slicer
PWRDN 1 Power down the DIAG1 slicer
Reserved 0 Reserved
0x59 GPO GPO[0] 0 Logic 0 output from GPO0 pin GPO_ENABLE must be set to 1
1 Logic 1 output from GPO0 pin for the GPO outputs to be
enabled. GPO outputs only
GPO[1] 0 Logic 0 output from GPO1 pin
available on ADV7280A-M,
1 Logic 1 output from GPO1 pin ADV7281A-M and
GPO[2] 0 Logic 0 output from GPO2 pin ADV7282A-M models.
1 Logic 1 output from GPO2 pin
Reserved 0 Reserved
GPO_ENABLE 0 GPO pins are tristated
1 GPO pins are enabled
Reserved 0 0 0
User Sub Map Bits1
0x60 ADC Switch 3 MUX_0N[3:0] 0 0 0 0 AINx selection. See Table 11, To enable this control, please
0 0 0 1 Table 12, Table 14, Table 15 for set MAN_MUX_EN = 1. This
specific values control varies in functionality for
0 0 1 0
the ADV7280A, ADV7281A, and
0 0 1 1 ADV7282A. See the Manual
0 1 0 0 Muxing Mode section for more
0 1 0 1 information.
0 1 1 0
0 1 1 1
1 0 0 0
Reserved 0 0 0 1
0x6A Output Sync HS_OUT_SEL[2:0] 0 0 0 The HS pin output horizontal sync
Select 1 selects which sync information.
comes out on the HS 0 0 1 The HS pin outputs vertical sync
pin information.
0 1 0 The HS pin outputs field sync
information.
0 1 1 The HS pin outputs data enable
(DE) information.
1 0 0 The HS pin outputs subcarrier
frequency lock (SFL) information.
Reserved 0 0 0 0 0
0x6B Output Sync FLD_OUT_SEL[2:0] 0 0 0 HS
Select 2 selects which sync 0 0 1 VS
comes out on the
0 1 0 Field sync
VS/FIELD/SFL pin
0 1 1 DE
1 0 0 SFL
Reserved 0 0 0 1 0 Set as default
0x8F Free Run Line Reserved 0 0 0 0 Set as default
Length 1 LLC_PAD_SEL[2:0]; 0 0 0 LLC (nominal 27 MHz) selected
enables manual out on LLC pin
selection of the clock 1 0 1 LLC (nominal 13.5 MHz) selected
for the LLC pin out on LLC pin
0x99 CCAP1 CCAP1[7:0]; closed X X X X X X X X CCAP1[7] contains parity bit for
(read only) caption data register Byte 0
0x9A CCAP2 CCAP2[7:0]; closed X X X X X X X X CCAP2[7] contains parity bit for
(read only) caption data register Byte 0
0x9B Letterbox 1 LB_LCT[7:0]; letterbox X X X X X X X X Reports the number of black lines This feature examines the active
(read only) data register detected at the top of active video video at the start and end of
0x9C Letterbox 2 LB_LCM[7:0]; X X X X X X X X Reports the number of black lines each field; it enables format
(read only) letterbox data register detected in the middle half of detection even if the video is
active video if subtitles are not accompanied by a CGMS or
detected WSS sequence.
0x9D Letterbox 3 LB_LCB[7:0]; letterbox X X X X X X X X Reports the number of black lines

(read only) data register detected at the bottom of active
video
0xB2 CRC enable Reserved 0 0 Sets as default
(write only) CRC_ENABLE; enable 0 Turns off CRC check
CRC checksum to 1 The derivative of CGMS goes high
validate the derivative with valid checksum
of CGMS
Reserved 0 0 0 1 1 Sets as default
User Sub Map Bits1
0xC3 ADC Switch 1 MUX_0P[3:0]; manual 0 0 0 0 AINx selection. See Table 11, To enable this control, set
muxing control for 0 0 0 1 Table 12, Table 14, Table 15 for MAN_MUX_EN = 1. This control
the MUX_0P specific values varies in function for the
0 0 1 0
multiplexor; this ADV7280A, ADV7281A, and
setting controls which 0 0 1 1 ADV7282A. See the Manual
input is routed to the 0 1 0 0 Muxing Mode section for more
ADC for processing 0 1 0 1 information.
0 1 1 0
0 1 1 1
1 0 0 0
MUX_1[3:0]; manual 0 0 0 0 AINx selection. See Table 11, To enable this control, please
muxing control for 0 0 0 1 Table 12, Table 14, Table 15 for set MAN_MUX_EN = 1. This
the MUX_1 specific values control varies in function for the
0 0 1 0
0 1 1 0
0 1 1 1
1 0 0 0
0xC4 ADC Switch 2 MUX_2[3:0]; manual 0 0 0 0 AINx selection. Please see To enable this control, please
muxing control for 0 0 0 1 Table 11, Table 12, Table 14, set MAN_MUX_EN = 1. This
the MUX_2 Table 15 for specific values control varies in function for the
0 0 1 0
0 1 1 0
0 1 1 1
1 0 0 0
Reserved 0 0 0
MAN_MUX_EN; 0 Disables This bit must be set to 1 for
enable manual 1 Enables manual muxing.
setting of input signal
muxing
0xDC Letterbox LB_TH[4:0]; sets the 0 1 1 0 0 Default threshold for the
Control 1 threshold value that detection of black lines
determines if a line is 01101 to 10000—increase
black threshold,
00000 to 01011—decrease
threshold
Reserved 1 0 1 Sets as default
0xDD Letterbox LB_EL[3:0]; programs 1 1 0 0 Letterbox detection ends with the
Control 2 the end line of the last line of active video on a field,
activity window for LB 1100b: 262/525
detection (end of
field)
LB_SL[3:0]; programs 1 1 0 0 Letterbox detection aligned with
the start line of the the start of active video, 0100:
activity window for LB 23/286 NTSC
detection (start of
field)
User Sub Map Bits1
0xDE ST Noise ST_NOISE[10:8] X X X ST noise[10:0] measures the
Readback 1 ST_NOISE_VLD X When = 1, ST_NOISE[10:0] is valid noise on the horizontal sync tip
(read only) of video source
Reserved
0xDF ST Noise ST_NOISE[7:0] X X X X X X X X
Readback 2
(read only)
0xE1 SD offset Cb SD_OFF_Cb[7:0]; 0 0 0 0 0 0 0 0 −312 mV oﬀset applied to the Cb
channel adjusts the hue by channel
selecting the offset 1 0 0 0 0 0 0 0 0 mV offset applied to the Cb
for the Cb channel channel
1 1 1 1 1 1 1 1 +312 mV offset applied to the Cb
channel
0xE2 SD offset Cr SD_OFF_Cr[7:0]; 0 0 0 0 0 0 0 0 −312 mV oﬀset applied to the Cr
channel adjusts the hue by channel
selecting the offset 1 0 0 0 0 0 0 0 0 mV offset applied to the Cr
for the Cr channel channel
1 1 1 1 1 1 1 1 +312 mV offset applied to the Cr
channel
0xE3 SD saturation Cb SD_SAT_Cb[7:0]; 0 0 0 0 0 0 0 0 Gain on Cb channel = −42 dB
channel adjusts the saturation 1 0 0 0 0 0 0 0 Gain on Cb channel = 0 dB
by affecting gain on
1 1 1 1 1 1 1 1 Gain on Cb channel = +6 dB
the Cb channel
0xE4 SD saturation Cr SD_SAT_Cr[7:0]; 0 0 0 0 0 0 0 0 Gain on Cr channel = −42 dB
channel adjusts the saturation 1 0 0 0 0 0 0 0 Gain on Cr channel = 0 dB
by affecting gain on
1 1 1 1 1 1 1 1 Gain on Cr channel = +6 dB
the Cr channel
0xE5 NTSC V bit begin NVBEG[4:0]; number 0 0 1 0 1 NTSC default (ITU-R BT.656)
of lines after line
count rollover to set
VS high
NVBEGSIGN 0 Sets to low when manual
programming
1 Not suitable for user
programming
NVBEGDELE; delay 0 No delay
V bit going high by 1 Additional delay by one line
one line relative to
NVBEG (even field)
NVBEGDELO; delay 0 No delay
NVBEG (odd field)
0xE6 NTSC V bit end NVEND[4:0]; number 0 0 1 0 0 NTSC default (ITU-R BT.656)
of lines after lCOUNT
rollover to set VS low
NVENDSIGN 0 Sets to low when manual
programming
programming
NVENDDELE; delay 0 No delay
V bit going low by 1 Additional delay by one line
NVEND (even field)
NVENDDELO; delay 0 No delay
NVEND (odd field)
User Sub Map Bits1
0xE7 NTSC F bit NFTOG[4:0]; number 0 0 0 1 1 NTSC default
toggle of lines after lCOUNT
rollover to toggle
F signal
NFTOGSIGN 0 Sets to low when manual
programming
programming
NFTOGDELE; delay 0 No delay
F transition by one 1 Additional delay by one line
line relative to NFTOG
(even field)
NFTOGDELO; delay F 0 No delay
transition by one line 1 Additional delay by one line
relative to NFTOG
(odd field)
0xE8 PAL V bit begin PVBEG[4:0]; number 0 0 1 0 1 PAL default (ITU-R BT.656)
of lines after line
VS high
PVBEGSIGN 0 Sets to low when manual
programming
programming
PVBEGDELE; delay 0 No delay
PVBEG (even field)
PVBEGDELO; delay 0 No delay
PVBEG (odd field)
0xE9 PAL V bit end PVEND[4:0]; number 1 0 1 0 0 PAL default (ITU-R BT.656)
of lines after line
VS low.
PVENDSIGN 0 Sets to low when manual
programming
programming
PVENDDELE; delay 0 No delay
PVEND (even field)
PVENDDELO; delay 0 No delay
PVEND (odd field)
0xEA PAL F bit toggle PFTOG[4:0]; number 0 0 0 1 1 PAL default (ITU-R BT.656)
of lines after line
count rollover to
toggle F signal
PFTOGSIGN 0 Sets to low when manual
programming
programming
PFTOGDELE; delay 0 No delay
line relative to PFTOG
(even field)
User Sub Map Bits1
PFTOGDELO; delay 0 No delay
line relative to PFTOG
(odd field)
0xEB Vblank PVBIELCM[1:0]; PAL 0 0 VBI ends one line earlier Controls position of first active
Control 1 VBI even field line (Line 335) (comb filtered) line after VBI on
control even field in PAL
0 1 ITU-R BT.470 compliant (Line 336)
1 0 VBI ends one line later (Line 337)
1 1 VBI ends two lines later (Line 338)
PVBIOLCM[1:0]; PAL 0 0 VBI ends one line earlier (Line 22) Controls position of first active
VBI odd field line 0 1 ITU-R BT.470 compliant (Line 23) (comb filtered) line after VBI on
control odd field in PAL
NVBIELCM[1:0]; NTSC 0 0 VBI ends one line earlier Controls position of first active
VBI even field line (Line 282) (comb filtered) line after VBI on
control 0 1 ITU-R BT.470 compliant (Line 283) even field in NTSC
NVBIOLCM[1:0]; NTSC 0 0 VBI ends one line earlier (Line 20) Controls position of first active
VBI odd field line 0 1 ITU-R BT.470 compliant (Line 21) (comb filtered) line after VBI on
control odd field in NTSC
0xEC Vblank PVBIECCM[1:0]; PAL 0 0 Color output beginning Line 335 Controls the position of first line
Control 2 VBI even field color 0 1 ITU-R BT.470 compliant color that outputs color after VBI on
control output beginning Line 336 even field in PAL
1 0 Color output beginning Line 337
PVBIOCCM[1:0]; PAL 0 0 Color output beginning Line 22 Controls the position of first line
VBI odd field color 0 1 ITU-R BT.470 compliant color that outputs color after VBI on
control output beginning Line 23 odd field in PAL
NVBIECCM[1:0]; NTSC 0 0 Color output beginning Line 282 Controls the position of first line
VBI even field color 0 1 ITU-R BT.470 compliant color that outputs color after VBI on
control output beginning Line 283 even field in NTSC
NVBIOCCM[1:0]; NTSC 0 0 Color output beginning Line 20 Controls the position of first line
VBI odd field color 0 1 ITU-R BT.470 compliant color that outputs color after VBI on
control output beginning Line 21 odd field in NTSC
0xF3 AFE Control 1 AA_FILT_EN[3:0] 0 Antialiasing Filter 1 disabled AA_FILT_MAN_OVR must be
antialiasing filter enabled to change settings
enable defined by INSEL[4:0]
1 Antialiasing Filter 1 enabled
0 Antialiasing Filter 2 disabled
0 Antialiasing Filter 3 disabled
User Sub Map Bits1
AA_FILT_MAN_OVR; 0 Override disabled
antialiasing filter 1 Override enabled
override
Reserved 0 0 0
0xF4 Drive strength DR_STR_S[1:0]; selects 0 0 Low drive strength (1×) The low drive strength
the drive strength for 0 1 Medium low drive strength (2×) settings for DR_STR,
the sync output DR_STR_C, and DR_STR_S are
1 0 Medium high drive strength (3×)
signals not recommended for the
1 1 High drive strength (4×) optimal performance of the
DR_STR_C[1:0]; 0 0 Low drive strength (1×) ADV7281A and ADV7282A
selects the drive 0 1 Medium low drive strength (2×) devices.
strength for the clock
output signal
1 1 High drive strength (4×)
DR_STR[1:0]; selects 0 0 Low drive strength (1×)
the drive strength for 0 1 Medium low drive strength (2×)
the data output
signals; can be
increased or 1 1 High drive strength (4×)
decreased for EMC or
crosstalk reasons
Reserved X
GLITCH_FILT_BYP 0
1
0xF8 IF_COMP_ IFFILTSEL[2:0]; IF filter 0 0 0 Bypass mode 0 dB
CONTROL selection for PAL and
NTSC
2 MHz NTSC filters
0 0 1 −3 dB
0 1 0 −6 dB
0 1 1 −10 dB
1 0 0 Reserved
3 MHz PAL filters
1 0 1 −2 dB
1 1 0 −5 dB
1 1 1 −7 dB
Reserved 0 0 0 0 0
0xF9 VS mode control EXTEND_VS_MAX_ 0 Limits maximum VS frequency to
FREQ 66.25 Hz (475 lines/frame)
1 Limits maximum VS frequency to
70.09 Hz (449 lines/frame)
EXTEND_VS_MIN_ 0 Limits minimum VS frequency to
FREQ 42.75 Hz (731 lines/frame)
1 Limits minimum VS frequency to
39.51 Hz (791 lines/frame)
VS_COAST_ 0 0 Autocoast mode This value forces the video
MODE[1:0] 0 1 576i, 50 Hz coast mode standard output during free run
mode
1 0 480i, 60 Hz coast mode
1 1 Reserved
Reserved 0 0 0 0
0xFB Peaking gain PEAKING_GAIN[7:0]; 0 1 0 0 0 0 0 0 Increases/decreases the gain for
luma peaking gain high frequency portions of the
video signal
0xFC DNR Noise DNR_TH2[7:0] 0 0 0 0 0 1 0 0 Specifies the maximum luma
Threshold 2 edge that is interpreted as noise
and therefore blanked
User Sub Map Bits1
0xFD VPP slave Reserved 0 Reserved
address VPP_SLAVE_ 0 0 0 0 0 0 0 Programs the I2C address of the Applies only to the
ADDR[6:0] video post processor (VPP) map ADV7280A, ADV7280A-M, and
ADV7282A-M models. The VPP
map cannot be accessed when
this register is set to 0x00.
Analog Devices recommended
scripts set this register to 0x84.
0xFE CSI Tx slave Reserved 0 Reserved
address CSI_TX_SLAVE_ 0 0 0 0 0 0 0 Programs the I2C address of the Applies only to the ADV7280A-
ADDR[6:0] MIPI CSI-2 TX map M, ADV7281A-M, and
ADV7282A-M models. The MIPI
CSI-2 TX map cannot be
accessed when this register is
set to 0x00. Analog Devices
recommended script sets this
register to 0x88.
1
USER SUB MAP 2 DESCRIPTION

To access the registers listed in Table 93, SUB_USR_EN[1:0] in Register Address 0x0E, user sub map, must be programmed to 10. The gray
shading is the default.
Table 93. User Sub Map 2 Register Map Descriptions

User Sub Map 2 Bits1
0x80 ACE Control 1 Reserved 0 0 0 0 0 0 0 Reserved.
ACE_ENABLE 0 Disables ACE
1 Enables ACE
0x83 ACE Control 4 ACE_LUMA_GAIN[4:0] 0 1 1 0 1 Set ACE luma autocontrast level to When ACE_ENABLE
default value. is set to 1
5b’00000 minimum value
…
5b’11111 maximum value
Reserved 0 0 0
0x84 ACE Control 5 ACE_CHROMA_GAIN[3:0] 1 0 0 0 Sets ACE color autosaturation level
4b’0000 minimum value
…
4b’1111 maximum value
ACE_CHROMA_MAX[3:0] 1 0 0 0 Sets maximum threshold for ACE
color saturation level
4b’0000 = minimum value
…
4b’1111 = maximum value
0x85 ACE Control 6 ACE_GAMMA_GAIN[3:0] 1 0 0 0 Sets further contrast enhancement
4b’0000 = minimum value
…
4b’1111 = maximum value
ACE_RESPONSE_SPEED[3:0] 1 1 1 1 Set speed of ACE response
4b’0000 slowest value
…
4b’1111 fastest value
0x92 Dither control BR_DITHER_MODE 0 8-bit to 6-bit downdither disabled
1 8-bit to 6-bit downdither enabled
Reserved 0 0 0 0 0 0 0
User Sub Map 2 Bits1
0xD9 MIN_MAX_0 MIN_THRESH_Y[7:0] 0 0 0 0 0 0 0 0 Selects the minimum threshold for
the incoming luma video signal.
0xDA MIN_MAX_1 MAX_THRESH_Y[7:0] 1 1 1 1 1 1 1 1 Selects the maximum threshold for
the incoming luma video signal.
0xDB MIN_MAX_2 MIN_THRESH_C[7:0] 0 0 0 0 0 0 0 0 Selects the minimum threshold for
the incoming chroma video signal.
0xDC MIN_MAX_3 MAX_THRESH_C[7:0] 1 1 1 1 1 1 1 1 Selects the maximum threshold for
the incoming chroma video signal.
0xDD MIN_MAX_4 MAX_SAMPLES_ALLOWED_Y[3:0] 1 1 0 0 Selects the number of maximum
luma samples allowed in a given
window before an interrupt is
triggered.
MIN_SAMPLES_ALLOWED_Y[3:0] 1 1 0 0 Selects the number of minimum
luma samples allowed in a given
triggered.
0xDE MIN_MAX_5 MAX_SAMPLES_ALLOWED_C[3:0] 1 1 0 0 Selects the number of maximum
chroma samples allowed in a given
triggered.
MIN_SAMPLES_ALLOWED_C[3:0] 1 1 0 0 Selects the number of minimum
chroma samples allowed in a given
triggered.
0xE0 FL control FL_ENABLE 0 Fast lock mode not enabled
1 Enables fast lock mode
Reserved 0 0 0 0 0 0 0 See Subaddress
0xE5 for least
significant bits
0xE1 Y Average 0 LINE_START[8:1] 0 0 0 1 0 0 0 1 Selects starting line for field See Subaddress
averaging 0xE5 for least
0xE2 Y Average 1 LINE_END[8:1] 1 0 0 0 1 0 0 0 Selects end line for field averaging significant bits
0xE3 Y Average 2 SAMPLE_START[9:2] 0 0 0 1 0 1 1 1 Selects starting sample for line
averaging
0xE4 Y Average 3 SAMPLE_END[9:2] 1 1 0 1 0 1 1 1 Selects end sample for line
averaging
0xE5 Y Average 4 LINE_START[0] 1
LINE_END[0] 1
Reserved 0 0
SAMPLE_START[1:0] 1 0
SAMPLE_END[1:0] 0 0
0xE6 Y Average 5 CAPTURE_VALUE 0 Trigger that stores the readback
value
Y_AVG_FILT_EN 0 Enable low pass filtering of the y
averaged data
Y_AVG_TIME_CONST[2:0] 1 0 0 Selects the filter cutoff to be used for
filtering the y averaged data.
3’b1xx = least filtered
3’b000 = next least
…
3’b011 = heavily filtered
Reserved 0 0 0 These are read only
bits
0xE7 Y average data Y_AVERAGE[9:2] X X X X X X X X Contains the averaged video data
MSB
0xE8 Y average data Y_AVERAGE[1:0] X X
LSB
1
INTERRUPT/VDP SUB MAP DESCRIPTION
To access the registers listed in Table 94, SUB_USR_EN[1:0] in Register Address 0x0E, user sub map, must be programmed to 01. The gray
shading is the default.
Table 94. Interrupt/VDP Sub Map Register Descriptions

Interrupt/VDP Sub Map Bits1
Address Register Name Bit Description 7 6 5 4 3 2 1 0 Functionality Comments
0x40 Interrupt INTRQ_OP_SEL[1:0]; interrupt 0 0 Open drain
Configuration 1 drive level select 0 1 Drive low when active
1 0 Drive high when active
1 1 Reserved
MPU_STIM_INTRQ; manual 0 Manual interrupt mode disabled
interrupt set mode 1 Manual interrupt mode enabled
Reserved X Not used
MV_INTRQ_SEL[1:0]; Rovi 0 0 Reserved
interrupt select 0 1 Pseudo sync only
1 0 Color stripe only
1 1 Pseudo sync or color stripe
INTRQ_DUR_SEL[1:0]; interrupt 0 0 3 XTAL periods
duration select 0 1 15 XTAL periods
1 0 63 XTAL periods
1 1 Active until cleared
0x42 Interrupt Status 1 SD_LOCK_Q 0 No change These bits can be cleared or
(read only) 1 SD input has caused the masked in Register 0x43
decoder to go from an unlocked and Register 0x44,
state to a locked state respectively
SD_UNLOCK_Q 0 No change
1 SD input has caused the
decoder to go from a locked
state to an unlocked state
Reserved X X X
SD_FR_CHNG_Q 0 No change
1 Denotes a change in the free run
status
MV_PS_CS_Q 0 No change
1 Pseudo sync/color striping
detected; see Register 0x40
MV_INTRQ_SEL[1:0] for
selection
Reserved X
0x43 Interrupt Clear 1 SD_LOCK_CLR 0 Do not clear
(write only) 1 Clears SD_LOCK_Q bit
SD_UNLOCK_CLR 0 Do not clear
1 Clears SD_UNLOCK_Q bit
Reserved 0 0 0 Not used
SD_FR_CHNG_CLR 0 Do not clear
1 Clears SD_FR_CHNG_Q bit
MV_PS_CS_CLR 0 Do not clear
1 Clears MV_PS_CS_Q bit
Reserved X Not used
0x44 Interrupt Mask 1 SD_LOCK_MSK 0 Masks SD_LOCK_Q bit
(read/write) 1 Unmasks SD_LOCK_Q bit
SD_UNLOCK_MSK 0 Masks SD_UNLOCK_Q bit
1 Unmasks SD_UNLOCK_Q bit
SD_FR_CHNG_MSK 0 Masks SD_FR_CHNG_Q bit
1 Unmasks SD_FR_CHNG_Q bit
MV_PS_CS_MSK 0 Masks MV_PS_CS_Q bit
1 Unmasks MV_PS_CS_Q bit
Reserved X Not used
0x45 Raw Status 2 CCAPD 0 No CCAPD data detected— These bits are status bits
(read only) VBI System 2 only; they cannot be
1 CCAPD data detected— cleared or masked; use
VBI System 2 Register 0x46
Reserved X X X
EVEN_FIELD 0 Current SD field is odd
numbered
1 Current SD field is even
numbered
CHX_MIN_MAX_INTRQ 0 If the input to the ADC is within
the correct range this is 0
1 If the input to the ADC is outside
the range, this is set to 1; the
range is set by User Sub Map 2
Reserved X Not used
MPU_STIM_INTRQ 0 MPU_STIM_INTRQ = 0
1 MPU_STIM_INTRQ = 1
0x46 Interrupt Status 2 CCAPD_Q 0 Closed captioning not detected These bits can be cleared or
(read only) in the input video signal—VBI masked by Register 0x47
System 2 and Register 0x48,
1 Closed captioning data respectively; note that the
detected in the video input interrupt in Register 0x46 for
signal—VBI System 2 the CCAP, CGMS, and WSS
data uses the Mode 1 data
Reserved X X X Not used
slicer
SD_FIELD_CHNGD_Q 0 SD signal has not changed field
from odd to even or vice versa
1 SD signal has changed field
from odd to even or vice versa
Reserved X X Not used
MPU_STIM_INTRQ_Q 0 Manual interrupt not set
1 Manual interrupt set
0x47 Interrupt Clear 2 CCAPD_CLR 0 Do not clear—VBI System 2 Note that interrupt in
(write only) 1 Clears CCAPD_Q bit— Register 0x46 for the CCAP,
VBI System 2 CGMS, and WSS data uses
the Mode 1 data slicer
SD_FIELD_CHNGD_CLR 0 Do not clear
1 Clears SD_FIELD_CHNGD_Q bit
CHX_MIN_MAX_INTRQ_CLR 0 Do not clear
1 Clears CHX_MIN_MAX_INTRQ
bit
Reserved X Not used
MPU_STIM_INTRQ_CLR 0 Do not clear
1 Clears MPU_STIM_INTRQ_Q bit
0x48 Interrupt Mask 2 CCAPD_MSK 0 Masks CCAPD_Q bit— The interrupt in
(read/write) VBI System 2 Register 0x46 for the CCAP,
1 Unmasks CCAPD_Q bit— CGMS, and WSS data uses
VBI System 2 the Mode 1 data slicer
SD_FIELD_CHNGD_MSK 0 Masks SD_FIELD_CHNGD_Q bit

1 Unmasks SD_FIELD_CHNGD_
Q bit
CHX_MIN_MAX_INTRQ_MSKB 0 Masks CHX_MIN_MAX_
INTRQ bit
1 Unmasks
CHX_MIN_MAX_INTRQ bit
Reserved 0 Not used
MPU_STIM_INTRQ_MSK 0 Masks MPU_STIM_INTRQ_Q bit
1 Unmasks MPU_STIM_INTRQ_
Q bit
0x49 Raw Status 3 SD_OP_50Hz; SD 60 Hz/50 Hz 0 SD 60 Hz signal output These bits are status bits
(read only) frame rate at output only; they cannot be cleared
1 SD 50 Hz signal output or masked; use
Register 0x4A
SD_V_LOCK 0 SD vertical sync lock is not
established
1 SD vertical sync lock established
SD_H_LOCK 0 SD horizontal sync lock is not
established
1 SD horizontal sync lock
established
Reserved X Not used
SCM_LOCK 0 SECAM lock is not established
1 SECAM lock established
0x4A Interrupt Status 3 SD_OP_CHNG_Q; SD 60 Hz/50 Hz 0 No change in SD signal standard These bits can be cleared
(read only) frame rate at output detected at the output and masked by
Register 0x4B and
Register 0x4C, respectively
1 A change in SD signal standard
is detected at the output
SD_V_LOCK_CHNG_Q 0 No change in SD VSYNC lock
status
1 SD VSYNC lock status has
changed
SD_H_LOCK_CHNG_Q 0 No change in HSYNC lock status
1 SD HSYNC lock status has
changed
SD_AD_CHNG_Q; SD autodetect 0 No change in AD_RESULT[2:0]
changed bits in Status 1 register
1 AD_RESULT[2:0] bits in Status 1
register have changed
SCM_LOCK_CHNG_Q; SECAM 0 No change in SECAM lock status
lock 1 SECAM lock status has changed
PAL_SW_LK_CHNG_Q 0 No change in PAL swinging
burst lock status
1 PAL swinging burst lock status
has changed
0x4B Interrupt Clear 3 SD_OP_CHNG_CLR 0 Do not clear
(write only) 1 Clears SD_OP_CHNG_Q bit
SD_V_LOCK_CHNG_CLR 0 Do not clear
1 Clears SD_V_LOCK_CHNG_Q bit
SD_H_LOCK_CHNG_CLR 0 Do not clear
1 Clears SD_H_LOCK_CHNG_Q bit
SD_AD_CHNG_CLR 0 Do not clear
1 Clears SD_AD_CHNG_Q bit
SCM_LOCK_CHNG_CLR 0 Do not clear
1 Clears SCM_LOCK_CHNG_Q bit
PAL_SW_LK_CHNG_CLR 0 Do not clear
1 Clears PAL_SW_LK_CHNG_Q bit
0x4C Interrupt Mask 3 SD_OP_CHNG_MSK 0 Masks SD_OP_CHNG_Q bit
(read/write) 1 Unmasks SD_OP_CHNG_Q bit
SD_V_LOCK_CHNG_MSK 0 Masks SD_V_LOCK_CHNG_Q bit
1 Unmasks SD_V_LOCK_CHNG_Q
bit
SD_H_LOCK_CHNG_MSK 0 Masks SD_H_LOCK_CHNG_Q bit
1 Unmasks SD_H_LOCK_CHNG_
Q bit
SD_AD_CHNG_MSK 0 Masks SD_AD_CHNG_Q bit
1 Unmasks SD_AD_CHNG_Q bit
SCM_LOCK_CHNG_MSK 0 Masks SCM_LOCK_CHNG_Q bit
1 Unmasks SCM_LOCK_CHNG_
Q bit
PAL_SW_LK_CHNG_MSK 0 Masks PAL_SW_LK_CHNG_Q bit
1 Unmasks PAL_SW_LK_CHNG_
Q bit
0x4E Interrupt Status 4 VDP_CCAPD_Q 0 Closed captioning not detected These bits can be cleared
(read only) and masked by Register
1 Closed captioning detected 0x4F and Register 0x50,
respectively; note that an
Reserved X interrupt in Register 0x4E for
VDP_CGMS_WSS_CHNGD_Q; 0 CGMS/WSS data is not the CCAP, CGMS, and WSS
see Address 0x9C, Bit 4, of user changed/not available data uses the VDP data
sub map to determine whether 1 CGMS/WSS data is slicer
interrupt is issued for a change in changed/available
detected data or for when data is
detected, regardless of content
Reserved X
Reserved X
Reserved X
Reserved X
Reserved X
0x4F Interrupt Clear 4 VDP_CCAPD_CLR 0 Do not clear In Register 0x4E,
(write only) 1 Clears VDP_CCAPD_Q CCAP/CGMS/WSS data uses
VDP data slicer
Reserved 0
VDP_CGMS_WSS_CHNGD_CLR 0 Do not clear
1 Clears
VDP_CGMS_WSS_CHNGD_Q
Reserved 0
Reserved 0
Reserved 0
Reserved 0 Do not clear
Reserved 0
VDP_CCAPD_CLR 0 Do not clear
0x50 Interrupt Mask 4 VDP_CCAPD_MSK 0 Masks VDP_CCAPD_Q Note that an interrupt in
1 Unmasks VDP_CCAPD_Q Register 0x4E for the CCAP,
CGMS, and WSS data uses
Reserved 0
the VDP data slicer
VDP_CGMS_WSS_CHNGD_MSK 0 Masks
1 Unmasks
Reserved 0
Reserved 0
Reserved 0
Reserved 0
Reserved 0
0x51 Interrupt Latch CR_CHANNEL_MAX_VIOLATION 0 Cr value is below programmed This register is cleared by
0 maximum value CHX_MIN_MAX_INTRQ_CLR
(read only)
1 Cr value is above programmed
maximum value
CR_CHANNEL_MIN_VIOLATION 0 Cr value is above programmed
minimum value
1 Cr value is below programmed
minimum value
CB_CHANNEL_MAX_VIOLATION 0 Cb value is below programmed
maximum value
1 Cb value is above programmed
maximum value
CB_CHANNEL_MIN_VIOLATION 0 Cb value is above programmed
minimum value
1 Cb value is below programmed
minimum value
Y_CHANNEL_MAX_VIOLATION 0 Y value is below programmed
maximum value
1 Y value is above programmed
maximum value
Y_CHANNEL_MIN_VIOLATION 0 Y value is above programmed
minimum value
1 Y value is below programmed
minimum value
Reserved 0 0
0x53 Interrupt Reserved X
Status 5 DIAG_TRI1_L1 0 Voltage higher than See DIAG1_SLICE_LEVEL
(read only) DIAG1_SLICE_LEVEL not (user sub map, Register
detected on DIAG1 pin 0x5D [4:2]) and
1 Voltage higher than DIAG2_SLICE_LEVEL (user
DIAG1_SLICE_LEVEL detected sub map, Register 0x5E,
on DIAG1 pin Bits [4:2]). These bits can be
cleared or masked in
Reserved X
Register 0x54 and Register
DIAG_TRI2_L1 0 Voltage higher than 0x55, respectively.
DIAG2_SLICE_LEVEL not
detected on DIAG2 pin
1 Voltage higher than
DIAG2_SLICE_LEVEL detected
on DIAG2 pin
Reserved X X X X
0x54 Interrupt Clear 5 Reserved 0
(write only) DIAG_TRI1_L1_CLR 0 Do not clear DIAG_TRI1_L1
1 Clear DIAG_TRI1_L1
Reserved 0
DIAG_TRI2_L1_CLR 0 Do not clear DIAG_TRI2_L1
1 Clear DIAG_TRI2_L1
Reserved 0 0 0 0
0x55 Interrupt Mask 5 Reserved 0
DIAG_TRI1_L1_MSK 0 Masks DIAG_TRI1_L1
1 Unmasks DIAG_TRI1_L1
Reserved 0
DIAG_TRI2_L1_MSK 0 Masks DIAG_TRI2_L1
1 Unmasks DIAG_TRI2_L1
Reserved 0 0 0 0
0x60 VDP_CONFIG_1 VDP_TTXT_TYPE_MAN[1:0] 0 0 PAL: Teletext-ITU-BT.653-625/
50-A, NTSC: reserved
0 1 PAL: Teletext-ITU-BT.653-625/
50-B (WST), NTSC: Teletext-ITU-
BT.653-525/ 60-B
50-C, NTSC: Teletext-ITU-BT.653-
525/60-C, orEIA516 (NABTS)
50-D, NTSC: Teletext-ITU-BT.653-
525/60-D
VDP_TTXT_TYPE_MAN_ENABLE 0 User programming of teletext
type disabled
1 User programming of teletext
type enabled
WST_PKT_DECODE_DISABLE 0 Enables hamming decoding of
WST packets
1 Disables hamming decoding of
WST packets
Reserved 1 0 0 0
0x62 VDP_ADF_ ADF_DID[4:0] 1 0 1 0 1 User-specified DID sent in the
CONFIG_1 ancillary data stream with VDP
decoded data
ADF_MODE[1:0] 0 0 Nibble mode Sets whether ancillary data
0 1 Byte mode, no code restrictions output mode in byte mode
or nibble mode
1 0 Byte mode with 0x00 and 0xFF
prevented
1 1 Reserved
ADF_ENABLE 0 Disables insertion of VBI
decoded data into ancillary 656
stream
1 Enables insertion of VBI
decoded data into ancillary 656
stream
0x63 VDP_ADF_ ADF_SDID[5:0] 1 0 1 0 1 0 User specified SDID sent in the
CONFIG_2 ancillary data stream with VDP
decoded data
Reserved X
DUPLICATE_ADF 0 Ancillary data packet is spread
across the Y and C data streams
1 Ancillary data packet is
duplicated on the Y and C data
streams
0x64 VDP_LINE_00E VBI_DATA_P318[3:0] 0 0 0 0 Sets VBI standard to be decoded
from Line 318 (PAL), NTSC—not
applicable
Reserved 0 0 0
MAN_LINE_PGM 0 Decode default VDP standards
on the expected lines.
1 Manually program the VBI If set to 1, all
standard to be decoded on each VBI_DATA_Px_Ny bits can
line. be set as desired
0x65 VDP_LINE_00F VBI_DATA_P319_N286[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
from Line 319 (PAL), Line 286 set to 1 for these bits to be
(NTSC) effective
VBI_DATA_P6_N23[3:0] 0 0 0 0 Sets VBI standard to be decoded
from Line 6 (PAL), Line 23 (NTSC)
0x66 VDP_LINE_010 VBI_DATA_P320_N287[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC) effective
0x68 VDP_LINE_012 VBI_DATA_P322[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
from Line 322 (PAL), NTSC—not set to 1 for these bits to be
applicable effective
VBI_DATA_P9[3:0] 0 0 0 0 Sets VBI standard to be decoded
applicable
0x69 VDP_LINE_013 VBI_DATA_P323[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
from Line 323 (PAL), NTSC—not set to 1 for these bits to be
applicable effective
applicable
0x6A VDP_LINE_014 VBI_DATA_P324_N272[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
from Line 11 (PAL); NTSC—not
applicable
0x6B VDP_LINE_015 VBI_DATA_P325_N273[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
from Line 12 (PAL), Line 10
(NTSC)
0x6C VDP_LINE_016 VBI_DATA_P326_N274[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x6D VDP_LINE_017 VBI_DATA_P327_N275[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x6E VDP_LINE_018 VBI_DATA_P328_N276[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x6F VDP_LINE_019 VBI_DATA_P329_N277[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x70 VDP_LINE_01A VBI_DATA_P330_N278[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x71 VDP_LINE_01B VBI_DATA_P331_N279[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x72 VDP_LINE_01C VBI_DATA_P332_N280[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x73 VDP_LINE_01D VBI_DATA_P333_N281[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC)
0x74 VDP_LINE_01E VBI_DATA_P334_N282[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
0x75 VDP_LINE_01F VBI_DATA_P335_N283[3:0] 0 0 0 0 Sets VBI standard to be decoded MAN_LINE_PGM must be
(NTSC) effective
(NTSC) effective
(NTSC) effective
0x78 VDP_STATUS CC_AVL 0 Closed captioning not detected CC_CLEAR resets the
(read only) CC_AVL bit
1 Closed captioning is detected
CC_EVEN_FIELD 0 Closed captioning decoded
from odd field
1 Closed captioning decoded
from even field
CGMS_WSS_AVL 0 CGMS/WSS is not detected CGMS_WSS_CLEAR resets
1 CGMS/WSS detected the CGMS_WSS_AVL bit
Reserved 0 0 0 0
TTXT_AVL 0 Teletext not detected
1 Teletext detected
VDP_STATUS_ CC_CLEAR 0 Does not reinitialize the CCAP This is a self clearing bit
CLEAR readback registers
(write only) 1 Reinitializes the CCAP readback
registers
Reserved 0
CGMS_WSS_CLEAR 0 Does not reinitialize the This is a self clearing bit
CGMS/WSS readback registers
1 Reinitializes the CGMS/WSS
readback registers
Reserved 0 0 0 0 0
0x79 VDP_CCAP_ CCAP_BYTE_1[7:0] X X X X X X X X Decoded Byte 1 of CCAP
DATA_0
(read only)
0x7A VDP_CCAP_ CCAP_BYTE_2[7:0] X X X X X X X X Decoded Byte 2 of CCAP
DATA_1
(read only)
0x7D VDP_CGMS_ CGMS_CRC[5:2] X X X X Decoded CRC sequence for
WSS_DATA_0 CGMS
(read only) Reserved 0 0 0 0
0x7E VDP_CGMS_ CGMS_WSS[13:8] X X X X X X Decoded CGMS/WSS data
WSS_DATA_1 CGMS_CRC[1:0] X X Decoded CRC sequence for
(read only) CGMS
0x7F VDP_CGMS_ CGMS_WSS[7:0] X X X X X X X X Decoded CGMS/WSS data
WSS_DATA_2
(read only)
0x9C VDP_OUTPUT_ Reserved 0 0 0 0
SEL WSS_CGMS_CB_CHANGE 0 Disable content-based updating The available bit shows the
of CGMS and WSS data availability of data only
1 Enable content-based updating when its content has
of CGMS and WSS data changed
Reserved 0 0 0
1
VPP MAP DESCRIPTION
To access the registers listed in Table 95, the user must set the VPP I2C device address by writing to VPP_SLAVE_ADDR[6:0].
VPP_SLAVE_ADDR[6:0] can be found in Register 0xFD, user sub map. Analog Devices recommended scripts set the VPP I2C device address to
0x84. The default bits are indicated by the gray shading.
Table 95. VPP Map Register Descriptions

VPP Map Bits
0x41 DEINT_RESET DEINT_RESET 0
1 Reset the I2P core
Reserved 0 0 0 0 0 0 0 Reserved
0x55 I2C_DEINT_ENABLE Reserved 0 0 0 0 0 0 0 Reserved
I2C_DEINT_ENABLE 0 Disable I2P converter For the I2P converter to operate
1 Enable I2P converter correctly, the
ADV_TIMING_MODE_EN bit must
be set to 1. Changes to the output
timing video are also needed.
Refer to the Analog Devices
recommended scripts.
0x5B ADV_TIMING_MODE_EN Reserved 0 0 0 0 0 0 0 Reserved
ADV_TIMING_MODE_EN 0 Enable advanced timing mode
1 Disable advanced timing Advanced timing mode must be
mode enabled for the I2P converter to
work correctly
MIPI CSI-2 TX MAP DESCRIPTION

To access the registers listed in Table 96, the user must set the CSI I2C device address by writing to CSI_TX_SLAVE_ADDR[6:0].
CSI_TX_SLAVE_ADDR[6:0] can be found in Register 0xFE, user sub map. Analog Devices recommended scripts set the CSI I2C device address
to 0x88. The gray shading indicates the default.
Table 96. MIPI CSI-2 Tx Map Register Descriptions

MIPI CSI-2 Tx Bit
0x00 CSITX_PWRDN Reserved 0 0 0 0 0 0 0 Reserved
CSITX_PWRDN 0 CSI Tx on
1 CSI Tx off
0x01 TLPX Reserved 0 0 0 Reserved
TLPX[4:0] 0 0 0 1 1 These bits set the duration of the For normal operation:
TLPX period of the D0P/D0N MIPI A 1 bit increase results in an increase
Tx data lanes of 37.04 ns
TLPX[4:0]must be greater than or
equal to 2
In I2P mode:
A 1 bit increase results in an increase
of 18.52 ns
TLPX[4:0] must be greater than or
equal to 3
0x02 THSPREP Reserved 0 0 0 Reserved
THSPREP[4:0] 0 0 0 1 1 These bits set the duration of the For normal operation:
THS-PREPARE period of the D0P/D0N A 1 bit increase results in an increase
MIPI Tx data lanes of 37.04 ns
THSPREP[4:0] must be greater than or
equal to 2
In I2P mode:
of 18.52 ns
THSPREP[4:0] must be greater than or
equal to 3
0x03 THSZEROS Reserved 0 0 0 Reserved
MIPI CSI-2 Tx Bit
THSZEROS[4:0] 0 0 1 1 0 These bits set the duration of the For normal operation:
HS-ZERO period of the D0P/D0N A 1 bit increase results in an increase
THSZEROS[4:0]must be greater than
or equal to 4
In I2P mode:
of 18.52 ns
THSZEROS[4:0] must be greater than
or equal to 7
0x04 THSTRAIL Reserved 0 0 0 Reserved
THSTRAIL[4:0] 0 0 1 0 0 These bits set the duration of the For normal operation:
HS-TRAILperiod of the D0P/D0N A 1 bit increase results in an increase
THSTRAIL[4:0] must be greater than or
equal to 3
In I2P mode:
of 18.52 ns
THSTRAIL[4:0] must be greater than or
equal to 4
0x05 THSEXIT Reserved 0 0 0 Reserved
THSEXIT[4:0] 0 0 1 0 1 These bits set the duration of the For normal operation:
HS-EXIT period of the D0P/D0N A 1 bit increase results in an increase
THSEXIT[4:0]must be greater than or
equal to 3
In I2P mode:
of 18.52 ns
THSEXIT[4:0]must be greater than or
equal to 6
0x06 TCLK_PREP Reserved 0 0 0 0 0 Reserved
TCLK_PREP[4:0] 0 1 0 These bits set the duration of the For normal operation:
HS-PREPARE period of the A 1 bit increase results in an increase
CLKP/CLKN MIPI Tx clock lanes. of 37.04 ns
TCLK_PREP[4:0] must be greater than
or equal to 2
In I2P mode:
of 18.52 ns
TCLK_PREP[4:0] must be greater than
or equal to 4
0x07 TCLK_ZEROS Reserved 0 0 0
TCLK_ZEROS[4:0] 0 1 0 1 1 These bits set the duration of the For normal operation:
HS-ZERO period of the A 1 bit increase results in an increase
TCLK_ZEROS[4:0] must be greater
than or equal to 7
In I2P mode:
of 18.52 ns
TCLK_ZEROS[4:0] must be greater
than or equal to 14
MIPI CSI-2 Tx Bit
0x08 TCLK_TRAIL Reserved 0 0 0 0 Reserved
TCLK_TRAIL[3:0] 0 0 1 1 These bits set the duration of the For normal operation:
HS-TRAIL period of the A 1 bit increase results in an increase
TCLK_TRAIL[3:0] must be greater than
or equal to 3
In I2P mode:
of 18.52 ns
TCLK_TRAIL[3:0] must be greater than
or equal to 4
0x09 ANCILLARY_DI Reserved 0 0 Reserved
ANCILLARY_DI 1 1 0 0 0 0 Data type for ancillary data Sets the 6 data type bits used in the
packets. data identifier byte. In this case the
data identifier byte is for ancillary data
packets.
0x0A VBIVIDEO_DI Reserved 0 0
VBIVIDEO_DI 1 1 0 0 0 1 Data type for VBI data packets. Sets the 6 data type bits used in the
data identifier byte. In this case the
data identifier byte is for Vertical
Blanking Interval data packets.
0x0B LSPKT_DI Reserved 0 0 Reserved
LSPKT_DI 0 0 0 0 1 0 Data type for line start packets. Sets the 6 data type bits used in the
data identifier byte is for line start
packets.
0x0C LEPKT_DI Reserved 0 0 Reserved
LEPKT_DI 0 0 0 0 1 1 Data type for line end packets. Sets the 6 data type bits used in the
data identifier byte is for line end
packets.
0x0D VC_REF Reserved 0 0 0 0 0 0 Reserved
VC_REF 0 0 Virtual channel identifier Sets the virtual channel identifier bits
used in Data Identifier bytes. Data
identifier bytes are used in MIPI Tx
data packets.
0x0E CKSUM_EN Reserved 0 0 0 0 0 0 0 Reserved
CKSUM_EN 0 High speed long packet
checksum replaced with 0xFFFF
1 High speed long packet
checksum appended to MIPI Tx
CSI stream
0x1F CSI_FRAME_ Reserved 0 0 0 0 0 0 Reserved
NUM_CTL
FBIT_VAL_AT_ 0 The field number is set to 0 at the Sets frame number used in MIPI Tx
FIELD1START_ start of the first field output. frame start/end packets of first frame.
INTERLACED
1 The field number is set to 1 at the
start of the first field output.
FRAMENUMBER_ 0 Frame number is 1 for odd fields Sets frame number in frame start/end
INTERLACED and 2 for even fields. packets
1 Frame number is 2 for even fields This I2C bit only applies for interlaced
and 1 for odd fields. video.
0x20 CSI_ Reserved 0 0 0 0 0 0 0 Reserved
LINENUMBER_
LINENUMBER_INCR_ 0 Increment line numbers by 2 The line numbers in the line start (LS)
INCR_
INTERLACED (default). and line end (LE) packets for
INTERLACED
interlaced video have to increment by
more than 1. This bit gives the option
of whether line numbers are
incremented in steps of 2 or 3.
1 Increment line numbers by 3. This bit only applies for interlaced
video.
MIPI CSI-2 Tx Bit
0x26 ESC_MODE_CTL Reserved 0 0 0 0 Reserved
ESC_XSHUTDOWN_ 0 These two bits force the MIPI Tx See MIPI CSI-2 Tx Output section for
CLK clock lanes (CLKP and CLKN) to more information.
1
enter and exit the Ultra Low
ESC_MODE_EN_CLK 0 Power State
1
ESC_XSHUTDOWN_ 0 These two bits force the MIPI Tx See MIPI CSI-2 Tx Output section for
D0 data lane (D0P and D0N) to enter more information.
and exit the Ultra Low Power
1
State
ESC_MODE_EN_D0 0
1
0xDE DPHY_PWDN_ DPHY_PWDN 0 MIPI Tx D-PHY Block is not To use this bit, the
CTL powered-down DPHY_PWDN_OVERRIDE bit must be
set to 1.
1 MIPI Tx D-PHY Block is powered-
down
DPHY_PWDN_ 0 Disable manual control of MIPI Tx
OVERRIDE D-PHY powerdown.
1 Enable manual control of MIPI Tx The MIPI Tx D-PHY block can now be
D-PHY powerdown. powered down by using the
DPHY_PWDN bit.
Reserved 0 0 0 0 0 0 Reserved
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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ADV7280A/ADV7281A/ADV7282A Device Manual

ADV7280A/ADV7281A/ADV7282A Functionality and Features

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

VIDEO DECODER MODELS

Table 2. Description of Models of ADV7280A, ADV7281A, and ADV7282A Devices

VIDEO INPUT PINS COLUMN DIAGNOSTIC PINS COLUMN

INTERRUPTS AND STB FUNCTIONALITY

Table 3. DIAG_TRI1_L1_MSK Function Clearing Diagnostic Interrupts

Table 4. DIAG_TRI2_L1_MSK Function Table 7. DIAG_TRI1_L1_CLR Function

When a software interrupt is unmasked and triggered, a hardware

ANALOG FRONT END

manually to correctly route the video from the analog input

is performed by the INSEL[4:0] setting. AIN4

For a full description of the INSEL[4:0] input formats, see the

AIN2 ADC AIN2

Figure 1. Manual Muxing Scheme for ADV7280A ADC

Figure 2. Manual Muxing Scheme for ADV7280A-M

Table 11. Manual Mux Settings for ADC of ADV7280A

Table 12. Manual Mux Settings for ADC of ADV7280A-M

Table 14. Manual Mux Settings for ADC of ADV7282A

FOUR ANALOG INPUTS ARE AVAILABLE ON

–16 When AA_FILT_EN[1] is set to 1, AA Filter 2 is enabled.

1k 10k 100k 1M 10M 100M

1k 10k 100k 1M 10M 100M

Figure 7. Antialiasing Filter Phase Response

GLOBAL CONTROL REGISTERS

GLOBAL STATUS REGISTER

Table 19. Status 1 Function Table 22. AD_RESULT[2:0] Function

MACROVISION VBI DATA STANDARD SLLC

Figure 8. Block Diagram of Video Processor

SELECT THE RAW LOCK SIGNAL

TAKE fSC LOCK INTO ACCOUNT

Figure 9. Lock Related Signal Path

The ADV7280A, ADV7281A, and ADV7282A devices use a

Figure 11. Single-Ended Clamping Overview

Figure 12. Differential Clamping Overview

YES YSFM IN AUTO MODE? NO

Figure 13. YSFM[4:0] and WYSFM[4:0] Control Flowchart

WYSFMOVR, Address 0x18, Bit 7, User Sub Map 01111 SVHS 14

WYSFM[4:0] bits are active only if the WYSFMOVR bit is set to 1.

Shaping Filter section.

Table 38. WYSFM[4:0] Function

00001 Reserved, do not use

00011 SVHS 2 FREQUENCY (MHz)

00100 SVHS 3 Figure 14. Combined Y Antialias, S-VHS Low-Pass Filter,

The CSH filter block can selectively reduce the bandwidth of

–30 Table 39. CSFM[2:0] Function

Figure 20. Differential Input Voltage Divider Network

Figure 21. Gain Control Overview

Luma Gain PW_UPD, Address 0x2B, Bit 0, User Sub Map

CTI_C_TH[7:0], Address 0x4E[7:0], User Sub Map

FILTER RESPONSE (dB)

Figure 23. DNR and Peaking Block Diagram –10

DNR and Peaking –15

DNR_EN, Address 0x4D, Bit 5, User Sub Map

Table 49. DNR_EN Function Figure 24. Peaking Filter Responses

Table 58. CTAPSP[1:0] Function

Table 59. CCMP[2:0] Function  Bypass mode

comb for CTAPSN = 10